Chip test system based on SPI communication protocol

Abstract

The utility model discloses a chip test system based on an SPI communication protocol, and the system comprises a test machine which is used for testing a to-be-tested chip and collecting the test data of the to-be-tested chip; the testing seat is electrically connected with the testing machine and is used for bearing the chip to be tested; the test machine is connected with the to-be-tested chip through an SPI (Serial Peripheral Interface) bus; the SPI bus is in a one-master and multi-slave connection mode, the test machine is a master device, the chip to be tested is a slave device, and the SPI bus comprises a CE wire, an SCLK wire, an SI wire and an SO wire; the one-master multi-slave connection mode includes that one end of the CE line, one end of the SCLK line and one end of the SI line are correspondingly connected with CE signal ports, SCLK signal ports and SI signal ports of the testing machine respectively, and a plurality of branch lines are led out from the other end of the CE line, the other end of the SCLK line and the other end of the SI line and correspondingly connected with CE pins, SCLK pins and SI pins of the chips to be tested respectively. Based on the SPI communication protocol, a plurality of chips share the signal ports, the number of the signal ports required by each chip is reduced, the chip testing efficiency is improved, and the testing cost is saved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the storage particle test technical field, especially a kind of chip test system based on SPI communication protocol. BACKGROUND

[0002] In the chip manufacturing process, testing is a crucial link, especially NOR Flash and NAND Flash and other storage chips, at present, the mainstream chip testing equipment, such as the T5830 testing equipment of the love 8TOM, its test channel quantity is very rich (288 signal ports are provided for each TOM (Tester On Module, testing module) board), allow to test multiple chips simultaneously.

[0003] SPI (Serial Peripheral interface, serial peripheral interface) protocol is the communication protocol commonly used when testing these chips.SPI bus communication protocol usually has a master device and one or more slave devices, needs 4 lines, they are SO (master device data input, slave device data output), SI (master device data output, slave device data input), SCLK (clock signal, generated by master device), CE (chip selection, slave device enable signal, controlled by master device).

[0004] However, the current test method based on SPI communication protocol usually allocates independent CE, SCLK, SI and SO line for each chip, so multiple test channels are needed, and the channel number of testing equipment becomes the bottleneck of limiting the number of tested chips, resulting in high test cost, low test efficiency and other problems. UTILITY MODEL CONTENTS

[0005] The main purpose of the utility model is to propose a kind of chip test system based on SPI communication protocol, to solve the problems of low chip test efficiency and high test cost of existing.

[0006] To achieve the above-mentioned purpose, the utility model provides a kind of chip test system based on SPI communication protocol, the chip test system includes:

[0007] Test machine, test the chip to be tested, and collect the test data of the chip to be tested;

[0008] Test seat, electrically connected to the test machine, for carrying the chip to be tested;

[0009] The test machine is connected with the chip to be tested through SPI bus;

[0010] The SPI bus is a master-slave connection mode, wherein the tester is a master device and the chips to be tested are slave devices, and the SPI bus includes four lines of CE, SCLK, SI and SO.

[0011] The master-slave connection mode includes that one end of the CE, SCLK and SI lines is respectively connected to the CE, SCLK and SI signal ports of the tester, and the other end is connected to a plurality of branches which are respectively connected to the CE, SCLK and SI pins of a plurality of chips to be tested.

[0012] In some embodiments, the master-slave connection mode further includes that one end of the CE line is connected to the CE signal port of the tester, and the other end is connected to a plurality of branches which are respectively connected to the CE pins of a plurality of chips to be tested.

[0013] In some embodiments, the master-slave connection mode further includes that one end of the SCLK line is connected to the SCLK signal port of the tester, and the other end is connected to a plurality of branches which are respectively connected to the SCLK pins of a plurality of chips to be tested.

[0014] In some embodiments, the master-slave connection mode further includes that one end of the SI line is connected to the SI signal port of the tester, and the other end is connected to a plurality of branches which are respectively connected to the SI pins of a plurality of chips to be tested.

[0015] In some embodiments, one end of the SO line is connected to the SO signal port of the tester, and the other end is connected to the SO pin of the chip to be tested, and the number of SO lines is the same as the number of chips to be tested, for outputting test data of each chip to be tested.

[0016] In some embodiments, the chip to be tested includes any one of the following two chips: NOR Flash chip and NAND Flash chip.

[0017] In some embodiments, the number of signal ports of the tester ranges from 288 to 2304.

[0018] In some embodiments, the number of testers ranges from 1 to 8.

[0019] In some embodiments, the tester further includes:

[0020] A power supply module electrically connected to the tester and the test seat for providing electric energy.

[0021] In some embodiments, the power supply module has a plurality of output ports for supplying power to a plurality of testers.

[0022] The utility model discloses technical scheme through the CE, SCLK and SI signal line in sharing SPI agreement, make every chip in the test machine occupies signal port number greatly reduces, thereby can test more chips on a test machine simultaneously, can greatly improve chip test efficiency under the condition of not increasing hardware cost, reduce test time, have remarkable economic benefits. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is structural schematic drawing of one embodiment of the chip test system based on SPI communication protocol of the utility model;

[0024] Figure 2 It is structural schematic drawing of another embodiment of the chip test system based on SPI communication protocol of the utility model;

[0025] Figure 3 It is structural schematic drawing of still another embodiment of the chip test system based on SPI communication protocol of the utility model.

[0026] In the drawing: 1-test machine, 2-test seat, 3-chip, 4-SPI bus, 41-CE line, 42-SCLK line, 43-SI line, 44-SO line, 5-power module. DETAILED DESCRIPTION

[0027] The utility model embodiments will be described below in conjunction with the drawings, obviously, the described embodiment is only a part of the utility model in the embodiment, rather than all the embodiments. Based on the embodiment in the utility model, all other embodiments obtained by the person skilled in the art without making creative labor belong to the range of the utility model protection.

[0028] It should be noted that all directionality instructions (such as up, down, left, right, front, back...) in the utility model embodiment are only used to explain the relative position relationship, movement condition etc. between components in a certain specific posture (such as shown in the drawing), if the specific posture changes, then the directionality instruction also changes accordingly.

[0029] It should be further noted that when an element is referred to as "fixed to" or "set to" another element, it can be directly on another element or there can be a middle element. When an element is referred to as "connected" to another element, it can be directly connected to another element or there can be a middle element.

[0030] In addition, the description of "first", "second" and the like in the utility model is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the same or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first" and "second" can be explicitly or implicitly included at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, also not in the protection scope required by the utility model.

[0031] The utility model provides a chip test system based on SPI communication protocol, refer to Figure 1 The chip test system comprises:

[0032] Test machine 1, test chip 3 is tested, and the test data of the test chip 3 is collected;

[0033] Test seat 2 is electrically connected with the test machine 1 and is used for bearing the test chip 3;

[0034] The test machine 1 is connected with the test chip 3 through SPI bus 4;

[0035] The SPI bus 4 is a master-slave connection mode, wherein the test machine 1 is a master device, and the test chip 3 is a slave device, and the SPI bus 4 includes four lines of CE line 41, SCLK line 42, SI line 42 and SO line 44;

[0036] The master-slave connection mode includes that one end of the CE line 41, the SCLK line 42 and the SI line 43 is connected with the CE, SCLK and SI signal port of the test machine 1 respectively, and the other end leads out several branch lines and is connected with the CE, SCLK and SI pin of several test chips 3 respectively.

[0037] The test seat 2 is electrically connected with the test machine 1 and is used for physically bearing the test chip 3 and ensuring the connection stability of the SPI bus 4. The test seat 2 is designed with the interface corresponding to the pin of the test chip 3, so that the test chip 3 and the signal line of the SPI bus 4 are closely connected during the test process, and the stable transmission of data is ensured.

[0038] The test machine 1 is responsible for testing the test chip 3, and collecting the test data returned from the test chip 3, including performance parameters, error information and the like, to ensure the comprehensiveness and accuracy of the test. By programming the control instruction sent by the test machine 1, the test machine 1 can communicate with each test chip 3 at different time periods, so as to realize the independent test of each chip.

[0039] The SPI bus 4 is used to realize the communication between the tester 1 and the chips 3. The tester 1 is equipped with a plurality of signal ports (for example, there are 288 signal ports on a TOM board of a T5830 test device), and each signal port can be connected with the chips 3 through the SPI bus 4. The SPI bus 4 adopts a master-slave connection mode, and the tester 1 is the master device and the chips 3 are the slave devices. The SPI bus 4 includes four signal lines: a CE line 41 (Chip Enable), an SCLK line 42 (Serial Clock), an SI line 43 (Serial Input) and an SO line 44 (Serial Output). Each signal line transmits a corresponding signal. For example, the CE line 41 transmits a CE signal. The specific connection mode is as follows:

[0040] The CE signal is used to activate a specific chip. One end of the CE line 41 is connected to the CE signal port of the tester 1, and the other end is led out a plurality of branch lines, each of which is connected to the CE pin of a different chip 3.

[0041] The SCLK signal is used to provide a synchronous clock signal to ensure accurate transmission of test data between the tester and the chips. One end of the SCLK line 42 is connected to the SCLK signal port of the tester 1, and the other end is led out a plurality of branch lines, each of which is connected to the SCLK pin of a different chip 3.

[0042] The SI signal is used to send test instructions and parameters from the tester 1 to the chips 3. One end of the SI line 43 is connected to the SI signal port of the tester 1, and the other end is led out a plurality of branch lines, each of which is connected to the SI pin of a different chip 3.

[0043] The SO signal is used to transmit test data from the chips 3 back to the tester. The SO pin of each chip 3 is connected to the SO signal port of the tester 1 through the SO line 44, which is used to collect test results.

[0044] In actual operation, a plurality of chips 3 are controlled through corresponding signals in the CE line 41, the SCLK line 42 and the SI line 43, and each chip 3 transmits SO signals through the SO line 44 to feed back test data individually. According to the number of chips 3 and the requirements of test items, the tester system can flexibly configure the sharing of CE, SCLK and SI signals to reduce the number of signal ports required for each chip.

[0045] When testing, first determine the item to be tested, determine whether the test is a serial test or a parallel test, wherein the serial test includes writing a unique identifier (UNID), and the parallel test includes erasing, programming and reading of the entire chip. According to the proportion of the time occupied by the test item in which all chips can operate together to the total time, determine the number of shared signals (3 signals can be selected to be shared, any 2 signals and any 1 signal) and the number of shared chips (2 chips can be selected to be shared, 3 chips can be selected to be shared, etc.). Balance between improving the parallel test efficiency and avoiding excessive time consumption of the serial test. Then test through the tester 1, and analyze and judge whether the function of the chip to be tested 3 is perfect.

[0046] The method for sharing SPI communication protocol signals of the embodiment can significantly improve the utilization rate of the signal ports of the tester 1, while ensuring the test quality, and can also realize fast data transmission and accurate test result feedback through the SPI communication protocol, thereby meeting the demand of modern electronic equipment for efficient testing.

[0047] In some embodiments, one end of the CE line 41 is connected to the CE signal port of the tester 1 in correspondence, and the other end is led out to be connected to the CE pin of the chip to be tested 3 in correspondence. At this time, for the purpose of selecting to share the CE signal, when the signal sharing is not performed between two chips to be tested 3, 8 signal ports are required, when the CE signal is shared between two chips, 7 signal ports are required, and the average independent signal port requirement of each chip is reduced to 3.5. At this time, 288 signal ports can be used to test 82 chips, which is increased by 13.8% compared with the original 72. In this way, the test system can test more chips at the same time, thereby improving the overall test efficiency. Of course, the number of shared chips can be increased, and the utility model does not limit this.

[0048] In some embodiments, referring to Figure 2 , one end of the SCLK line 42 is connected to the SCLK signal port of the tester 1 in correspondence, and the other end is led out to be connected to the SCLK pin of the chip to be tested 3 in correspondence. At this time, the CE and SCLK signals are selected to be shared between two chips, and the average independent signal port requirement of each chip is reduced to 3. At this time, 288 signal ports can be used to test 96 chips, which is increased by 33.3%. The test efficiency is further improved. Of course, the number of shared chips can be increased, for example, 3 chips share the CE and SCLK signals, and the utility model does not limit this.

[0049] In some embodiments, referring to Figure 3The SI line 43 is connected to the SI signal port of the tester 1 at one end and connected to the SI pin of the chip 3 at the other end. The chips share the CE, SCLK and SI signals. In this case, the number of independent signal ports required by each chip is reduced to 2.5 on average. 288 signal ports can test 115 chips, which is an increase of 59.7%. The test efficiency is further improved. Of course, the number of shared chips can be increased, for example, 3 chips share the CE, SCLK and SO signals, which is not limited by the utility model.

[0050] In some embodiments, the SO line 44 is connected to the SO signal port of the tester 1 at one end and connected to the SO pin of the chip 3 at the other end. The number of SO lines 44 is the same as the number of chips 3, which is used for the output of test data of each chip 3.

[0051] Although the CE, SCLK and SI signals can be shared, the SO signal is used for data return of each chip to ensure that the data return of each chip is not affected, and the SO signal remains independent. At the same time, the data returned through the SO determines the chip that has a problem in the chip 3 under test, so the SO line 44 that transmits the SO signal cannot be reduced in the signal port of the chip tester.

[0052] In some embodiments, the chip 3 under test includes any one of the following two types of chips: NOR Flash chip and NAND Flash chip. NOR Flash and NAND Flash chips usually involve the following three test items during testing: 1. Full chip erase: all data stored in the chip is cleared; 2. Programming (write): data is written to a specific memory cell in the chip; 3. Read: read the stored data from the chip and verify its accuracy. These test items need to be operated on all chips, which usually takes a long time to complete. The above test items can usually be performed in parallel, i.e. simultaneously performing erase, programming or read operations on multiple chips. Specifically, each chip can perform the above test items based on the SPI communication protocol. By processing test items in parallel, the total test time is greatly shortened, and the test efficiency is greatly improved.

[0053] Although most test items can be tested in parallel, some test items can only be tested in series, such as writing a unique identifier (UNID). When sharing the CE, SCLK and SI signals, these serial tests cannot be performed on multiple chips at the same time and must be tested on each chip in sequence. This will result in an increase in time consumption during the serial test phase. The number of shared chips is determined according to the proportion of the time occupied by the test items that can be operated together to the total time.

[0054] For NAND flash and NOR Flash, only the write UNID needs serial test, and the time of test items that can be operated together accounts for a large proportion of the total time.

[0055] The embodiment describes a test method for NAND Flash and NOR Flash chips, which shares signals based on the SPI communication protocol and fully utilizes the parallel test mechanism, greatly improves the test efficiency, and ensures the comprehensiveness and accuracy of the test.

[0056] In some embodiments, the number of signal ports of the test machine 1 ranges from 288 to 2304.

[0057] The number of signal ports determines the number of chips that can be tested at the same time, and the more signal ports a test machine has, the more chips can be tested at the same time.

[0058] In some embodiments, the number of test machines 1 ranges from 1 to 8.

[0059] The more test machines there are, the more chips can be tested at the same time.

[0060] In some embodiments, the test system further comprises:

[0061] The power supply module 5 is electrically connected to the test machine 1 and the test seat 2, and is used to provide electric energy.

[0062] The power supply module 5 supplies power to each test machine 1 and test seat 2, facilitating the control of the opening and closing of the entire chip test system.

[0063] In some embodiments, the power supply module 5 has a plurality of output ports for supplying power to a plurality of test machines 1.

[0064] The technical scheme of the utility model through sharing CE, SCLK and SI signals in SPI protocol, make each chip in the test machine occupies the signal port number greatly reduces, can test more chips on a test machine at the same time, can greatly improve the chip test efficiency, reduce test time under the condition of not increasing hardware cost, have remarkable economic benefits.

[0065] The above merely describes some or preferred embodiments of the present application, neither the text nor the drawings can limit the scope of protection of the present application, any equivalent structural transformation made by using the content of the present application specification and drawings, or direct / indirect application in other related technical fields are included in the scope of protection of the present application.

Claims

1. A chip test system based on SPI communication protocol, characterized in that, The application relates to a test machine and a test seat. The test machine is connected with the test seat through an SPI bus. The SPI bus is a master-slave connection mode, wherein the test machine is a master device and the test chip is a slave device. The SPI bus includes four lines of CE, SCLK, SI and SO. One end of the CE line is connected with the CE signal port of the test machine, and the other end is connected with the CE pin of the test chip. One end of the SCLK line is connected with the SCLK signal port of the test machine, and the other end is connected with the SCLK pin of the test chip.

2. The chip testing system of claim 1, wherein One end of the SI line is connected with the SI signal port of the test machine, and the other end is connected with the SI pin of the test chip.

3. The chip testing system of claim 2, wherein One end of the SO line is connected with the SO signal port of the test machine, and the other end is connected with the SO pin of the test chip.

4. The chip testing system of claim 3, wherein The test chip includes any one of the following two chips: a NOR Flash chip and a NAND Flash chip.

5. The chip testing system according to any one of claims 1 to 4, wherein The number of signal ports of the test machine ranges from 288 to 2304.

6. The system of claim 1, wherein The number of test machines ranges from 1 to 8.

7. The system of claim 1, wherein The application further relates to a power supply module.

8. The system of claim 1, wherein, The power supply module has a plurality of output ports for supplying power to the test machines.

9. The system of claim 1, wherein, ​ ​ 10. The chip testing system of claim 9, wherein, ​

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