Novel electronic paper TFT MIS tube structure

Abstract

The utility model discloses a novel electronic paper TFT MIS tube structure, which relates to the technical field of electronic information and comprises a common electrode plate and an M IS tube. Comprising a gate plate, a GI gate insulating layer covering the gate plate, a semiconductor layer covering the GI gate insulating layer, a source electrode plate and a drain electrode plate located on the semiconductor layer, a PV passivation layer covering the source electrode plate and the drain electrode plate, and a pixel electrode plate located on the uppermost layer, a group of pixel electrode plate VIA bridging holes are formed in the upper end of the source electrode plate, the MIS tube channel plane structure of the novel electronic paper TFTMIS tube structure is in an umbrella shape, the overlapping area of the grid plate and the source electrode plate is greatly reduced by designing the MIS tube channel plane structure to be in the umbrella shape, the Cgsoft coupling capacitance value and the jump of the voltage of the pixel electrode plate are reduced, and the performance of the novel electronic paper TFTMIS tube structure is improved. The degree that the pixel electrode plate is written by mistake is reduced, the electronic paper can display colors and images more accurately, and the color accuracy and the response speed are improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic information technical field, especially a novel electronic paper TFT MIS pipe structure. BACKGROUND

[0002] Electronic paper display is widely used in electronic price tag, reader and other fields due to its eye protection, low power consumption and other characteristics. However, the display effect of electronic paper is largely dependent on the performance of its TFT MIS pipe.

[0003] In the traditional electronic paper TFT MIS pipe structure, the MIS pipe channel structure is usually“I shape”. This structure design has certain limitations, because the gate and the source have a large overlapping area, reaching 268μm 2 , resulting in a large parasitic capacitance Cgs, especially the Cgsoff part, which will cause a large jump of the pixel electrode voltage Vp when the electronic paper module refreshes the picture, denoted as△Vp. The large△Vp value affects the display quality of the electronic paper, and it is difficult to meet the market demand for higher display quality.

[0004] In order to reduce the channel resistance when the MIS pipe is turned on, the MIS pipe structure design needs to overlap a part of the gate and the source, but the parasitic capacitance generated by the overlapping part has an adverse effect on the display effect. In order to ensure the display quality of the electronic paper, it is necessary to minimize the degree of pixel electrode Vp being miswritten, that is, to control△Vp as low as possible.

[0005] Under this background, a novel electronic paper TFT MIS pipe structure design scheme is proposed, aiming to solve the problems existing in the traditional structure and improve the display effect and market competitiveness of the electronic paper. SUMMARY

[0006] (I) Technical problems solved

[0007] In view of the deficiencies of the prior art, the utility model provides a novel electronic paper TFT MIS pipe structure to solve the technical problem of solving the deficiencies of the traditional electronic paper TFT MIS pipe in display quality.

[0008] (II) Technical scheme

[0009] To achieve the above purpose, the utility model realizes through the following technical scheme:

[0010] The novel electronic paper TFT MIS tube structure comprises a common electrode plate and a MIS tube, and comprises, in sequence, a gate plate, a MIS tube channel, a GI gate insulating layer covering the gate plate, a semiconductor layer covering the GI gate insulating layer, a source plate and a drain plate located on the semiconductor layer, a PV passivation layer covering the source plate and the drain plate, and a pixel electrode plate located at the uppermost layer, and a group of pixel electrode plate VIA bridge holes are formed in the upper end of the source plate.

[0011] Preferably, in the MIS tube channel of the novel electronic paper TFT MIS tube structure, the shape of the gate plate is arc-shaped, the shapes of the source plate and the drain plate are strip-shaped, the gate plate is located above the source plate and the drain plate, and the arc-shaped part of the gate plate overlaps the strip-shaped part of the source plate and the drain plate, and the overlapping part forms a gate-source overlap area one and a gate-source overlap area two.

[0012] Preferably, in the MIS tube channel of the novel electronic paper TFT MIS tube structure, the overlapping area of the source plate and the drain plate is 145 μm 2 .

[0013] Preferably, in the MIS tube channel of the novel electronic paper TFT MIS tube structure, the gate plate and the GI gate insulating layer are connected through chemical bonding, the source plate and the drain plate and the semiconductor layer are connected through ohmic contact, the PV passivation layer and the source plate and the drain plate are connected through physical adsorption, and the pixel electrode plate and the PV passivation layer are connected through covalent bond.

[0014] (Three) beneficial effects

[0015] 1. By designing the MIS tube channel plane structure as an umbrella shape, the overlapping area of the gate plate and the source plate is greatly reduced, the Cgsoff coupling capacity and the jump of the pixel electrode plate voltage are reduced, the degree of miswriting of the pixel electrode plate is reduced, the electronic paper can more accurately display colors and images, and the definition, color accuracy and response speed are improved.

[0016] 2. The TFT process of the new design scheme can directly use the traditional 6-film layer design without increasing the mask and the production cycle, and the production cycle and the production cost remain unchanged, and the new design scheme is convenient for popularization and application on the existing production line. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above description is only a summary of the technical scheme of the present application, in order to more clearly understand the technical means of the present application, and the contents of the specification can be implemented, the following will be described in detail with the preferred embodiments of the present application and the accompanying drawings.

[0018] Figure 1A TFT overall structure plane schematic diagram is designed for a traditional electronic paper TFT MIS tube structure;

[0019] Figure 2 An MIS tube gate-source overlapping area schematic diagram is designed for a traditional electronic paper TFT MIS structure;

[0020] Figure 3 A TFT overall structure plane schematic diagram is designed for the utility model;

[0021] Figure 4 An MIS tube gate-source overlapping area schematic diagram is designed for the utility model;

[0022] Figure 5 A gate layer and common electrode plate structure schematic diagram is designed for the utility model;

[0023] Figure 6 A semiconductor layer / ohmic contact layer covers the gate layer structure schematic diagram is designed for the utility model;

[0024] Figure 7 An MIS transistor and common electrode structure schematic diagram is designed for the utility model.

[0025] Legend: 11, source plate; 12, gate plate; 13, pixel electrode plate; 14, pixel electrode plate VIA bridge hole; 15, drain plate; 16, common electrode plate; 17, MIS tube; 18, gate-source overlapping area one; 19, MIS tube channel; 20, gate-source overlapping area two; 21, semiconductor layer. DETAILED DESCRIPTION

[0026] The present detailed description describes a new electronic paper TFT MIS tube structure design, manufacturing and performance characteristics. The new structure aims to solve the shortcomings of traditional electronic paper TFT MIS tube in display quality, through optimizing the channel plane structure, realizing the significant improvement of electronic paper display effect.

[0027] The novel electronic paper TFT MIS tube structure includes a common electrode plate 16 and a MIS tube 17, and a gate plate 12, a GI gate insulation layer, a semiconductor layer 21, a source plate 11 and a drain plate 15, a PV passivation layer, and a pixel electrode plate 13 which are sequentially stacked and connected, the gate plate 12 is the bottommost layer and is made of molybdenum material to provide an input port for the control signal of the whole structure, the GI gate insulation layer is located above the gate plate 12 and is made of silicon nitride material to play an insulating and isolating role and prevent the gate signal from leaking, the semiconductor layer 21 is covered on the GI gate insulation layer and is responsible for the transmission and control of electric charge, the source plate 11 and the drain plate 15 are located above the semiconductor layer 21 and are made of indium tin oxide material to realize the injection and extraction of current, the PV passivation layer is covered on the source plate 11 and the drain plate 15 and is made of silicon dioxide material to protect the internal structure and reduce external interference, the pixel electrode plate 13 is located on the uppermost layer and is made of indium tin oxide material to be connected with an external circuit and realize the output of the signal, the MIS tube channel 19 of the novel structure has a “umbrella-shaped” plane structure, specifically, the gate plate 12 has an arc shape, the source plate 11 and the drain plate 15 have a long strip shape, the gate plate 12 is located above the source plate 11 and the drain plate 15, and the arc-shaped part of the gate plate 12 overlaps with the long strip-shaped part of the source plate 11 and the drain plate 15, compared with the traditional “I-shaped” channel structure, the “umbrella-shaped” design significantly reduces the total area of the gate-source overlap area one 18 and the gate-source overlap area two 20, and a group of pixel electrode plate VIA bridge holes 14 are arranged at the upper end of the source plate 11.

[0028] In the preparation, first, a molybdenum material is deposited on the substrate by a physical vapor deposition (PVD) process to form the gate plate 12, then, a silicon nitride material is deposited on the gate plate 12 by a chemical vapor deposition (CVD) process to form the GI gate insulation layer, then, the semiconductor layer 21 is sequentially deposited on the GI gate insulation layer by using the CVD process again, after that, the indium tin oxide material is deposited on the semiconductor layer 21 by the PVD process to form the source plate 11 and the drain plate 15, the CVD process is continued to be used to deposit the silicon dioxide material on the source plate 11 and the drain plate 15 to form the PV passivation layer, finally, the indium tin oxide material is deposited on the PV passivation layer by the PVD process to form the pixel electrode plate 13, and in the whole manufacturing process, the deposition thickness, uniformity and purity of each layer need to be strictly controlled to ensure the performance and stability of the TFT MIS tube.

[0029] In the “umbrella-shaped” MIS tube channel 19 structure, due to the special shape and relative position relationship of the gate plate 12 and the source plate 11 and the drain plate 15, the total area of the gate-source overlap area one 18 and the gate-source overlap area two 20 is greatly reduced to 145 μm 2 , compared with 268 μm 2, significantly reduces the Cgsoff part of the parasitic capacitance Cgs. The reduction of the gate-source overlap area directly leads to the reduction of the Cgsoff capacitance, according to the calculation formula Cgsoff = (ε·S) / d, where ε (dielectric constant of the dielectric layer) and d (distance between the two metal electrodes) are constants, and reducing S (gate-source overlap area) effectively reduces the Cgsoff capacitance. When the electronic paper module refreshes the picture, due to the reduction of the Cgsoff capacitance, the amount of gate voltage Vgs change ΔVgs coupled to the pixel electrode is greatly reduced, thereby reducing the jump ΔVp of the pixel electrode voltage Vp, improving the stability of the pixel electrode voltage, and significantly improving the display quality of the electronic paper. The process of writing gray scale voltage Vd into the pixel electrode plate 13 of each pixel of the electronic paper TFT through the MIS tube 17 is more accurate, reducing the degree of miswriting of the pixel electrode plate 13, thereby more accurately driving the charged particles of different colors in the Eink paper film to electrophoresis, showing clearer and more accurate colors and images.

[0030] In the traditional electronic paper TFT MIS tube structure, the MIS tube channel 19 structure is "I-shaped". The shape of the gate and the source is relatively simple, the gate-source overlap area is large, reaching 268μm 2 This large overlap area leads to a large Cgsoff capacitance, which easily causes a large jump in the pixel electrode voltage when the electronic paper module refreshes the picture, affecting the display quality. In addition, the "I-shaped" structure has a relatively simple manufacturing process, but has obvious shortcomings in display effect.

[0031] The "umbrella-shaped" design of the new structure effectively reduces the total area of the gate-source overlap area 18 and the gate-source overlap area 20, and reduces the Cgsoff capacitance and the jump of the pixel electrode voltage. Although the manufacturing process of the "umbrella-shaped" structure is relatively complex, it has a significant advantage in improving the display quality, which can meet the demand for high display quality of electronic paper displays on the basis of eye protection, low power consumption and other characteristics.

[0032] The new electronic paper TFT MIS tube structure successfully reduces the gate-source overlap area through innovative "umbrella-shaped" channel design and optimized film layer material selection, improves the stability of the pixel electrode voltage, and significantly improves the display quality of the electronic paper. Without increasing the production cost and production cycle, it provides an effective solution for the development of electronic paper display technology, and has broad market application prospects.

[0033] Finally, it should be noted that: apparently, the above embodiments are merely examples for clearly illustrating the utility model, and are not limited to the implementation. For ordinary skilled in the art, on the basis of the above description, other different forms of changes or variations can be made. Here, it is not necessary and impossible to exhaust all the implementation. The obvious changes or variations derived from it are still within the protection scope of the utility model.

Claims

1. A novel e-paper TFT MIS tube structure, comprising a common electrode plate (16) and a MIS tube (17), characterized in that, The new electronic paper TFT MIS tube structure also comprises a gate plate (12), a MIS tube channel (19), a GI gate insulation layer covering the gate plate (12), a semiconductor layer (21) covering the GI gate insulation layer, a source plate (11) and a drain plate (15) located above the semiconductor layer (21), a PV passivation layer covering the source plate (11) and the drain plate (15), and a pixel electrode plate (13) located at the uppermost layer, and a group of pixel electrode plate VIA bridge holes (14) are formed at the upper end of the source plate (11). The MIS tube channel (19) of the new electronic paper TFT MIS tube structure has a "umbrella-shaped" planar structure.

2. A novel electronic paper TFT MIS tube structure according to claim 1, characterized by: In the MIS tube channel (19) of the new electronic paper TFT MIS tube structure, the shape of the gate plate (12) is arc-shaped, the shape of the source plate (11) and the drain plate (15) is strip-shaped, the gate plate (12) is located above the source plate (11) and the drain plate (15), and the arc-shaped part of the gate plate (12) overlaps with the strip-shaped part of the source plate (11) and the drain plate (15), and the overlapping part forms a gate-source overlap area one (18) and a gate-source overlap area two (20).

3. A novel e-paper TFT MIS tube structure according to claim 2, characterized in that: In the MIS tube channel (19) of the novel electronic paper TFT MIS tube structure, the overlapping area of the source plate (11) and the drain plate (15) is 145 μm 2 .

4. A novel e-paper TFT MIS tube structure according to claim 3, characterized in that: In the MIS tube channel (19) of the new electronic paper TFT MIS tube structure, the gate plate (12) is connected with the GI gate insulation layer through chemical bonding, the source plate (11) and the drain plate (15) are connected with the semiconductor layer (21) through ohmic contact, the PV passivation layer is connected with the source plate (11) and the drain plate (15) through physical adsorption, and the pixel electrode plate (13) is connected with the PV passivation layer through covalent bond.

Images