PWM (Pulse Width Modulation) wave driving circuit device with voltage spike suppression function

Abstract

The utility model discloses a PWM (Pulse Width Modulation) wave drive circuit device with a voltage spike suppression function, and provides a PWM wave drive circuit scheme with the voltage spike suppression function, which is characterized in that for a positive voltage spike, a discharge circuit consisting of an MOS (Metal Oxide Semiconductor) tube and a power resistor is used for absorbing the energy of the positive voltage spike; for a negative voltage peak, a discharge loop composed of a PNP tube and a power resistor is used to absorb the energy of the negative voltage peak. According to the scheme of the utility model, voltage spikes can be effectively suppressed, and the reliability of the PWM wave driving circuit is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to circuit test technical field, especially in a kind of PWM wave drive circuit device with voltage peak suppression function. BACKGROUND

[0002] In the direct current brushless motor control circuit, often need PWM (pulse width modulation) wave signal control motor speed, control method is simple. Because motor is inductive load, when power voltage adjustment (generally for 24V) or speed change, motor coil will inevitably occur induced voltage (will produce positive peak or negative peak, will appear ±50V or so amplitude), peak amplitude is high and will be superimposed on power line or signal line, interfere with external control signal, serious case can damage external control circuit. Thus, it is urgent to protect PWM wave circuit, realize the suppression of voltage peak. SUMMARY

[0003] The utility model provides a kind of PWM wave drive circuit device with voltage peak suppression function, to solve the problem of difficult to suppress voltage peak in prior art to PWM wave drive circuit.

[0004] According to an aspect of the utility model, a kind of PWM wave drive circuit device with voltage peak suppression function is provided, comprising:

[0005] sequentially connected negative voltage peak discharge circuit and positive voltage peak discharge circuit;

[0006] The negative voltage peak discharge circuit includes: resistance R1, R2 and R3 are connected between power supply and triode Q1, and form the direct current bias circuit of triode Q1;Resistance R5, R6 are connected input level Vin and triode Q2, and form the direct current bias circuit of triode Q2;Resistance R3 is connected to the collector of triode Q2;Resistance R4 and diode D1 are the collector load of triode Q1 and output amplified PWM wave drive signal Vout;Diode D2 positive pole is grounded, and negative pole connects diode D1;

[0007] The positive voltage peak discharge circuit includes: MOS tube Q4 and triode Q3;Resistance R7, R8 and diode D4 form the direct current bias circuit of triode Q3;Diode D3 and D5 are the protection diode of MOS tube Q4;Diode D4 positive pole is grounded, and negative pole connects resistance R8;Resistance R9 is connected to the collector of MOS tube Q4 and triode Q3;Resistance R10 is the voltage drop protection resistance of MOS tube Q4;Resistance R11 is the power resistance of MOS tube Q4.

[0008] The device further includes:

[0009] The triode Q1, Q3 is a PNP triode; the triode Q2 is an NPN triode.

[0010] The device further comprises:

[0011] The MOS tube Q4 is an N-type metal-oxide-semiconductor NMOS transistor.

[0012] The device further comprises:

[0013] The diodes D1, D2, D3, D4 and D5 are transient voltage suppression (TVS) diodes.

[0014] The device operates according to the following manner:

[0015] When Vin is high, the triode Q2 is turned on under the voltage division of resistors R5 and R6; the triode Q1 is turned on with current flowing through resistors R1, R2 and R3, and a high-level Vout is outputted through resistor R4 and diode D1;

[0016] When Vin is low, the triode Q2 is turned off, the triode Q1 is turned off, and Vout is low;

[0017] When Vout < Vbr + 0.7, the Vbr is the breakdown voltage of diode D4;

[0018] The diode D4 is turned off, the triode Q3 is turned off, and the MOS tube Q4 is turned off;

[0019] When Vout > Vbr + 0.7,

[0020] The resistor R7 and the diode D4 form a direct current bias circuit of the PNP triode Q3, the diode D4 is first turned on, the triode Q3 is turned on, the voltage on resistor R10 is greater than the turn-on voltage of the MOS tube Q4, the MOS tube Q4 is turned on, the power line passes through the power resistor R11, a large current is instantaneously released, and the positive voltage spike energy in the circuit is quickly absorbed;

[0021] The large current instantaneously released is obtained according to the following manner:

[0022] I = (Vbr + 0.7) / R11.

[0023] The device operates according to the following manner:

[0024] When a negative voltage spike occurs in Vout, the voltage value of Vout is below 0V, at this time, Vin is high, the triode Q1 is turned on, and the Vce voltage is large; the discharge circuit is the triode Q1-resistor R4-diode D1, and the discharge current is large.

[0025] The device further comprises:

[0026] R4 is a power resistor, which prevents excessive current from being generated on the transistor Q1.

[0027] The transistor Q1 is externally provided with a heat dissipation device, which includes a heat dissipation pad for increasing the heat dissipation area of the PCB associated with the transistor Q1 or for contacting the transistor Q1 with the housing of the whole machine.

[0028] The device further comprises:

[0029] When the diode D2 is turned on, a discharge circuit is formed, a discharge current is generated, and a negative voltage spike is accelerated.

[0030] The device further comprises:

[0031] The Vin is an LVTTL level, which is a PWM wave control signal output by an MCU; the Vout is an amplified PWM wave driving signal, which has high voltage and current; and the power voltage is Power.

[0032] The technical scheme of the PWM wave driving circuit with the voltage spike suppression function is provided, for a positive voltage spike, a discharge circuit composed of a MOS tube and a power resistor is used to absorb the energy of the positive voltage spike; and for a negative voltage spike, a discharge circuit composed of a PNP tube and a power resistor is used to absorb the energy of the negative voltage spike.

[0033] The technical scheme of the PWM wave driving circuit with the voltage spike suppression function is provided, for a positive voltage spike, a discharge circuit composed of a MOS tube and a power resistor is used to absorb the energy of the positive voltage spike; and for a negative voltage spike, a discharge circuit composed of a PNP tube and a power resistor is used to absorb the energy of the negative voltage spike. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the specification, and are used to explain the present application together with the embodiments of the present application, and do not constitute a limitation on the present application. In the drawings:

[0035] Figure 1 The PWM wave driving circuit with the voltage spike suppression function in the embodiments of the present application is shown in the schematic diagram. DETAILED DESCRIPTION

[0036] The preferred embodiments of the present application are described below in combination with the drawings, and it should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and do not limit the present application.

[0037] The basic idea of the embodiments of the present application is:

[0038] For a positive voltage spike, a discharge circuit composed of a MOS tube and a power resistor is used to absorb the energy of the positive voltage spike; and for a negative voltage spike, a discharge circuit composed of a PNP tube and a power resistor is used to absorb the energy of the negative voltage spike.

[0039] Figure 1 It is a schematic structural diagram of the PWM wave driving circuit device with voltage peak suppression function in the embodiment of the utility model. Figure 1 As shown in the figure, the PWM wave driving circuit device with voltage peak suppression function comprises:

[0040] a negative voltage peak discharge circuit and a positive voltage peak discharge circuit connected in sequence;

[0041] The negative voltage peak discharge circuit comprises: resistors R1, R2 and R3 connected in series between a power supply and a transistor Q1, forming a direct current bias circuit of the transistor Q1; resistors R5 and R6 connected in series between an input level Vin and a transistor Q2, forming a direct current bias circuit of the transistor Q2; resistor R3 connected in series with a collector of the transistor Q2; resistor R4 and diode D1 serving as a collector load of the transistor Q1 and outputting an amplified PWM wave driving signal Vout; diode D2 with a positive electrode grounded and a negative electrode connected to diode D1;

[0042] The positive voltage peak discharge circuit comprises: a MOS transistor Q4 and a transistor Q3; resistors R7, R8 and diode D4 forming a direct current bias circuit of the transistor Q3; diodes D3 and D5 serving as protection diodes of the MOS transistor Q4; diode D4 with a positive electrode grounded and a negative electrode connected to resistor R8; resistor R9 connected in series with the MOS transistor Q4 and a collector of the transistor Q3; resistor R10 serving as a voltage drop protection resistor of the MOS transistor Q4; and resistor R11 serving as a power resistor of the MOS transistor Q4.

[0043] In the embodiment of the utility model, the transistors Q1 and Q3 are PNP transistors, and the transistor Q2 is an NPN transistor.

[0044] The MOS transistor Q4 is an N-type metal-oxide-semiconductor NMOS transistor.

[0045] The diodes D1, D2, D3, D4 and D5 are transient voltage suppression TVS diodes.

[0046] Resistors R1, R2 and R3 form a direct current bias circuit of the PNP transistor Q1, and resistors R5 and R6 form a direct current bias circuit of the NPN transistor Q2.

[0047] When Vin is a high level, the transistor Q2 is turned on through voltage division of resistors R5 and R6; resistors R1, R2 and R3 have a current, the transistor Q1 is turned on, and a high level is outputted to the outside through R4 and D1, i.e. Vout is a high level. R4 and D1 serve as a collector load of the transistor Q1.

[0048] When Vin is a low level, the transistor Q2 is turned off, the transistor Q1 is turned off, and Vout is a low level.

[0049] When the positive voltage spike is suppressed:

[0050] The breakdown voltage of the TVS tube D4 is Vbr.

[0051] When Vout < Vbr+0.7, at this time, the TVS tube D4 is off, the triode Q3 is off, and the MOS tube Q4 is off.

[0052] The diode D1 is off and does not conduct, protecting the triode Q1.

[0053] When Vout > Vbr+0.7, the resistance R7 and the TVS tube D4 form a direct current bias circuit of the PNP triode Q3.

[0054] The TVS tube D4 is first turned on; the triode Q3 is turned on, so that the voltage on the resistance R10 is greater than the turn-on voltage Vmos_th of the MOS tube Q4; the MOS tube Q4 is turned on, the power supply line passes through the power resistance R11, and a large current is released instantaneously: I=(Vbr+0.7) / R11, quickly absorbing the positive voltage spike energy in the circuit; wherein D3 and D4 are protection TVS tubes of the MOS tube, protecting the MOS tube Q4 from being broken down by high voltage.

[0055] When the negative voltage spike is suppressed:

[0056] The working principle of the triodes Q1 and Q2 is the same as described above. At this time, the positive voltage spike suppression circuit does not work.

[0057] When the negative voltage spike occurs, the Vout voltage value is below 0V, at this time, the triode Q1 is turned on (at this time, Vin is high), and the Vce voltage is also relatively large.

[0058] At this time, the discharge circuit is Q1-R4-D1, and the discharge current is large. R4 is a power resistance that prevents excessive current from being generated on Q1. At this time, the voltage drop of the diode D1 is also large, the Vce of the triode Q1 is also large, and the dissipation power is also large, so the heat dissipation area of Q1 needs to be increased (increase the PCB heat dissipation area or contact the whole machine shell through a heat pad). The TVS tube D2 is also turned on, forming another discharge circuit, generating a large discharge current, and accelerating the suppression of the negative voltage spike.

[0059] In the practical circuit, the signal line has a good absorption effect on the voltage pulse with a maintenance time of us level or more, which has been verified. Moreover, according to the amplitude and maintenance time of the voltage pulse, the parameters of the components can be flexibly selected to maximize the absorption of the voltage spike energy.

[0060] In summary, the technical scheme of the utility model provides a PWM wave driving circuit scheme with voltage peak suppression function, for positive voltage peak, using the discharge circuit composed of MOS tube and power resistor, absorbing positive voltage peak energy, for negative voltage peak, using the discharge circuit composed of PNP tube and power resistor, absorbing negative voltage peak energy, the utility model scheme can effectively suppress voltage peak, improve PWM wave driving circuit reliability.

[0061] Those skilled in the art will understand that the embodiments of the utility model can be provided as a method, a system, or a computer program product. Therefore, the utility model can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the utility model can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk memory and optical memory, etc.) containing computer usable program codes.

[0062] The utility model is described with reference to flow charts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the utility model. It should be understood that each flow and / or block in the flow chart and / or block diagram and the combination of flows and / or blocks in the flow chart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine so that the instructions executed by the processor of the computer or other programmable data processing devices produce a device that realizes the functions specified in the flow chart and / or block diagram. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks

[0063] These computer program instructions can also be stored in a computer readable memory capable of guiding the computer or other programmable data processing devices to work in a specific way, so that the instructions stored in the computer readable memory produce a product including instruction devices that realize the functions specified in the flow chart and / or block diagram. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks

[0064] These computer program instructions can also be loaded into the computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable devices to produce a computer implemented process, so that the instructions executed on the computer or other programmable devices provide steps for realizing the functions specified in the flow chart and / or block diagram. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks

[0065] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

Claims

1. A PWM wave drive circuit device having a voltage spike suppression function, characterized by comprising: a PWM wave drive circuit; a voltage spike suppression circuit; and a control circuit for controlling the PWM wave drive circuit and the voltage spike suppression circuit. The device comprises: a negative voltage spike discharge circuit and a positive voltage spike discharge circuit connected in sequence; the negative voltage spike discharge circuit comprises: resistors R1, R2 and R3 connected in series between a power supply and a transistor Q1, forming a direct current bias circuit of the transistor Q1; resistors R5 and R6 connected in series between an input level Vin and a transistor Q2, forming a direct current bias circuit of the transistor Q2; a resistor R3 connected in series with a collector of the transistor Q2; a resistor R4 and a diode D1 serving as a load for a collector of the transistor Q1 and outputting an amplified PWM wave driving signal Vout; a diode D2 having a positive electrode connected to ground and a negative electrode connected to the diode D1; the positive voltage spike discharge circuit comprises: a MOS transistor Q4 and a transistor Q3; resistors R7, R8 and a diode D4 forming a direct current bias circuit of the transistor Q3; diodes D3 and D5 serving as protection diodes for the MOS transistor Q4; a diode D4 having a positive electrode connected to ground and a negative electrode connected to a resistor R8; a resistor R9 connected in series between the MOS transistor Q4 and a collector of the transistor Q3; a resistor R10 serving as a voltage reduction protection resistor for the MOS transistor Q4; and a resistor R11 serving as a power resistor for the MOS transistor Q4.

2. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, characterized in that, The device further comprises: the transistors Q1 and Q3 are PNP transistors; and the transistor Q2 is an NPN transistor.

3. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, characterized in that, The device further comprises: the MOS transistor Q4 is an N-type metal-oxide-semiconductor (NMOS) transistor.

4. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, characterized in that, The device further comprises: the diodes D1, D2, D3, D4 and D5 are transient voltage suppression (TVS) diodes.

5. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, characterized in that, The device operates according to the following manner: when the Vin is at a high level, the transistor Q2 is turned on under the voltage division of the resistors R5 and R6; the transistor Q1 is turned on with current flowing through the resistors R1, R2 and R3, and the resistor R4 and the diode D1 output a high level Vout to the outside; when the Vin is at a low level, the transistor Q2 is turned off, the transistor Q1 is turned off, and the Vout is at a low level; when Vout < Vbr + 0.7, the Vbr is a breakdown voltage of the diode D4; the diode D4 is turned off, the transistor Q3 is turned off, and the MOS transistor Q4 is turned off; when Vout > Vbr + 0.7, the resistor R7 and the diode D4 form a direct current bias circuit of the PNP transistor Q3, the diode D4 is first turned on, the transistor Q3 is turned on, the voltage on the resistor R10 is greater than the turn-on voltage of the MOS transistor Q4, the MOS transistor Q4 is turned on, the power supply line passes through the power resistor R11, and a large current is instantaneously released to quickly absorb the positive voltage spike energy in the circuit; the large current instantaneously released is obtained according to the following manner: I = (Vbr + 0.7) / R11.

6. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, wherein The device operates according to the following manner: when a negative voltage spike occurs in the Vout, the voltage value of the Vout is below 0V, at this time, the Vin is at a high level, the transistor Q1 is turned on, and the Vce voltage is large; the discharge circuit is the transistor Q1-resistor R4-diode D1, and the discharge current is large.

7. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, wherein The device further comprises: R4 is a power resistor, which prevents excessive current from being generated on the transistor Q1.

8. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, characterized in that, The transistor Q1 externally comprises a heat dissipation device, which includes increasing the heat dissipation area of a PCB related to the transistor Q1 or contacting the transistor Q1 with the housing of the whole machine through a heat conduction pad.

9. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, characterized in that, The device further comprises: When the diode D2 is turned on, a discharge circuit is formed to generate a discharge current to accelerate the suppression of negative voltage spikes.

10. The PWM wave driving circuit device with voltage spike suppression function according to claim 1, characterized in that, The device further comprises: The Vin is an LVTTL level, which is a PWM wave control signal output by an MCU; the Vout is an amplified PWM wave driving signal with high voltage and current; and the power voltage is Power.

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