MOS isolation driving circuit

Abstract

The utility model relates to the technical field of circuit design, in particular to an MOS (Metal Oxide Semiconductor) isolation driving circuit, which comprises a transformer, a first MOS tube and a second MOS tube, the transformer comprises a first coil and a second coil; the first coil comprises a first pin position and a second pin position; the second coil comprises a third pin position and a fourth pin position; a second pin position of the first coil is connected with a drain electrode of the first MOS tube; and the fourth pin of the second coil is connected with the grid electrode of the second MOS tube. According to the utility model, the transformer coupling mode is realized through the electromagnetic induction relation between the two coils of the transformer, and a traditional blocking capacitor is omitted, so that the problem that the amplitude of the output driving voltage changes along with the duty ratio is avoided. Meanwhile, due to the fact that no blocking capacitor exists, the stability of the output voltage only depends on the induction voltage of the primary coil of the transformer, the induction voltage is in proportional relation with the input voltage, and therefore the stability of the driving voltage is ensured and is not affected by the duty ratio.

Description

TECHNICAL FIELD

[0001] The utility model relates to circuit design technical field especially relates to a MOS isolation drive circuit. BACKGROUND

[0002] The traditional MOS isolation drive circuit changes with the duty ratio change because of the direct current isolation capacitor, and the output drive voltage amplitude changes, which influences the drive performance of MOS.

[0003] Therefore, it is urgent to provide a technical scheme to solve the above problems. INVENTION CONTENTS

[0004] In order to solve the above technical problems, the utility model provides a MOS isolation drive circuit.

[0005] A MOS isolation drive circuit, comprising: transformer, first MOS tube and second MOS tube;

[0006] The transformer comprises: first coil and second coil;The first coil comprises: first foot and second foot;The second coil comprises: third foot and fourth foot;

[0007] The second foot of the first coil is connected with the drain of the first MOS tube;

[0008] The fourth foot of the second coil is connected with the gate of the second MOS tube.

[0009] The utility model discloses a MOS isolation drive circuit's beneficial effects are as follows:

[0010] The utility model discloses the transformer coupling mode that realizes through the electromagnetic induction relation between the two coils of transformer, saves the traditional direct current isolation capacitor, thereby avoid the problem that the output drive voltage amplitude changes with the duty ratio change.Simultaneously, because there is no direct current isolation capacitor, the stability of output voltage only depends on the induced voltage of transformer primary coil, and the induced voltage is proportional to input voltage, thereby ensuring the stability of drive voltage, and the influence of duty ratio is not received.

[0011] In an alternative way, further comprising: first diode;

[0012] The cathode of the first diode is connected with the second foot of the first coil and the drain of the first MOS tube respectively.

[0013] In the above optional mode, the introduction of the first diode can protect the first MOS tube, prevent the drain of the first MOS tube from appearing reverse voltage breakdown, and help stabilize the voltage, ensure the safety and reliability of the circuit.

[0014] In an alternative, a second diode is further included;

[0015] The anode of the second diode is connected to the gate of the first MOS tube;

[0016] The cathode of the second diode is connected to the source of the first MOS tube.

[0017] In the above alternative, the second diode prevents negative voltage between the gate and the source of the first MOS tube, protects the first MOS tube from damage caused by excessively high or low voltage, and improves the stability of the circuit.

[0018] In an alternative, a third diode is further included;

[0019] The anode of the third diode is connected to the fourth pin of the second coil and the gate of the second MOS tube, respectively;

[0020] The cathode of the third diode is connected to the source of the second MOS tube.

[0021] In the above alternative, the third diode protects the second MOS tube from excessively high or low gate voltage, ensures correct transmission of the driving signal, and improves the reliability of the circuit.

[0022] In an alternative, a first resistor is further included;

[0023] The first end of the first resistor is connected to the third pin of the second coil;

[0024] The second end of the first resistor is connected to the drain of the second MOS tube.

[0025] In the above alternative, the first resistor helps to limit the current flowing through the second MOS tube, prevents excessive current from passing through the second MOS tube, protects the device, and helps to stabilize the operating point of the circuit, improving the reliability of the circuit.

[0026] In an alternative, a second resistor is further included;

[0027] The first end of the second resistor is connected to the second end of the first resistor and the drain of the second MOS tube, respectively.

[0028] In the above alternative, the second resistor is used in conjunction with the first resistor to further adjust the current and voltage flowing through the second MOS tube, optimize the working state of the second MOS tube, and improve the stability and efficiency of the circuit.

[0029] In an alternative, a third resistor is further included;

[0030] The first end of the third resistor is connected with the fourth pin of the second coil and the anode of the third diode respectively.

[0031] The second end of the third resistor is connected with the gate of the second MOS.

[0032] In the optional mode, the third resistor helps to adjust the gate voltage of the second MOS, protects the second MOS from high gate voltage, and improves the stability and reliability of the circuit.

[0033] In an optional mode, the signal input end is further included.

[0034] The signal input end is connected with the first pin of the first coil, the gate of the first MOS and the anode of the second diode respectively.

[0035] In the optional mode, the signal input end ensures that the PWM driving signal can be correctly transmitted to the first MOS, guarantees the normal operation of the driving circuit, and improves the reliability and response speed of the circuit.

[0036] In an optional mode, the power input end is further included.

[0037] The power input end is connected with the anode of the first diode.

[0038] In the optional mode, the power input end ensures that the circuit can obtain stable power supply through the first diode, guarantees the normal operation of the circuit, and improves the reliability and stability of the circuit.

[0039] In an optional mode, the signal output end is further included.

[0040] The signal output end is connected with the second end of the second resistor.

[0041] In the optional mode, the signal output end ensures the stability and accuracy of the output signal, and helps to improve the performance and reliability of the entire driving circuit, especially for the driving control of the second MOS.

[0042] The above description is only a summary of the technical scheme of the present application, in order to more clearly understand the technical means of the present application, the specific embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0044] Figure 1 A schematic view of a MOS isolation driving circuit according to the present application is shown in the accompanying drawings.

[0045] Reference signs: 1, first coil; 2, second coil; 3, first pin; 4, second pin; 5, third pin; 6, fourth pin; Q1, first MOS tube; Q2, second MOS tube; D1, first diode; D2, second diode; D3, third diode; R1, first resistor; R2, second resistor; R3, third resistor; PWM, signal input end; VCC, power input end; DRV, signal output end. DETAILED DESCRIPTION

[0046] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it is understood that the present application can be embodied in various forms and should not be limited by the embodiments set forth herein.

[0047] Figure 1 A schematic view of a MOS isolation driving circuit according to the present application is shown in the accompanying drawings. Figure 1 As shown, it comprises a transformer, a first MOS tube Q1 and a second MOS tube Q2.

[0048] The transformer comprises a first coil 1 and a second coil 2; the first coil 1 comprises a first pin 3 and a second pin 4; the second coil 2 comprises a third pin 5 and a fourth pin 6.

[0049] The second pin 4 of the first coil 1 is connected with the drain of the first MOS tube Q1.

[0050] The fourth pin 6 of the second coil 2 is connected with the gate of the second MOS tube Q2.

[0051] The transformer is used for coupling the PWM driving signal received by the first coil 1 to the second coil 2 through electromagnetic induction, and ensures that the PWM driving signal is transmitted while being electrically isolated.

[0052] The first terminal 3 and the second terminal 4 are input terminals of the primary side of the transformer, and are used for receiving the PWM driving signal from the signal input terminal PWM and transmitting the PWM driving signal to the first coil 1, so as to affect the voltage induction of the transformer.

[0053] The third terminal 5 and the fourth terminal 6 are terminals of the secondary side of the transformer, and are used for receiving the induced induction voltage from the second coil 2 of the transformer and transmitting the secondary side PWM driving signal.

[0054] The first MOS Q1 is used for controlling the on-off of the input PWM driving signal, and further controlling the voltage application of the primary side of the transformer.

[0055] The second MOS Q2 is used for controlling the on-off of the output PWM driving signal.

[0056] The MOS isolation driving circuit of the utility model, through the electromagnetic induction relation between the two coils of the transformer realizes the transformer coupling mode, has saved the traditional direct current isolation capacitor, thereby avoided the problem that the output driving voltage amplitude changes with the duty ratio. Meanwhile, since there is no direct current isolation capacitor, the stability of the output voltage only depends on the induced voltage of the primary coil of the transformer, the induced voltage is proportional to the input voltage, thereby ensuring the stability of the driving voltage, and the driving voltage is not affected by the duty ratio.

[0057] In an alternative, it further comprises a first diode D1.

[0058] The cathode of the first diode D1 is connected to the second pin 4 of the first coil 1 and the drain of the first MOS Q1, respectively.

[0059] The first diode D1 functions as a voltage limiter and a reset, thereby limiting the voltage. The first diode D1 ensures that the voltage at the drain of the first MOS Q1 does not exceed the voltage of the power supply, and avoids negative voltage between the drain and the source.

[0060] In an alternative, it further comprises a second diode D2.

[0061] The anode of the second diode D2 is connected to the gate of the first MOS Q1.

[0062] The cathode of the second diode D2 is connected to the source of the first MOS Q1.

[0063] The second diode D2 functions as a voltage limiter, limiting the voltage difference between the gate and the source of the first MOS Q1, ensuring that the voltage between the gate and the source of the first MOS Q1 does not exceed a certain value or become negative, thereby protecting the gate of the first MOS Q1 from being damaged.

[0064] In an alternative, it further comprises a third diode D3.

[0065] The anode of the third diode D3 is connected to the fourth pin 6 of the second coil 2 and the gate of the second MOS Q2, respectively.

[0066] The cathode of the third diode D3 is connected to the source of the second MOS Q2.

[0067] The third diode D3 functions as a voltage limiter, limiting the voltage difference between the gate and the source of the second MOS Q2, ensuring that the voltage between the gate and the source of the second MOS Q2 does not exceed a certain value or become negative, thereby protecting the gate of the second MOS Q2 from being damaged.

[0068] In an alternative, it further comprises a first resistor R1.

[0069] The first end of the first resistor R1 is connected to the third pin 5 of the second coil 2.

[0070] The second end of the first resistor R1 is connected to the drain of the second MOS Q2.

[0071] The first resistor R1 functions to limit current and divide voltage, limits the current size between the third terminal 5 of the second coil 2 and the drain of the second MOS tube Q2, and divides voltage according to the resistance value of the first resistor R1. Through current limiting and voltage dividing, the first resistor R1 ensures that appropriate current and voltage are obtained at the drain of the second MOS tube Q2, preventing excessive current or voltage.

[0072] In an alternative way, further comprising: a second resistor R2;

[0073] The first end of the second resistor R2 is connected to the second end of the first resistor R1 and the drain of the second MOS tube Q2, respectively.

[0074] The second resistor R2 further functions to limit current and divide voltage, limits the current transmitted through the second end of the first resistor R1, and divides voltage again according to the resistance value of the second resistor R2. Through further current limiting and voltage dividing, the second resistor R2 ensures that precisely controlled current and voltage are obtained at the drain of the second MOS tube Q2 and subsequent circuits.

[0075] In an alternative way, further comprising: a third resistor R3;

[0076] The first end of the third resistor R3 is connected to the fourth terminal 6 of the second coil 2 and the anode of the third diode D3, respectively.

[0077] The second end of the third resistor R3 is connected to the gate of the second MOS tube Q2.

[0078] The third resistor R3 functions to limit current and control voltage, limits the current transmitted to the gate of the second MOS tube Q2 through the fourth terminal 6 of the second coil 2 or the anode of the third diode D3, and controls voltage according to the resistance value of the third resistor R3. Through current limiting and voltage control, the third resistor R3 ensures that appropriate current and voltage are obtained at the gate of the second MOS tube Q2, preventing excessive current or voltage.

[0079] In an alternative way, further comprising: a signal input end PWM;

[0080] The signal input end PWM is connected to the first terminal 3 of the first coil 1, the gate of the first MOS tube Q1, and the anode of the second diode D2, respectively.

[0081] The signal input end PWM is used to transmit and distribute PWM driving signals, and the signal input end PWM transmits PWM driving signals to the first terminal 3 of the first coil 1, the gate of the first MOS tube Q1, and the anode of the second diode D2 to control the corresponding operation of the above-mentioned components.

[0082] In an alternative, it further comprises a power input terminal VCC.

[0083] The power input terminal VCC is connected to the anode of the first diode D1.

[0084] The power input terminal VCC is used to provide a power voltage, and output the power voltage to the anode of the first diode D1 to provide the required voltage and current.

[0085] In an alternative, it further comprises a signal output terminal DRV.

[0086] The signal output terminal DRV is connected to the second end of the second resistor R2.

[0087] The signal output terminal DRV is used to output a PWM drive signal which is proportional to the input PWM drive signal. The signal output terminal DRV outputs the PWM drive signal received from the second end of the second resistor R2 to an external circuit.

[0088] It should be noted that when the PWM drive signal sent by the signal input terminal PWM is high, the first MOS Q1 is turned on. At this time, the voltage of the PWM drive signal is directly added to the first coil 1 of the transformer, specifically, the first pin 3 is a positive voltage, and the second pin 4 is a negative voltage. According to the working principle of the forward transformer, the second coil 2 of the transformer induces a voltage proportional to the voltage of the first coil 1, that is, the third pin 5 of the second coil 2 is a positive voltage, and the fourth pin 6 is a negative voltage. Since the fourth pin 6 is a negative voltage, the gate voltage of the second MOS Q2 is low, causing the second MOS Q2 to be cut off. At this time, the signal output terminal DRV outputs a voltage proportional to the voltage of the first coil 1, and forms a loop with the third diode D3.

[0089] When the PWM drive signal sent by the signal input terminal PWM is low, the first MOS Q1 is cut off. At this time, the voltages of the first pin 3 and the second pin 4 of the first coil 1 of the transformer are reversed, specifically, the second pin 4 is a positive voltage, and the first pin 3 is a negative voltage. The first diode D1 functions as a clamping and resetting, ensuring that the voltage of the first MOS Q1 does not exceed the voltage of the power input terminal VCC. The second diode D2 functions as a clamping to prevent negative voltage between the source and the gate of the first MOS Q1. According to the working principle of the forward transformer, the induced voltage of the second coil 2 is also reversed, that is, the fourth pin 6 of the second coil 2 is a positive voltage, and the third pin 5 is a negative voltage. Since the fourth pin 6 is a positive voltage, the gate voltage of the second MOS Q2 is high, causing the second MOS Q2 to be turned on. At this time, the voltage between the source and the drain of the second MOS Q2 is 0, and forms a loop with the third diode D3, and the output voltage of the signal output terminal DRV is 0, ensuring the reset of the system.

[0090] Therefore, the design of the above-mentioned circuit can be reset when the PWM driving signal is low, so that the PWM driving signal proportional to the input PWM driving signal can be accurately output again in the next high level period.

[0091] Although the embodiments of the utility model have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the utility model, and the ordinary skilled in the art can change, modify, replace and transform the above-mentioned embodiments within the scope of the utility model.

Claims

1. A MOS isolated driver circuit, characterized by, Comprising: a transformer, a first MOS tube and a second MOS tube; the transformer comprises a first coil and a second coil; the first coil comprises a first pin and a second pin; the second coil comprises a third pin and a fourth pin; the second pin of the first coil is connected with the drain of the first MOS tube; the fourth pin of the second coil is connected with the gate of the second MOS tube.

2. The MOS isolated driver circuit of claim 1, wherein, Further comprising: a first diode; the cathode of the first diode is connected with the second pin of the first coil and the drain of the first MOS tube respectively.

3. The MOS isolated driver circuit of claim 2, wherein, Further comprising: a second diode; the anode of the second diode is connected with the gate of the first MOS tube; the cathode of the second diode is connected with the source of the first MOS tube.

4. The MOS isolated driver circuit of claim 3, wherein, Further comprising: a third diode; the anode of the third diode is connected with the fourth pin of the second coil and the gate of the second MOS tube respectively; the cathode of the third diode is connected with the source of the second MOS tube.

5. The MOS isolated driver circuit of claim 4, wherein, Further comprising: a first resistor; the first end of the first resistor is connected with the third pin of the second coil; the second end of the first resistor is connected with the drain of the second MOS tube.

6. The MOS isolated driver circuit of claim 5, wherein, Further comprising: a second resistor; the first end of the second resistor is connected with the second end of the first resistor and the drain of the second MOS tube respectively.

7. The MOS isolated driver circuit of claim 6, wherein, Further comprising: a third resistor; the first end of the third resistor is connected with the fourth pin of the second coil and the anode of the third diode respectively; the second end of the third resistor is connected with the gate of the second MOS tube.

8. The MOS isolated driver circuit of claim 7, wherein, Further comprising: a signal input end; the signal input end is connected with the first pin of the first coil, the gate of the first MOS tube and the anode of the second diode respectively.

9. The MOS isolated driver circuit of claim 8, wherein, Further comprising: a power input end; the power input end is connected with the anode of the first diode.

10. The MOS isolated driver circuit of claim 9, wherein, Further comprising: a signal output end; the signal output end is connected with the second end of the second resistor.

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