Low-power-consumption RC correction circuit
By introducing a reference voltage generation module, a capacitor array charging module, a comparison module, and a logic circuit module, the problems of complex resistor correction and high power consumption in existing RC correction circuits are solved, and a low-power frequency tuning circuit design is realized.
Patent Information
- Application Number
- CN202422492950.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2034-10-15
AI Technical Summary
Existing RC correction circuits require correction resistors and capacitors during frequency tuning, resulting in complex circuits, high power consumption, and difficulty in achieving accurate time constant adjustment.
The system employs a reference voltage generation module, a capacitor array charging module, a comparison module, an arithmetic capture module, and a logic circuit module. Frequency tuning is achieved by adjusting the charging time of the capacitor array, reducing the need for resistor correction. Dynamic comparators and RS latches are used to achieve correction without static power consumption.
It simplifies the circuit structure, reduces power consumption and design complexity, and enables accurate adjustment of the time constant.
Smart Images
Figure CN223528047U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, and in particular to a low-power RC correction circuit. Background Technology
[0002] For various RC circuits, such as active RC, it is difficult to obtain an accurate time constant when implementing them with integrated circuits. It is necessary to find a way to control the parameter values of the devices in order to adjust the time constant to the required value. This process is called frequency tuning.
[0003] Common frequency tuning circuits such as Figure 1 As shown, the circuit includes a resistor array, a switched capacitor array, a comparator circuit, and a logic control circuit. This circuit requires first calibrating resistor R. The current I flowing through R generates an accurate reference voltage V1. The time it takes for the capacitor to charge to V1 using a mirror current kI characterizes the time constant. The logic control circuit determines whether the capacitor array is too large or too small, controlling the switching of the capacitor array to achieve frequency tuning. However, this frequency tuning circuit requires calibrating the resistors first, then the capacitors, making the circuit relatively complex and requiring improvement. Summary of the Invention
[0004] To reduce the complexity of frequency tuning circuit correction, this application provides a low-power RC correction circuit.
[0005] This application provides a low-power RC correction circuit, which adopts the following technical solution:
[0006] A low-power RC correction circuit includes a reference voltage generation module, a capacitor array charging module, a comparison module, an operation capture module, and a logic circuit module.
[0007] One input terminal of the comparison module is connected to the reference voltage generation module and receives the reference voltage signal. The other input terminal of the comparison module is connected to the capacitor array charging module and receives the charging voltage signal. The output terminal of the comparison module outputs a comparison signal to the operation capture module. The operation capture module outputs an operation capture signal to the logic circuit module. The logic circuit module controls the switching of the capacitor array charging module to adjust the charging time.
[0008] Optionally, the reference voltage generation module includes a power supply, a first current source, and a sampling resistor, wherein the first current source is connected in series with one end of the sampling resistor, and the other end of the sampling resistor is grounded.
[0009] Optionally, the capacitor array charging module includes a second current source and a capacitor array unit, one end of the second current source is electrically connected to the power supply, and the other end of the second current source is connected to the capacitor array unit.
[0010] Optionally, the capacitor array unit comprises a reset tube and a plurality of parallel capacitive charging loops, any of the capacitive charging loops comprising a charging capacitor and a charging switch MOS tube arranged in series.
[0011] Optionally, the comparison module comprises a two-stage full dynamic comparator, a VIN end of the two-stage full dynamic comparator being connected between the first current source and the sampling resistor, and a VIP end of the two-stage full dynamic comparator being connected between the other end of the second current source and the capacitor array unit.
[0012] Optionally, the operation capture module comprises an RS latch.
[0013] In summary, the present application has at least one of the following beneficial technical effects:
[0014] 1. The logic circuit module controls the switch of the capacitor array charging module to adjust the charging time, without a resistance correction circuit and a resistance array, and the deviation of the resistance is corrected by adjusting the capacitor array charging module, only one correction is needed, thus greatly reducing the circuit area and lowering the design complexity. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 is a schematic diagram of a common frequency tuning circuit in the background art.
[0016] Figure 2 is a circuit schematic diagram of the RC correction circuit mainly embodied in the embodiment of the present application.
[0017] Figure 3 is a schematic diagram of the dynamic comparison module mainly embodied in the embodiment of the present application.
[0018] Figure 4 is a schematic diagram of the operation capture module mainly embodied in the embodiment of the present application. DETAILED DESCRIPTION
[0019] The embodiments of the present application are described in detail below, examples of the embodiments being shown in the accompanying drawings. Figures 1-4
[0020] In the description of the present application, the description of the terms "certain embodiments", "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present description, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0021] The embodiment of the application discloses a low-power RC correction circuit Figure 2 , comprising a reference voltage generation module, a capacitor array charging module, a dynamic comparison module, an operation capture module and a logic circuit module.
[0022] An input end of the dynamic comparison module is connected with the reference voltage generation module and receives a reference voltage signal, another input end of the dynamic comparison module is connected with the capacitor array charging module and receives a charging voltage signal, an output end of the dynamic comparison module outputs a comparison signal to the operation capture module, the operation capture module outputs an operation capture signal to the logic circuit module, and the logic circuit module controls a switch of the capacitor array charging module to adjust a charging time.
[0023] I2 and I1 are in a mirror ratio relationship, I2 = n * I1, RL is a common resistor without correction, and the function of RL is to generate a reference voltage Vref, Vref will fluctuate with the fluctuation of R, Vin is obtained by charging the capacitor array by I2, the time constant is characterized by the time of charging the capacitor array to Vref by I2, the latch output Vout is sent to the logic circuit, and then the logic circuit judges and controls the switch of the capacitor array to adjust the charging time, so that the frequency tuning purpose is achieved. The scheme does not need to correct the resistor, and the fluctuation of RC is compensated by adjusting the capacitor array.
[0024] The reference voltage generation module comprises a power supply, a first current source and a sampling resistor, the first current source is connected in series with one end of the sampling resistor, and the other end of the sampling resistor is grounded.
[0025] The capacitor array charging module comprises a second current source and a capacitor array unit, one end of the second current source is electrically connected with the power supply, and the other end of the second current source is connected with the capacitor array unit.
[0026] The capacitor array unit comprises a reset tube and a plurality of parallelly connected capacitor charging loops, any capacitor charging loop comprises a charging capacitor and a charging switch MOS tube arranged in series. The reset tube resets once every time the logic circuit sends a code, so that the charge on the capacitor array is completely discharged, and then the capacitor array is charged again, and the above process is repeated.
[0027] Refer to Figure 2 and Figure 3 The comparison module comprises two-stage full-dynamic comparators, a VIN end of the two-stage full-dynamic comparators is connected between the first current source and the sampling resistor, and a VIP end of the two-stage full-dynamic comparators is connected between the other end of the second current source and the capacitor array unit. The dynamic comparator is used, no static power consumption, the clock period is known, and every period, the dynamic comparator samples Vin, the charging time of the capacitor array is obtained by counting the number of sampling periods when the comparator flips.
[0028] Reset stage: CLK is low, CLKB is high, OIN and OIP are pulled up by M3 and M4, M7 and M8 are off, O2P and O2N are forced to be low.
[0029] Comparison stage: CLK is high, CLKB is low, M11 and M12 are off, M0 is on, OIN and OIP are both pulled down, if VIP>VIN, then OIN
[0030] Reference Figure 4 , the operation capture module includes an RS latch, which latches the comparator output after the comparator flips and gives the voltage shaping to the logic circuit module. Its truth table is shown as follows:
[0031]
[0032] Although the embodiments of the present application have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and modifications to the above-mentioned embodiments within the scope of the present application.
Claims
1. A low power RC calibration circuit, characterized by, The application relates to a reference voltage generation module, a capacitor array charging module, a dynamic comparison module, an operation capture module and a logic circuit module. An input end of the dynamic comparison module is connected with the reference voltage generation module and receives a reference voltage signal, another input end of the dynamic comparison module is connected with the capacitor array charging module and receives a charging voltage signal, an output end of the dynamic comparison module outputs a comparison signal to the operation capture module, the operation capture module outputs an operation capture signal to the logic circuit module, and the logic circuit module controls switches of the capacitor array charging module to adjust a charging time.
2. The low power RC calibration circuit of claim 1, wherein, The reference voltage generation module comprises a power supply, a first current source and a sampling resistor, one end of the first current source is connected with the sampling resistor in series, and the other end of the sampling resistor is grounded.
3. The low power RC calibration circuit of claim 2, wherein, The capacitor array charging module comprises a second current source and a capacitor array unit, one end of the second current source is electrically connected with the power supply, and the other end of the second current source is connected with the capacitor array unit.
4. The low power RC calibration circuit of claim 3, wherein, The capacitor array unit comprises a reset tube and a plurality of parallelly connected capacitor charging loops, any capacitor charging loop comprises a charging capacitor and a charging switch MOS tube arranged in series.
5. The low power RC calibration circuit of claim 4, wherein, The comparison module comprises a two-stage full dynamic comparator, a VIN end of the two-stage full dynamic comparator is connected between the first current source and the sampling resistor, and a VIP end of the two-stage full dynamic comparator is connected between the other end of the second current source and the capacitor array unit.
6. The low power RC calibration circuit of claim 1, wherein, The operation capture module comprises an RS latch.