Ambient light elimination circuit

Abstract

The utility model discloses an ambient light elimination circuit. The ambient light elimination circuit comprises a light source acquisition module, a current processing module, an integration module and a sampling hold circuit. The light source acquisition module is used for acquiring target light and ambient light and converting the target light and the ambient light into current signals; the current processing module is used for processing the current signal; the integration module is used for carrying out integration on the processed current signal to obtain an integration voltage representing the related light acquired by the light source acquisition module, and outputting a differential voltage obtained by the integration voltage; the sample hold circuit holds and outputs the differential voltage. According to the utility model, hardware support can be provided when the ambient light is eliminated.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuits, and in particular to an ambient light elimination circuit. Background Technology

[0002] Currently, heart rate and blood oxygen detection require prior detection of the target light source. Existing technologies typically extract heart rate and blood oxygen information by collecting light reflected from the skin and blood vessels. However, complex acquisition environments can result in ambient light of varying energies. Insufficient elimination of ambient light can lead to distortion of the acquired information.

[0003] Therefore, there is an urgent need to propose an ambient light cancellation circuit to provide hardware support for achieving ambient light cancellation. Utility Model Content

[0004] The purpose of this invention is to propose an ambient light elimination circuit that provides hardware support for eliminating ambient light.

[0005] To solve the above-mentioned technical problems, this utility model provides an ambient light elimination circuit, including a light source acquisition module, a current processing module, an integration module, and a sample-and-hold circuit;

[0006] The light source acquisition module is used to acquire target light and ambient light and convert them into current signals;

[0007] The current processing module is used to process the current signal;

[0008] The integration module is used to integrate the processed current signal to obtain the integrated voltage characterizing the relevant light collected by the light source acquisition module, and output the differential voltage obtained from the integrated voltage.

[0009] The sample-and-hold circuit holds and outputs the differential voltage.

[0010] Furthermore, the light source acquisition module includes a photodiode (PD).

[0011] Furthermore, the current processing module includes a first current source, a second current source, a switch S1, and a switch S2; one end of the first current source is connected to the power supply voltage, and the other end of the first current source is connected to the negative terminal of the photodiode PD, one end of switch S1, and one end of switch S2; one end of the second current source is connected to the positive terminal of the photodiode PD, the other end of switch S1, and the other end of switch S2, and the other end of the second current source is grounded.

[0012] Furthermore, the switch S2 comprises a combination of two single-pole double-throw switches.

[0013] Furthermore, the switch S2 includes node N1, node N2, node INP, and node INN; node N1 is connected to node INP or node INN, and node N2 is connected to node INN or node INP.

[0014] Furthermore, the integration module includes an operational amplifier, multiple integrating capacitors Cint, and multiple reset switches S3; the node INP is connected to the non-inverting input of the operational amplifier, and the node INN is connected to the inverting input of the operational amplifier; wherein the two ends of the first integrating capacitor Cint are connected to the non-inverting input and the inverting output of the operational amplifier, respectively, and the two ends of the second integrating capacitor Cint are connected to the inverting input and the non-inverting output of the operational amplifier, respectively; the two ends of each reset switch S3 are connected to the two ends of each integrating capacitor Cint.

[0015] Furthermore, the integration module outputs the integrated voltage to the sample-and-hold circuit via nodes VON and VOP.

[0016] Furthermore, the sample-and-hold circuit includes multiple switches S4, multiple switches S5, and multiple holding capacitors C; the node VON is connected to one end of the switch S5 through the switch S4; the node VOP is connected to one end of the switch S5 through the switch S4; the other end of the switch S5 is connected to the common-mode voltage VCM; one end of the holding capacitor C is located between the switch S4 and the switch S5, and the other end is connected to the signal output terminal.

[0017] Through the above technical solution, this utility model has the following beneficial effects:

[0018] The device comprises a light source acquisition module, a current processing module, an integration module, and a sample-and-hold circuit. The light source acquisition module collects target light and ambient light, converting it into a current signal. The current processing module processes the current signal. The integration module integrates the processed current signal to obtain an integrated voltage representing the relevant light collected by the light source acquisition module, and outputs a differential voltage obtained from the integrated voltage. The sample-and-hold circuit holds and outputs the differential voltage. This device can eliminate ambient light. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall structure of the ambient light elimination circuit in one embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the circuit structure of the ambient light elimination circuit in one embodiment of the present invention. Detailed Implementation

[0021] The ambient light elimination circuit of this utility model will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the utility model. It should be understood that those skilled in the art can modify the utility model described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the utility model.

[0022] The present invention will be described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0023] like Figure 1 As shown in the figure, this utility model embodiment proposes an ambient light elimination circuit, including a light source acquisition module, a current processing module, an integration module, and a sample-and-hold circuit.

[0024] Specifically, the light source acquisition module is used to acquire target light and ambient light and convert them into current signals; the current processing module is used to process the current signals; the integration module is used to integrate the processed current signals to obtain an integrated voltage characterizing the correlated light acquired by the light source acquisition module (i.e., the correlated light acquired by the light source acquisition module, for example, the correlated light includes ambient light and a mixture of target light and ambient light), and outputs a differential voltage obtained from the integrated voltage (the differential voltage is a voltage related to the target light, or a voltage after mixing the ambient light and target light); the sample-and-hold circuit holds and outputs the differential voltage.

[0025] In one embodiment, the differential voltage mentioned above includes both the voltage related to ambient light and the voltage resulting from the mixing of ambient light and target light.

[0026] The current processing module is located between the light source acquisition module and the integration module. The integration module is located between the current processing module and the sample-and-hold circuit.

[0027] In this embodiment, as Figure 2 As shown, the light source acquisition module includes a photodiode PD, and the capacitance of the PD itself is denoted as Cpd.

[0028] In one embodiment, the current processing module needs to process the current signal converted from light by the PD (photodiode) to prevent excessive current from causing saturation of the integrator module output. The integrator module, in conjunction with the control logic, periodically integrates the processed PD current (i.e., the current signal). After the integrator module completes its operation, a sample-and-hold circuit samples and holds the voltage of the integrator module, completing one cycle of PD current processing and conversion.

[0029] In this embodiment, the current processing module includes a first current source, a second current source, a switch S1, and a switch S2. Specifically, one end of the first current source is connected to the power supply voltage, and the other end of the first current source is connected to the negative terminal of the photodiode PD, one end of switch S1, and one end of switch S2; one end of the second current source is connected to the positive terminal of the photodiode PD, the other end of switch S1, and the other end of switch S2, and the other end of the second current source is grounded.

[0030] Preferably, the switch S2 comprises a combination of two single-pole double-throw switches.

[0031] In one embodiment, the switch S2 includes node N1, node N2, node INP, and node INN; node N1 is connected to node INP or node INN, and node N2 is connected to node INN or node INP.

[0032] In this configuration, nodes INP and N2 are connected, while nodes INN and N1 are also connected, indicating that switch S2 is cross-connected; that is, node N1 equals node INN, and node N2 equals node INP. Alternatively, nodes INP and N1 being connected, while nodes INN and N2 being connected, indicates that switch S2 is sequentially connected; that is, when switch S2 is closed, node N1 equals node INP, and node N2 equals node INN. Within one processing cycle, the integration module needs to integrate twice. Each time, integration switch S1 is turned off; when the integration module is not integrating, S1 needs to be closed.

[0033] In this embodiment, the integration module includes an operational amplifier, multiple integrating capacitors Cint, and multiple reset switches S3; the node INP is connected to the non-inverting input of the operational amplifier, and the node INN is connected to the inverting input of the operational amplifier; wherein the two ends of the first integrating capacitor Cint are connected to the non-inverting input and the inverting output of the operational amplifier, respectively, and the two ends of the second integrating capacitor Cint are connected to the inverting input and the non-inverting output of the operational amplifier, respectively; the two ends of each reset switch S3 are connected to the two ends of each integrating capacitor Cint.

[0034] Furthermore, the integration module outputs the integrated voltage to the sample-and-hold circuit via nodes VON and VOP.

[0035] In this embodiment, the sample-and-hold circuit includes multiple switches S4, multiple switches S5, and multiple holding capacitors C. Specifically, node VON is connected to one end of switch S5 through switch S4; node VOP is connected to one end of switch S5 through switch S4; the other end of switch S5 is connected to the common-mode voltage VCM; one end of the holding capacitor C is disposed between switch S4 and switch S5, and the other end is connected to the signal output terminal.

[0036] Because the photodiode PD generates a reverse current Ipd when exposed to light, which is the current flowing from node N1 into node N2, such as... Figure 2 As shown, the directional current generated by different wavelengths and light intensities is different. To prevent Ipd from being too large and causing the integrator module output to saturate, a certain amount of compensation current Ioffset needs to be enabled. The compensation value can be obtained through existing scenario simulations. When sampling and converting the current of the photodiode PD, its compensation value can be directly called.

[0037] In one specific embodiment, this embodiment directly addresses the issue of ambient light elimination. First, ambient light is integrated separately, and then the mixed light from the ambient light and the specific LED is integrated. By subtracting the two integrations using circuit principles, ambient light can be effectively eliminated, thus achieving the goal of detecting only the specific LED light source information carrying biological information. That is, the integration module integrates twice before transmitting the integrated voltage to the sample-and-hold circuit. During each integration, the light source acquisition module collects light once. The first integrated voltage contains only ambient light, while the second integrated voltage contains both ambient light and target light. However, because the integrated voltage is calculated by subtracting the ambient light from the first integration, it only includes the target light. Specifically:

[0038] When in use, the PD is irradiated by two types of light: ambient light and light emitted from a specific LED (target light) and reflected from the skin and blood vessels.

[0039] During the first integration, the specific LED light is not turned on, only the ambient light is used, and the integration is performed separately for this ambient light. In chronological order, switch S1 is turned off, Ioffset is 0, and reset switch S3 is closed after Δt0. During Δt0, the integration module is reset. The voltage V at the node VON where the integration module is connected to the current processing module is... ON and the voltage V of node VOP OP All are common-mode voltages VCM, i.e., V during the period Δt0. ON =V OP =VCM.

[0040] When the reset switch S3 is turned off, the integration module begins its first integration during Δt1, and switch S2 is turned on sequentially. Let the current of the photodiode PD be Ipd_amb, then the integrated current from node VON to node INP is equal to Ipd_amb - Ioffset, where Ioffset is the compensation current. During the first integration period, Ioffset is 0, therefore V... ON =VCM + Ipd_amb × Δt1 / C int V OP =VCM-Ipd_amb×Δt1 / C int C int This is the capacitance value of the integrating capacitor Cint.

[0041] After the first integration is completed, a target light loading time and a compensation current code issuance time Δt2 are reserved. During Δt2, the switch S1 is closed, the integration module is disconnected from the current processing module, the nodes INP and INN maintain the common mode voltage VCM, and the nodes VON and VOP also maintain the final integrated voltage during Δt1.

[0042] During Δt2, Ioffset will vary depending on the application scenario, but it will be less than Ipd. Closing switch S1 during Δt2 facilitates the mutual conduction of Ioffset currents between nodes N1 and N2, preventing the voltage of node N1 from gradually approaching the power supply and the voltage of node N2 from gradually approaching ground when Ioffset is greater than Ipd. This ensures that when switch S2 is closed during Δt3, there will be no drastic current changes due to large voltage differences between nodes N1 and INP, or between nodes N2 and INN.

[0043] Therefore, during the second integration, switch S1 is closed during Δt2; simultaneously, the specific LED light is turned on during Δt2 and Δt3, and Ioffset is the predetermined compensation current. During Δt3, switch S2 is cross-conducting; since the target light has been loaded during Δt3, let the current on the photodiode PD be Ipd_sum. Then there is a current Ipd_sum - Ioffset flowing from node INP to node VON, and there is a current Ipd_sum - Ioffset flowing from node VOP to node INN.

[0044] The closure of switch S1 maintains a low common-mode voltage VCM for the voltage drift operational amplifiers at nodes N1 and N2, ensuring the stability of the integrated current during Δt3. After Δt3, the integration module is partially disconnected from the current processing module, and switch S1 is closed. Nodes VOP and VON are stable, containing only the light source information of specific LEDs (Δt1 and Δt3 are equal, and the ambient light remains unchanged during Δt1 and Δt3). After Δt3, the sample-and-hold circuit transfers the information from nodes VON and VOP to the sample-and-hold circuit, completing the processing and conversion of the PD current for one cycle and eliminating the ambient light component.

[0045] Since the current integration directions of Δt3 and Δt1 are opposite, and the integration module has no feedback resistor, the voltage V at node VON and node VOP of Δt3 is... ON and V OP as follows:

[0046] V ON =(VCM+Ipd_amb×Δt1 / C) int )-(Ipd_sum-Ioffset)×Δt3 / C int ;

[0047] V OP =(VCM-Ipd_amb×Δt1 / C) int )+(Ipd_sum-Ioffset)×Δt3 / C int ;

[0048] Ipd_sum = Ipd_amb + Ipd_led.

[0049] Where Ipd_led is the current of the target light, V OP V represents the voltage value at node VOP. ON C represents the voltage value at node VON. int Here is the capacitance value of the integrating capacitor Cint.

[0050] When Δt1 = Δt3, the final voltage V of Δt3 ON and V OP as follows:

[0051] V ON =VCM+(Ioffset-Ipd_led)×Δt1 / Cint ;

[0052] V OP =VCM+(Ipd_led-Ioffset)×Δt1 / C int ;

[0053] The output after differential conversion is the second differential voltage:

[0054] V OP -V ON = 2(Ipd_led - Ioffset) × Δt1 / C int .

[0055] Finally, the differential voltage is transmitted to the ADC (Analog-to-Digital Converter) for quantization via a sample-and-hold circuit, completing the conversion from analog to digital signal. Specifically, when switch S4 is closed and switch S5 is closed, the sample-and-hold circuit can receive the differential voltage and store it on the holding capacitor C. When switch S4 is closed and switch S5 is closed, the previously stored differential voltage can be reset, and the differential voltage can be stored again when switch S4 is closed next time.

[0056] In this embodiment, combined with Figure 2 As shown. For example, the target light is a specific LED light source. First, integrate the ambient light separately once, for example, the common-mode voltage VCM is 1.2V, during the period Δt0, V ON =V OP =1.2V, output differential voltage is V OP -V ON =0.

[0057] When reset switch S3 is open, the integrator module begins its first integration during Δt1, and switch S2 is sequentially turned on. Since only ambient light is present on the PD at this time, let the PD current (i.e., the current of the photodiode PD) be Ipd_amb. Therefore, the integrated current from node VON to node INP is equal to Ipd_amb - Ioffset. During the first integration period, Ioffset is 0, so V... ON =VCM + Ipd_amb × Δt1 / C int V OP =VCM-Ipd_amb×Δt1 / C int .

[0058] After the first integration is completed, time is needed to load the specific LED light source (target light) and to issue the compensation current code; Δt2 is this time period. During Δt2, switch S1 is closed, disconnecting part of the circuitry between the integration module and the current processing module. Nodes INP and INN maintain a common-mode voltage VCM, i.e., 1.2V, while V... ON and V OP It also maintains the final integral voltage during Δt1.

[0059] During Δt3, switch S2 is cross-conducting, so nodes INP and N2 are conducting, and nodes INN and N1 are conducting. Because the LED is on during this period, the current on photodiode PD is Ipd_sum. Therefore, there is a current Ipd_sum - Ioffset flowing from node INP to node VON, and similarly, there is a current Ipd_sum - Ioffset flowing from node VOP to node INN. Because the current integration directions in Δt3 and Δt1 are opposite, and the integration module has no feedback resistor, the voltage V at nodes VON and VOP in Δt3 is... ON and V OP as follows:

[0060] V ON =(VCM+Ipd_amb×Δt1 / C) int )-(Ipd_sum-Ioffset)×Δt3 / C int ;

[0061] V OP =(VCM-Ipd_amb×Δt1 / C) int )+(Ipd_sum-Ioffset)×Δt3 / C int ;

[0062] Ipd_sum = Ipd_amb + Ipd_led.

[0063] And Δt1 = Δt3, so the final V ON and V OP as follows:

[0064] V ON =VCM+(Ioffset-Ipd_led)×Δt1 / C int ;

[0065] V OP =VCM+(Ipd_led-Ioffset)×Δt1 / C int ;

[0066] Then the differential output voltage:

[0067] V OP -V ON = 2(Ipd_led - Ioffset) × Δt1 / C int ;

[0068] Because Ioffset, Δt1, C int Since all of these are known quantities, the final output differential voltage is simply voltage information related to the specific LED light (target light) during Δt3.

[0069] The sample-and-hold circuit then transmits the differential voltage to the ADC (Analog-to-Digital Converter) for quantization, completing the conversion from analog to digital signal. By repeating this embodiment as a single instruction N times within a predetermined work cycle, N discrete voltage points can be obtained. Reducing the time interval between these discrete voltage points or increasing the number of discrete voltage points allows for the fitting of heart rate or blood oxygenation information to discrete points over a continuous time period using specific LED light.

[0070] In summary, the ambient light elimination circuit proposed in this utility model has the following advantages:

[0071] The device comprises a light source acquisition module, a current processing module, an integration module, and a sample-and-hold circuit. The light source acquisition module collects target light and ambient light, converting it into a current signal. The current processing module processes the current signal. The integration module integrates the processed current signal to obtain an integrated voltage representing the relevant light collected by the light source acquisition module, and outputs a differential voltage obtained from the integrated voltage. The sample-and-hold circuit holds and outputs the differential voltage. This device can eliminate ambient light.

[0072] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.

Claims

1. An ambient light cancellation circuit, characterized in that, It includes a light source acquisition module, a current processing module, an integration module, and a sample-and-hold circuit; The light source acquisition module is used to acquire target light and ambient light and convert them into current signals; The current processing module is used to process the current signal; The integration module is used to integrate the processed current signal to obtain the integrated voltage characterizing the relevant light collected by the light source acquisition module, and output the differential voltage obtained from the integrated voltage. The sample-and-hold circuit holds and outputs the differential voltage.

2. The ambient light elimination circuit as described in claim 1, characterized in that, The light source acquisition module includes a photodiode (PD).

3. The ambient light elimination circuit as described in claim 2, characterized in that, The current processing module includes a first current source, a second current source, a switch S1, and a switch S2; one end of the first current source is connected to the power supply voltage, and the other end of the first current source is connected to the negative terminal of the photodiode PD, one end of switch S1, and one end of switch S2; one end of the second current source is connected to the positive terminal of the photodiode PD, the other end of switch S1, and the other end of switch S2, and the other end of the second current source is grounded.

4. The ambient light elimination circuit as described in claim 3, characterized in that, The switch S2 comprises a combination of two single-pole double-throw switches.

5. The ambient light elimination circuit as described in claim 4, characterized in that, The switch S2 includes node N1, node N2, node INP, and node INN; node N1 can be connected to node INP or node INN, and node N2 can be connected to node INN or node INP.

6. The ambient light elimination circuit as described in claim 5, characterized in that, The integration module includes an operational amplifier, multiple integrating capacitors Cint, and multiple reset switches S3; the node INP is connected to the non-inverting input of the operational amplifier, and the node INN is connected to the inverting input of the operational amplifier; wherein the two ends of the first integrating capacitor Cint are connected to the non-inverting input and the inverting output of the operational amplifier, respectively, and the two ends of the second integrating capacitor Cint are connected to the inverting input and the non-inverting output of the operational amplifier, respectively; the two ends of each reset switch S3 are connected to the two ends of each integrating capacitor Cint.

7. The ambient light elimination circuit as described in claim 6, characterized in that, The integration module outputs the integrated voltage to the sample-and-hold circuit through nodes VON and VOP.

8. The ambient light elimination circuit as described in claim 7, characterized in that, The sample-and-hold circuit includes multiple switches S4, multiple switches S5, and multiple holding capacitors C; node VON is connected to one end of switch S5 through switch S4; node VOP is connected to one end of switch S5 through switch S4; the other end of switch S5 is connected to common-mode voltage VCM; one end of holding capacitor C is located between switch S4 and switch S5, and the other end is connected to the signal output terminal.

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