Watchdog chip performance detection circuit and device

Abstract

The utility model relates to the technical field of chip testing, in particular to a watchdog chip performance detection circuit and device. The circuit comprises a test board which is composed of a PCB, a chip seat is welded on the test board, and the chip seat is used for installing a watchdog chip; one end of the voltage-dividing current-limiting resistor R1 is connected in series with an external 3V3 power supply, and the other end of the voltage-dividing current-limiting resistor R1 is connected to a VCC pin of the chip seat; one end of the filter capacitor C1 is connected to the VCC pin, and the other end of the filter capacitor C1 is connected to the ground (GND); and the filter capacitor C2 and the single-pole switch J1 are connected in parallel between the MR pin of the chip seat and the ground (GND). According to the utility model, the situation that the chip generates a reset signal to restart equipment or a WD I pin or an MR pin is manually short-circuited to finish resetting by using a conventional serial port command is avoided. The process is saved, and the time is saved; and the problem that the chip and surrounding components are easy to damage due to multiple operations is also avoided.

Description

Technical Field

[0001] This utility model relates to the field of chip testing technology, specifically to a watchdog chip performance testing circuit and device. Background Technology

[0002] Currently, our performance verification tests for watchdog chips are conducted after the chip is installed in our product. The methods are either sending a serial command to trigger a reset signal and restart the device, or manually shorting the WDI or MR pins to complete the reset. Sending a serial command requires waiting for the entire serial port to print and the device to restart before proceeding to the next verification, which can take several minutes and is time-consuming. Manually shorting the pins can easily generate electrical sparks, and repeated operations can damage the chip and surrounding components. Utility Model Content

[0003] The purpose of this invention is to perform multiple, rapid, and effective verifications of the watchdog chip's performance by individually pulling the MR pin low or individually stopping the control signal to perform the watchdog feeding action, and then using a measuring instrument to detect whether the RESET pin has performed a reset action.

[0004] The technical solution of this utility model to solve the above-mentioned technical problems is as follows:

[0005] On the one hand, a watchdog chip performance detection circuit is provided, the circuit comprising:

[0006] A test board, consisting of a PCB board, on which a chip socket is soldered for mounting a watchdog chip;

[0007] A voltage divider and current limiting resistor R1 is connected in series with an external 3V3 power supply at one end and connected to the VCC pin of the chip socket at the other end.

[0008] A filter capacitor C1 is connected at one end to the VCC pin and at the other end to ground (GND);

[0009] A filter capacitor C2 and a single-pole switch J1 are connected in parallel between the MR pin of the chip socket and ground (GND);

[0010] A voltage divider and current limiting resistor R2 is connected at one end to the RESET pin of the chip socket and at the other end to a tester for monitoring the reset signal.

[0011] A filter capacitor C3 is connected between the RESET pin of the chip socket and ground (GND);

[0012] A filter capacitor C4 and a single-pole switch J2 are connected in parallel between the WDI pin of the chip socket and a control signal transmitter, which is used to generate a timing reset signal.

[0013] Furthermore, the PCB board has a multi-layer structure to optimize electrical performance and reduce signal coupling and crosstalk;

[0014] The PCB board also includes multiple connectors for connecting different interfaces, thereby increasing the applicability of the circuit.

[0015] Furthermore, the filter capacitor C1 is configured to provide power filtering in the circuit, ensuring a stable power supply during use.

[0016] Furthermore, the resistance values ​​of the voltage divider and current limit resistor R1 and the voltage divider and current limit resistor R2 are adjustable to adapt to the voltage and current requirements of different types of watchdog chips.

[0017] Furthermore, the single-pole switches J1 and J2 are manually controlled switches, allowing manual control of the states of the MR pin and the WDI pin during testing, for debugging and verifying the watchdog's performance.

[0018] On the other hand, a watchdog chip performance testing device is provided, including the watchdog chip performance verification circuit as described above, the device further including:

[0019] A tester, connected to the RESET pin in the circuit, is used to detect the reset signal transmitted through the RESET pin;

[0020] A control signal transmitter is connected to the WDI pin in the circuit to provide a timing reset signal to the circuit in order to control the operating state of the watchdog chip.

[0021] Furthermore, the tester has a simulated signal generation function, which can simulate different working environments and signal conditions for the evaluation and improvement of the device's performance;

[0022] The control signal transmitter is designed with a timing control circuit, which can precisely control the transmission timing, frequency and strength of the signal, and is used to verify the watchdog chip's response to the timing reset signal during the test.

[0023] Furthermore, the device is integrated into a portable housing that is dustproof, shockproof, and waterproof, providing protection for the circuitry and the device in various testing environments.

[0024] Furthermore, the device also includes a user interface module that provides interactive display and control functions for real-time monitoring of verification status, adjustment of test parameters, and reading and storing test results.

[0025] The beneficial effects of this utility model are:

[0026] This invention avoids the conventional methods of using serial port commands to generate a reset signal for the chip and restart the device, or manually shorting the WDI or MR pins to complete the reset. This saves time and streamlines the process; it also avoids the problem of damaging the chip and surrounding components due to repeated operations.

[0027] This invention provides a device for quickly and effectively verifying the performance of a watchdog chip by individually pulling the MR pin low or individually stopping the control signal to perform the watchdog feeding action, and then using a measuring instrument to detect whether the RESET pin has performed a reset action. It is suitable for the product development stage, has a simple circuit, requires fewer components, can be reused, and is low in cost and cost-effective. Attached Figure Description

[0028] Figure 1 This is a circuit diagram for the performance testing of the watchdog chip of this utility model. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this utility model and are not intended to limit this utility model.

[0030] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0031] The present invention provides the following preferred embodiments:

[0032] To facilitate understanding of the technical solution of this utility model, the working principle of the watchdog timer is briefly introduced below: Embedded electronic products with CPUs may experience program abnormalities under interference from complex environments such as power transients, electromagnetic interference, electrostatic discharge, and extreme temperature and humidity, causing the system to malfunction. In such cases, it is desirable for the device to automatically reset without manual intervention. The watchdog timer can help capture and reset the "out-of-control" device, enabling unattended operation and improving system reliability. The use of a watchdog chip can help accomplish this task. When the device program crashes, the CPU fails to output a signal to the watchdog timer at regular intervals to reset it. If the watchdog timer is not fed for a specified period, it overflows, sending a reset signal that pulls the RST pin low, resetting the chip and restarting the device. Watchdog chips play a crucial role in ensuring the reliability and stability of devices. Therefore, watchdog chips undergo multiple performance verifications during the research and development phase. Currently, the common verification methods involve resetting the chip via serial port commands or directly shorting the WDI pin on the product's PCB. These methods are complex, time-consuming, and short-circuiting can easily damage other electronic components. It would be beneficial to perform separate and multiple performance verifications of the watchdog chip during the research and development phase to determine if it meets the standards, thereby saving on later research and development materials and testing time. This is an area that needs to be considered.

[0033] like Figure 1 As shown, the watchdog chip performance testing device of this utility model mainly consists of three parts: a test board, a tester, and a control signal transmitter. It should be explained that the test board is the core part of the entire testing device, integrating the watchdog chip performance testing circuit. Its structural design and component configuration affect the accuracy of the test. Understandably, the test board should be made of a high-quality PCB board, and a dedicated watchdog chip socket is soldered onto the test board to accommodate the chip under test. The test board also features complex peripheral circuits, including voltage divider and current limiting resistors, multiple filter capacitors, and single-pole switches. Each component has a specific function and role, designed to provide a stable working environment for the watchdog chip and accurately monitor its operating status.

[0034] In this embodiment, the external 3.3V power supply is connected to the VCC pin of the chip socket through a voltage divider and current limiting resistor R1, providing a stable power supply for the watchdog chip. Capacitor C1 is connected between the VCC pin and ground to filter out high-frequency noise in the power supply, ensuring power stability during chip operation. Meanwhile, filter capacitor C2 and single-pole switch J1 are connected in parallel between the MR pin of the watchdog chip and ground. By operating switch J1, a manual reset scenario can be simulated, allowing engineers to verify the chip's response and stability under different reset conditions.

[0035] Furthermore, the RESET pin of the watchdog chip is connected to the test instrument via a current-limiting resistor R2, providing a critical signal detection path for the device. Changes in the state of the RESET pin directly reflect the watchdog chip's reset behavior under conditions of external signal interference or timing overflow. Capacitor C3 is connected between the RESET pin and ground, also for signal filtering, ensuring the accuracy of the recorded reset signal. Through the test instrument, users can monitor changes in the RESET signal in real time, providing crucial data support for evaluating the actual performance of the watchdog chip.

[0036] Furthermore, the control signal transmitter is connected to the chip's WDI pin via filter capacitor C4 and single-pole switch J2. The transmitter can generate timing reset signals of different frequencies and intensities to simulate the "watchdog timer" operation during normal system operation. By adjusting the signal period and amplitude, the chip can be tested under various operating environments. This design allows the watchdog chip to demonstrate its operational stability and reset response accuracy under different test conditions.

[0037] Furthermore, it's important to understand that the entire test board design also considers circuit stability and signal integrity. By employing a multi-layer PCB, signal paths can be optimized, reducing potential signal crosstalk and noise coupling. This design not only ensures the independence of power and ground planes but also improves signal transmission quality and enhances the overall reliability of the test environment.

[0038] Furthermore, in addition to the meticulous consideration of hardware design, the testing device of this invention also emphasizes its scalability and compatibility in practical applications. By adjusting the resistance values ​​of the voltage divider and current limiting resistors R1 and R2, it can be compatible with various models of watchdog chips. This makes the device not only suitable for testing a specific chip model, but also applicable to a wider range of application scenarios. For R&D personnel, this flexible compatibility greatly simplifies the switching between different chip models and improves testing efficiency.

[0039] In further applications, the control signal transmitter also features programmability, allowing users to set characteristic parameters of signal transmission, such as signal period, amplitude, and duration, via a software interface. This design not only provides more stringent and diverse testing conditions for watchdog chips but also reserves upgrade space for future verification of new chips. It can effectively simulate various extreme operating conditions in complex applications, helping users better understand the characteristics of the chip under test.

[0040] Furthermore, by working in conjunction with advanced testing equipment, the testing device of this invention also supports the analysis and processing of collected data to generate detailed test reports. These reports record in detail the chip's performance across various indicators during testing, including key data such as reset frequency, response time, and current consumption. This data provides engineers with quantitative performance evaluation data, helping to optimize product design and improve chip utilization.

[0041] Understandably, the watchdog chip supports both manual reset and watchdog overflow reset, as detailed below:

[0042] Manual reset: Open the single-pole switch J2, and at the same time, the transmitter outputs a signal to the WDI pin at regular intervals to clear the watchdog timer, so that the watchdog timer overflows and generates a reset signal. Then close the switch J1 to pull the MR pin low, so that the chip generates a manual reset. At this time, the reset signal is detected by the measuring instrument.

[0043] Watchdog Overflow Reset: With single-pole switch J2 closed, the WDI pin is pulled low, preventing timely watchdog feeding. A watchdog overflow pulls the chip's RESET pin low, generating a reset signal. Simultaneously, switch J1 is opened, causing the MR pin to float, preventing manual chip reset. The presence of a reset signal is then detected using a measuring instrument. This method enables rapid and effective verification of watchdog chip performance for use in hardware circuit applications. It allows for quick and effective verification of watchdog chip performance during the product design phase, maximizing chip utilization in the circuit.

[0044] The advantage of this embodiment lies in the fact that the watchdog chip performance verification device provided by this invention not only strives for simplicity and efficiency in its design, but also demonstrates strong scalability and adaptability in its functionality. By combining different testing methods and data analysis techniques, the testing device of this invention can not only help engineers efficiently complete chip performance verification, but also provide continuous support and optimization suggestions throughout the product's lifecycle. In today's increasingly complex electronic products, this device provides strong technical support for ensuring product stability and enhancing market competitiveness.

[0045] The beneficial effects of this utility model are specifically reflected in the fact that the above description is only a preferred embodiment of this utility model and is not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A watchdog chip performance detection circuit, characterized in that, The circuit includes: A test board, consisting of a PCB board, on which a chip socket is soldered for mounting a watchdog chip; A voltage divider and current limiting resistor R1 is connected in series with an external 3V3 power supply at one end and connected to the VCC pin of the chip socket at the other end. A filter capacitor C1 is connected at one end to the VCC pin and at the other end to ground (GND); A filter capacitor C2 and a single-pole switch J1 are connected in parallel between the MR pin of the chip socket and ground (GND); A voltage divider and current limiting resistor R2 is connected at one end to the RESET pin of the chip socket and at the other end to a tester for monitoring the reset signal. A filter capacitor C3 is connected between the RESET pin of the chip socket and ground (GND); A filter capacitor C4 and a single-pole switch J2 are connected in parallel between the WDI pin of the chip socket and a control signal transmitter, which is used to generate a timing reset signal.

2. The watchdog chip performance detection circuit according to claim 1, characterized in that, The PCB board has a multi-layer structure to optimize electrical performance and reduce signal coupling and crosstalk; The PCB board also includes multiple connectors for connecting different interfaces, thereby increasing the applicability of the circuit.

3. The watchdog chip performance detection circuit according to claim 1, characterized in that, The filter capacitor C1 is configured to provide power filtering in the circuit, ensuring a stable power supply during use.

4. The watchdog chip performance detection circuit according to claim 1, characterized in that, The resistance values ​​of the voltage divider and current limiting resistors R1 and R2 are adjustable to adapt to the voltage and current requirements of different types of watchdog chips.

5. The watchdog chip performance detection circuit according to claim 1, characterized in that, The single-pole switches J1 and J2 are manual control switches, which allow manual control of the state of the MR pin and WDI pin during testing, for debugging and verifying the watchdog performance.

6. A watchdog chip performance testing device, characterized in that, The apparatus, comprising the watchdog chip performance verification circuit as described in any one of claims 1 to 5, further comprises: A tester, connected to the RESET pin in the circuit, is used to detect the reset signal transmitted through the RESET pin; A control signal transmitter is connected to the WDI pin in the circuit to provide a timing reset signal to the circuit in order to control the operating state of the watchdog chip.

7. The watchdog chip performance testing device according to claim 6, characterized in that, The tester has a simulated signal generation function, which can simulate different working environments and signal conditions for the evaluation and improvement of the device's performance. The control signal transmitter is designed with a timing control circuit, which can precisely control the transmission timing, frequency and strength of the signal, and is used to verify the watchdog chip's response to the timing reset signal during the test.

8. The watchdog chip performance testing device according to claim 6, characterized in that, The device is integrated into a portable housing that is dustproof, shockproof, and waterproof, providing protection for the circuitry and the device in various testing environments.

9. The watchdog chip performance testing device according to claim 8, characterized in that, The device also includes a user interface module that provides interactive display and control functions for real-time monitoring of verification status, adjustment of test parameters, and reading and storage of test results.

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