Cache device compatible with Cache / tcm working mode
By designing a cache device compatible with both Cache/TCM operating modes, and utilizing bus switches and bridges to achieve mode switching and rate/bit width matching, the problem of cache devices in SOC chips needing to be compatible with two operating modes is solved, thereby improving the flexibility and performance of the cache device.
Patent Information
- Application Number
- CN202423237492.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-11-11
- Estimated Expiration
- 2034-12-26
AI Technical Summary
The cache device in the SOC chip needs to be compatible with both cache and tcm operating modes and be able to switch between them as needed to leverage their respective performance advantages.
A cache device compatible with Cache/tcm operating mode is designed, including first and second bus switches and Cache/tcm cache. Mode switching and rate/bit width matching are realized through bus switches and bus bridges, and frequency and bit width conversion is performed using an AXI bus bridge.
It achieves compatibility and switching between Cache and TCM modes, ensuring speed and bit width matching between the DSP and the system bus, and improving the flexibility and performance of the cache device.
Smart Images
Figure CN223539185U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of SOC on-chip cache technology, and particularly relates to a cache device compatible with Cache / tcm working mode. Background Technology
[0002] In SOC chips, the cache operates in cache mode, accessing data line by line and not supporting cross-line operations. This requires a certain degree of randomness and repetition in the data in order to leverage the performance advantages of the cache.
[0003] The cache operates in TCM (tightly coupled memory) mode, which leverages the performance advantages of TCM when processing data that is used only once, such as in data stream processing.
[0004] When a cache needs to support the two different application scenarios mentioned above, a caching device is required that is compatible with both cache and TCM working modes and can be switched according to needs. Utility Model Content
[0005] Based on the above analysis, this utility model aims to provide a caching device compatible with both Cache and TCM working modes, enabling support and switching between the two working modes.
[0006] The objective of this utility model is mainly achieved through the following technical solutions:
[0007] This utility model discloses a cache device compatible with Cache / tcm working mode, including: a first bus switch, a second bus switch and a Cache / tcm cache;
[0008] The first bus switch is a one-to-two bus switch, and the second bus switch is a two-to-one bus switch.
[0009] The master terminal M1 of the first bus switch is connected to the DSP, and the first slave terminal S1 is connected to the first master terminal m1 of the second bus switch; the second slave terminal S2 of the first bus switch is connected to the Cache / tcm buffer; the second master terminal m2 of the second bus switch is connected to the Cache / tcm buffer; the slave terminal s1 of the second bus switch is connected to the system bus; the system bus is also connected to the Cache / tcm buffer.
[0010] Furthermore, the Cache / tcm cache operates in Cache mode.
[0011] The master terminal M1 of the first bus switch is connected to the slave terminal S2, and the connection with the slave terminal S1 is disconnected; the DSP is connected to the cache working in Cache mode through the master terminal M1 and the slave terminal S2 of the first bus switch.
[0012] The second master terminal m2 of the second bus switch is connected to the slave terminal s1, and the connection between the first master terminal m1 and the slave terminal s1 is disconnected; the cache working in Cache mode is connected to the system bus through the second master terminal m2 and the slave terminal s1 of the second bus switch.
[0013] Furthermore, the Cache / tcm cache operates in tcm mode.
[0014] The master terminal M1 of the first bus switch is connected to the first slave terminal S1, and disconnected from the second slave terminal S2.
[0015] The first master terminal m1 of the second bus switch is connected to the slave terminal s1, and the connection between the second master terminal m2 and the slave terminal s1 is disconnected.
[0016] The DSP is connected to the first master terminal m1 of the second bus switch via the first master terminal M1 and the first slave terminal S1 of the first bus switch. It is then connected to the system bus via the first master terminal m1 and the slave terminal of the second bus switch, and finally connected to the cache operating in TCM mode via the system bus.
[0017] Furthermore, the Cache / tcm cache operates in tcm mode.
[0018] Other master devices on the system bus interconnect connect to the cache operating in TCM mode via the system bus to read and write cached data.
[0019] Furthermore, the DSP and cache operate at the same frequency and bit width, which is higher than the frequency and bit width of the system bus;
[0020] The cache device also includes a bus bridge;
[0021] The first master terminal m'1 of the bus bridge is connected to the slave terminal s1 of the second bus switch; the first slave terminal s'1 is connected to the system bus, the second master terminal m'2 is connected to the system bus, and the second slave terminal s'2 is connected to the buffer.
[0022] The first master terminal m'1 to the first slave terminal s'1 of the bus bridge provides a path for reducing speed and bit width from the DSP to the bus; the second master terminal m'2 to the second slave terminal s'2 of the bus bridge provides a path for increasing speed and bit width from the system bus to the cache operating in TCM mode.
[0023] Furthermore, the Cache / tcm cache operates in Cache mode.
[0024] The master terminal M1 of the first bus switch is connected to the slave terminal S2, and the connection with the slave terminal S1 is disconnected; the DSP is connected to the cache working in Cache mode through the master terminal M1 and the slave terminal S2 of the first bus switch.
[0025] The second master terminal m2 of the second bus switch is connected to the slave terminal s1, and the connection between the first master terminal m1 and the slave terminal s1 is disconnected; the cache working in Cache mode is connected to the first master terminal m'1 of the bus bridge through the second master terminal m2 and the slave terminal s1 of the second bus switch, and the first slave terminal s'1 of the bus bridge is connected to the system bus.
[0026] Disconnect the second slave end s'2 of the bus bridge from the buffer.
[0027] Furthermore, the Cache / tcm cache operates in tcm mode.
[0028] Cache / tcm caching operates in tcm mode.
[0029] The master terminal M1 of the first bus switch is connected to the first slave terminal S1, and disconnected from the second slave terminal S2.
[0030] The first master terminal m1 of the second bus switch is connected to the slave terminal s1, and the connection between the second master terminal m2 and the slave terminal s1 is disconnected.
[0031] The DSP is connected to the first master terminal m1 of the second bus switch via the first master terminal M1 and the first slave terminal S1 of the first bus switch. Then, it is connected to the first master terminal m'1 of the bus bridge via the first master terminal m1 and the slave terminal of the second bus switch. Then, it is connected to the system bus via the first slave terminal s'1 of the bus bridge. Then, it is connected to the second master terminal m'2 of the bus bridge via the system bus. Finally, it is connected to the cache operating in TCM mode via the second slave terminal s'2 of the bus bridge.
[0032] Furthermore, other master devices on the system bus interconnect are connected to the cache operating in TCM mode via the second master terminal m'2 of the bus bridge and then via the second slave terminal s'2 of the bus bridge.
[0033] Furthermore, the DSP has a 600MHz clock cycle and a 32-bit width; the system bus has a 300MHz clock cycle and a 16-bit width.
[0034] Furthermore, both the system bus and the internal bus of the cache device are AXI buses.
[0035] The beneficial effects of this utility model are as follows:
[0036] The device disclosed in this utility model is compatible with both cache and tcm working modes, achieving compatibility and switching between the two cache working modes, and also achieving speed and bit width matching between the DSP and the system bus. Attached Figure Description
[0037] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0038] Figure 1 This is a schematic diagram showing the connection of a cache device compatible with Cache / tcm working mode in an embodiment of this utility model;
[0039] Figure 2 This is a schematic diagram illustrating the connection of a cache device in the Cache / TCM working mode compatible with a bus bridge, as described in this embodiment of the present invention. Detailed Implementation
[0040] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and, together with the embodiments of the present invention, serve to illustrate the principles of the present invention.
[0041] A specific embodiment of this utility model discloses a caching device compatible with Cache / TCM working mode, such as... Figure 1 As shown, it includes: a first bus switch, a second bus switch, and a Cache / tcm buffer;
[0042] The first bus switch and the second bus switch can statically switch the bus connection relationship (like a single-pole double-throw switch), and switch the bus connection relationship according to the system's working mode.
[0043] The core storage logic is cache / tcm, which can be used as cache or tcm in different working modes;
[0044] The first bus switch is a one-to-two bus switch, and the second bus switch is a two-to-one bus switch.
[0045] The master terminal M1 of the first bus switch is connected to the DSP, and the first slave terminal S1 is connected to the first master terminal m1 of the second bus switch; the second slave terminal S2 of the first bus switch is connected to the Cache / tcm buffer; the second master terminal m2 of the second bus switch is connected to the Cache / tcm buffer; the slave terminal s1 of the second bus switch is connected to the system bus; the system bus is also connected to the Cache / tcm buffer.
[0046] Specifically, Cache / tcm cache operates in Cache mode.
[0047] The master terminal M1 of the first bus switch is connected to the slave terminal S2, and the connection with the slave terminal S1 is disconnected; the DSP is connected to the cache working in Cache mode through the master terminal M1 and the slave terminal S2 of the first bus switch.
[0048] The second master terminal m2 of the second bus switch is connected to the slave terminal s1, and the connection between the first master terminal m1 and the slave terminal s1 is disconnected; the cache working in Cache mode is connected to the system bus through the second master terminal m2 and the slave terminal s1 of the second bus switch.
[0049] The DSP's read and write requests reach the cache through the first bus switch, and the cache's read and write requests reach the system bus through the second bus switch, reaching the slave devices connected to the system bus, thus realizing data interconnection through the cache.
[0050] Specifically, the Cache / tcm cache operates in tcm mode.
[0051] The master terminal M1 of the first bus switch is connected to the first slave terminal S1, and disconnected from the second slave terminal S2.
[0052] The first master terminal m1 of the second bus switch is connected to the slave terminal s1, and the connection between the second master terminal m2 and the slave terminal s1 is disconnected.
[0053] The DSP is connected to the first master terminal m1 of the second bus switch via the first master terminal M1 and the first slave terminal S1 of the first bus switch. It is then connected to the system bus via the first master terminal m1 and the slave terminal of the second bus switch, and finally connected to the cache operating in TCM mode via the system bus.
[0054] The DSP's read and write requests reach the system bus through the first bus switch and the second bus switch, and then from the system bus to the cache operating in TCM mode to access the cached data.
[0055] Furthermore, when the Cache / tcm cache operates in TCM mode, other master devices on the system bus interconnect connect to the cache operating in TCM mode via the system bus to read and write cached data.
[0056] In this embodiment, under TCM mode, the DSP and other master devices on the system bus interconnection can read and write access to the TCM cache.
[0057] In the alternative scheme, the DSP and cache operate at the same frequency and bit width, which is higher than the frequency and bit width of the system bus;
[0058] Specifically, the DSP has a 600MHz clock cycle and a 32-bit width; the system bus has a 300MHz clock cycle and a 16-bit width.
[0059] Therefore, bidirectional conversion of bit width and speed is required in the connection between the DSP, cache, and bus; based on this, the cache device in this embodiment is as follows: Figure 2 As shown, it also includes a bus bridge;
[0060] The first master terminal m'1 of the bus bridge is connected to the slave terminal s1 of the second bus switch; the first slave terminal s'1 is connected to the system bus, the second master terminal m'2 is connected to the system bus, and the second slave terminal s'2 is connected to the buffer.
[0061] The first master terminal m'1 to the first slave terminal s'1 of the bus bridge provides a path for reducing speed and bit width from the DSP to the bus; the second master terminal m'2 to the second slave terminal s'2 of the bus bridge provides a path for increasing speed and bit width from the system bus to the cache operating in TCM mode.
[0062] The bus bridge can be selected based on the bus type of the system bus and the cache device. For example, when both the system bus and the internal bus of the cache device are AXI buses, an AXI bus bridge can be used.
[0063] The AXI bus bridge can be implemented using existing IP cores. The implementation process is not within the protection scope of this utility model and will not be described in detail here. Any scheme that can perform clock cycle frequency and bit width conversion between AXI buses through existing technology can be applied to this utility model.
[0064] In a specific design of a buffer device that includes a bus bridge,
[0065] Cache / tcm caching operates in Cache mode.
[0066] The master terminal M1 of the first bus switch is connected to the slave terminal S2, and the connection with the slave terminal S1 is disconnected; the DSP is connected to the cache working in Cache mode through the master terminal M1 and the slave terminal S2 of the first bus switch.
[0067] The second master terminal m2 of the second bus switch is connected to the slave terminal s1, and the connection between the first master terminal m1 and the slave terminal s1 is disconnected; the cache working in Cache mode is connected to the first master terminal m'1 of the bus bridge through the second master terminal m2 and the slave terminal s1 of the second bus switch, and the first slave terminal s'1 of the bus bridge is connected to the system bus.
[0068] Disconnect the second slave end s'2 of the bus bridge from the buffer.
[0069] The DSP's read and write requests reach the cache through the first bus switch. The cache's read and write requests then reach the system bus through the second bus switch bus bridge, and finally reach the slave devices connected to the system bus, thus realizing data interconnection through the cache.
[0070] Cache / tcm caching operates in tcm mode.
[0071] The master terminal M1 of the first bus switch is connected to the first slave terminal S1, and disconnected from the second slave terminal S2.
[0072] The first master terminal m1 of the second bus switch is connected to the slave terminal s1, and the connection between the second master terminal m2 and the slave terminal s1 is disconnected.
[0073] The DSP is connected to the first master terminal m1 of the second bus switch via the first master terminal M1 and the first slave terminal S1 of the first bus switch. Then, it is connected to the first master terminal m'1 of the bus bridge via the first master terminal m1 and the slave terminal of the second bus switch. Then, it is connected to the system bus via the first slave terminal s'1 of the bus bridge. Then, it is connected to the second master terminal m'2 of the bus bridge via the system bus. Finally, it is connected to the cache operating in TCM mode via the second slave terminal s'2 of the bus bridge.
[0074] The DSP's read and write requests reach the bus bridge through the first bus switch and the second bus switch. After the bus bridge reduces the speed and bit width to match the system bus speed and bit width, the requests reach the bus bridge through the system bus connection. After the bus bridge increases the speed and bit width to match the cache speed and bit width, the requests reach the cache operating in TCM mode for data read and write access.
[0075] Furthermore, other master devices on the system bus interconnect are connected to the cache operating in TCM mode via the second master terminal m'2 of the bus bridge and then via the second slave terminal s'2 of the bus bridge.
[0076] Read and write requests from other master devices on the system bus interconnect can be processed by the bus bridge to achieve a speed and bit width that match the cache before reaching the cache operating in TCM mode for data read and write access.
[0077] In this embodiment, under TCM mode, the DSP and other master devices on the system bus interconnection can read and write access to the TCM cache.
[0078] In summary, the device disclosed in this embodiment, which is compatible with both cache and tcm operating modes, achieves compatibility and switching between the two cache operating modes, and also achieves speed and bit width matching between the DSP and the system bus.
[0079] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present utility model should be included within the protection scope of the present utility model.
Claims
1. A caching device compatible with Cache / TCM working mode, characterized in that, include: First bus switch, second bus switch, and Cache / tcm cache; The first bus switch is a one-to-two bus switch, and the second bus switch is a two-to-one bus switch. The master terminal M1 of the first bus switch is connected to the DSP, and the first slave terminal S1 is connected to the first master terminal m1 of the second bus switch; the second slave terminal S2 of the first bus switch is connected to the Cache / tcm buffer; the second master terminal m2 of the second bus switch is connected to the Cache / tcm buffer; the slave terminal s1 of the second bus switch is connected to the system bus; the system bus is also connected to the Cache / tcm buffer.
2. The cache device compatible with Cache / TCM working mode according to claim 1, characterized in that, Cache / tcm caching operates in Cache mode. The master terminal M1 of the first bus switch is connected to the slave terminal S2, and the connection with the slave terminal S1 is disconnected; the DSP is connected to the cache working in Cache mode through the master terminal M1 and the slave terminal S2 of the first bus switch. The second master terminal m2 of the second bus switch is connected to the slave terminal s1, and the connection between the first master terminal m1 and the slave terminal s1 is disconnected; the cache working in Cache mode is connected to the system bus through the second master terminal m2 and the slave terminal s1 of the second bus switch.
3. The caching device compatible with Cache / TCM working mode according to claim 1, characterized in that, Cache / tcm caching operates in tcm mode. The master terminal M1 of the first bus switch is connected to the first slave terminal S1, and disconnected from the second slave terminal S2. The first master terminal m1 of the second bus switch is connected to the slave terminal s1, and the connection between the second master terminal m2 and the slave terminal s1 is disconnected. The DSP is connected to the first master terminal m1 of the second bus switch via the first master terminal M1 and the first slave terminal S1 of the first bus switch. It is then connected to the system bus via the first master terminal m1 and the slave terminal of the second bus switch, and finally connected to the cache operating in TCM mode via the system bus.
4. The cache device compatible with Cache / TCM working mode according to claim 3, characterized in that, Cache / tcm caching operates in tcm mode. Other master devices on the system bus interconnect connect to the cache operating in TCM mode via the system bus to read and write cached data.
5. The cache device compatible with Cache / TCM working mode according to claim 1, characterized in that, The DSP and cache operate at the same frequency and bit width, which is higher than the frequency and bit width of the system bus. The cache device also includes a bus bridge; The first master terminal m'1 of the bus bridge is connected to the slave terminal s1 of the second bus switch; The first slave terminal s'1 is connected to the system bus, the second master terminal m'2 is connected to the system bus, and the second slave terminal s'2 is connected to the buffer. The first master terminal m'1 to the first slave terminal s'1 of the bus bridge provides a path for reducing speed and bit width from the DSP to the bus; the second master terminal m'2 to the second slave terminal s'2 of the bus bridge provides a path for increasing speed and bit width from the system bus to the cache operating in TCM mode.
6. The caching device compatible with Cache / TCM working mode according to claim 5, characterized in that, Cache / tcm caching operates in Cache mode. The master terminal M1 of the first bus switch is connected to the slave terminal S2, and the connection with the slave terminal S1 is disconnected; the DSP is connected to the cache working in Cache mode through the master terminal M1 and the slave terminal S2 of the first bus switch. The second master terminal m2 of the second bus switch is connected to the slave terminal s1, and the connection between the first master terminal m1 and the slave terminal s1 is disconnected; the cache working in Cache mode is connected to the first master terminal m'1 of the bus bridge through the second master terminal m2 and the slave terminal s1 of the second bus switch, and the first slave terminal s'1 of the bus bridge is connected to the system bus. Disconnect the second slave end s'2 of the bus bridge from the buffer.
7. The cache device compatible with Cache / TCM working mode according to claim 5, characterized in that, Cache / tcm caching operates in tcm mode. The master terminal M1 of the first bus switch is connected to the first slave terminal S1, and disconnected from the second slave terminal S2. The first master terminal m1 of the second bus switch is connected to the slave terminal s1, and the connection between the second master terminal m2 and the slave terminal s1 is disconnected. The DSP is connected to the first master terminal m1 of the second bus switch through the first master terminal M1 and the first slave terminal S1 of the first bus switch, and then connected to the first master terminal m'1 of the bus bridge through the first master terminal m1 and the slave terminal of the second bus switch, and then connected to the system bus through the first slave terminal s'1 of the bus bridge. Then, the second master terminal m'2 of the bus bridge is connected via the system bus, and the second slave terminal s'2 of the bus bridge is connected to the cache operating in TCM mode.
8. The cache device compatible with Cache / TCM working mode according to claim 7, characterized in that, Other master devices on the system bus interconnect are connected to the cache operating in TCM mode through the second master terminal m'2 of the bus bridge and then through the second slave terminal s'2 of the bus bridge.
9. The cache device compatible with Cache / TCM operating mode according to any one of claims 1-8, characterized in that, The DSP has a clock cycle of 600MHz and a width of 32 bits; the system bus has a clock cycle of 300MHz and a width of 16 bits.
10. The cache device compatible with Cache / TCM working mode according to claim 9, characterized in that, The system bus and the internal bus of the cache device are both AXI buses.