High-reliability external watchdog circuit built based on inverter and used for collector

Abstract

The utility model relates to the technical field of watchdog circuits, in particular to a high-reliability external watchdog circuit built based on an inverter for a collector, which comprises a signal input part, a first-order CR passive high-pass filter circuit, a signal amplification and reversing part, an RC timing reset output circuit, a reset output control part and a power supply part. According to the circuit design, low-frequency interference is filtered through a high-pass filter, it is ensured that a PWM signal can pass only when a system operates normally through signal amplification and reverse processing, and the reset pulse width is flexibly controlled through an RC timing circuit. In addition, the circuit adopts a low-cost inverter and a peripheral resistance-capacitance device, so that the cost is reduced, and the circuit design is simplified. The circuit can effectively avoid error reset caused by external electromagnetic interference, and the stability and reliability of a system are improved.

Description

Technical Field

[0001] This utility model relates to the field of watchdog circuit technology, specifically to a high-reliability external watchdog circuit based on an inverter for a data acquisition unit. Background Technology

[0002] An external watchdog circuit is a hardware circuit used to monitor the operating status of embedded systems or microcontrollers. Its main purpose is to ensure that the system does not enter an infinite loop or unpredictable state during normal operation, thereby preventing system crashes or stalls. External watchdog circuits typically operate by receiving periodic signals (i.e., "feed the dog" signals) from the monitored system. If the system fails to send this signal within a certain time, the watchdog circuit will trigger a reset signal, causing the system to restart and return to a known safe state. An external watchdog circuit based on an inverter for data acquisition is a circuit solution specifically designed for data acquisition. This circuit utilizes an inverter (such as a CMOS inverter) and its peripheral resistors and capacitors (resistors, capacitors, etc.) to achieve efficient monitoring and reset control of the terminal system (such as the data acquisition device).

[0003] In existing technologies, many external watchdog circuits built using inverters for data acquisition devices cannot flexibly adjust the reset pulse width, especially during system power-on startup, where the watchdog timer cannot be disabled, easily leading to abnormal resets. Some external watchdog circuits based on watchdog chips cannot effectively handle interference within the frequency range of the feed signal input from the main control chip, exhibiting poor electromagnetic compatibility and susceptibility to complex electromagnetic environments, resulting in false resets. Furthermore, external watchdog circuits built using high-end components such as watchdog chips or tri-state buffers are expensive and unsuitable for cost-sensitive applications.

[0004] In summary, to address the problems of uncontrollable reset pulse width, poor anti-interference capability, and high cost in existing technologies, designing a highly reliable external watchdog circuit based on an inverter for a data acquisition device is of great significance. Utility Model Content

[0005] To address the problems existing in the background technology, this utility model provides a highly reliable external watchdog circuit based on an inverter for a data acquisition device, which includes:

[0006] The signal input section includes the PWM transmit pin SIG_IN: which receives periodic PWM signals from the data acquisition unit;

[0007] A first-order CR passive high-pass filter circuit includes a high-pass filter circuit composed of resistors R1 and R2 and capacitor C1, which filters out interference signals below a specific frequency; capacitor C1 works with resistors R1 and R2 to set the cutoff frequency of the high-pass filter.

[0008] The signal amplification and inversion section includes transistor VT1, which acts as a signal amplifier. Its base receives the signal after high-pass filtering, and its collector outputs the amplified signal to the inverter. Inverter N1 inverts the signal output from VT1 and outputs it to the reset control section.

[0009] The RC timed reset output circuit includes resistors R3 and R4 and capacitors C2 and C4, which control the width of the reset pulse.

[0010] The reset output control section includes transistor VT2, which controls the on / off state of VT3 based on the output of inverter N1, thereby controlling the level state of the DOG_RST pin; MOSFETs VT3 (PMOS and NMOS) act as switching elements to control the power supply on / off state and realize the reset function; resistors R5, R6, and R7 work with VT2 and VT3 to ensure normal circuit operation; capacitor C5 helps stabilize the circuit state.

[0011] The power supply section, including the power supply VCC, VDD, and GND, provides electrical energy to the entire circuit.

[0012] In a preferred embodiment, the connection relationship of resistors R1, R2 and capacitor C1 in the first-order CR passive high-pass filter circuit is as follows: the PWM transmitting pin SIG_IN is connected to one end of resistor R1, the other end of resistor R1 is connected to one end of capacitor C1, the other end of capacitor C1 is connected to one end of resistor R2 and the base of transistor VT1, and the other end of resistor R2 and the emitter of transistor VT1 are both grounded.

[0013] In the preferred embodiment, the collector of transistor VT1 is connected to one end of resistor R3, and also to one end of capacitor C2 and pin 2 of inverter N1; the other end of capacitor C2 is connected to pin 3 of inverter N1 and grounded; pin 5 of inverter N1 is connected to power supply VCC and grounded through capacitor C3; pin 4 of inverter N1 is connected to one end of resistor R4, the other end of R4 is connected to the other end of resistor R3, one end of capacitor C4 and reset pin DOG_RST; the other end of capacitor C4 is grounded.

[0014] In the preferred embodiment, the reset pin DOG_RST is connected to one end of resistor R5, and the other end of R5 is connected to the base of transistor VT2; the emitter of transistor VT2 is grounded, and the collector is connected to one end of resistor R7; the other end of resistor R7 is connected to one end of resistor R6, one end of capacitor C5, and the gate of PMOS; the other end of capacitor C5 is connected to the other end of resistor R6, the source of NMOS, and power supply VDD; the drain of NMOS is connected to power supply VCC.

[0015] The beneficial effects achieved by this utility model are as follows:

[0016] First, this invention effectively filters out low-frequency interference signals from the external environment through a first-order CR passive high-pass filter circuit, ensuring that the watchdog signal can pass through without distortion only when the system is operating normally and the PWM signal frequency is higher than the set cutoff frequency. This design greatly reduces false resets caused by external electromagnetic interference, improving the stability and reliability of the system.

[0017] Secondly, the width of the reset pulse designed in this invention can be flexibly controlled by adjusting the values ​​of resistor R3 and capacitor C2 in the RC charging and discharging circuit. This design allows for precise setting of the reset duration based on the differences in signal lag at the initial power-on of different types of operating systems, effectively avoiding abnormal reset problems caused by signal lag.

[0018] Third, this invention abandons traditional high-cost watchdog chips or tri-state buffers, instead using inexpensive inverters and external resistors and capacitors to build the circuit. This design not only reduces hardware costs but also facilitates wider adoption in cost-sensitive applications. Using discrete components to build the circuit makes the overall design simpler and clearer, facilitating production and maintenance. Furthermore, reducing the use of high-end components also lowers supply chain complexity and potential risks. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of a highly reliable external watchdog circuit based on an inverter for a data acquisition unit. Detailed Implementation

[0020] The technical solution of this utility model will be clearly and completely described below with reference to the accompanying drawings. In addition, the forms of the various structures described in the following embodiments are merely illustrative. This utility model is not limited to the structures described in the following embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0021] Reference Figure 1The high-reliability external watchdog circuit based on an inverter for a data acquisition device, as described in this utility model, mainly consists of the following parts:

[0022] Signal input section:

[0023] PWM transmit pin (SIG_IN): Used to receive periodic PWM signals from the data acquisition unit.

[0024] First-order CR passive high-pass filter circuit:

[0025] Resistors R1 and R2, together with capacitor C1, form a high-pass filter circuit used to filter out interference signals below a specific frequency.

[0026] Capacitor C1: In conjunction with resistors R1 and R2, it sets the cutoff frequency of the high-pass filter.

[0027] Signal amplification and inversion section:

[0028] Transistor VT1: As a signal amplifier, its base receives the signal after high-pass filtering, and its collector outputs the amplified signal to the inverter.

[0029] Inverter N1: Inverts the signal output from VT1 and outputs it to the reset control section.

[0030] RC timer reset output circuit:

[0031] Resistors R3 and R4, together with capacitors C2 and C4, form an RC timing circuit used to control the width of the reset pulse.

[0032] Capacitors C2 and C4, together with resistors, enable timing functionality.

[0033] Reset output control section:

[0034] Transistor VT2: Controls the on / off state of VT3 based on the output of inverter N1, thereby controlling the level state of the DOG_RST pin.

[0035] MOSFET VT3 (PMOS and NMOS): As a switching element, it controls the power supply to turn on and off and realizes the reset function.

[0036] Resistors R5, R6, and R7: work in conjunction with VT2 and VT3 to ensure the circuit functions properly.

[0037] Capacitor C5: Auxiliary stabilizing circuit state.

[0038] Power supply section:

[0039] Power supply VCC, VDD, GND: Provides the necessary electrical energy for the entire circuit.

[0040] in:

[0041] The PWM transmit pin SIG_IN is connected to one end of resistor R1, and the other end of R1 is connected to one end of capacitor C1.

[0042] The other end of capacitor C1 is connected to one end of resistor R2 and the base of transistor VT1.

[0043] The other end of resistor R2 and the emitter of transistor VT1 are both grounded.

[0044] The collector of transistor VT1 is connected to one end of resistor R3, and also to one end of capacitor C2 and pin 2 of inverter N1.

[0045] The other end of capacitor C2 is connected to pin 3 of inverter N1 and ground.

[0046] Pin 5 of inverter N1 is connected to power supply VCC and grounded through capacitor C3.

[0047] Pin 4 of inverter N1 is connected to one end of resistor R4, and the other end of R4 is connected to the other end of resistor R3, one end of capacitor C4, and the reset pin DOG_RST.

[0048] The other end of capacitor C4 is grounded.

[0049] The reset pin DOG_RST is connected to one end of resistor R5, and the other end of R5 is connected to the base of transistor VT2.

[0050] The emitter of transistor VT2 is grounded, and the collector is connected to one end of resistor R7.

[0051] The other end of resistor R7 is connected to one end of resistor R6, one end of capacitor C5, and the gate of the PMOS.

[0052] The other end of capacitor C5 is connected to the other end of resistor R6, the source of the NMOS transistor, and the power supply VDD.

[0053] The drain of the NMOS is connected to the power supply VCC.

[0054] This invention discloses a high-reliability external watchdog circuit for a data acquisition device, built based on an inverter. During operation, a high-frequency PWM signal is input to the SIG_IN pin of the PWM transmitter. After processing by a high-pass filter circuit, VT1 is periodically turned on, causing the voltage at pin 2 of inverter N1 to be periodically discharged to a low potential. If the signal frequency is lower than the high-pass filter cutoff frequency, VT1 is turned off, and inverter N1 charges C2 through R3. When the voltage at pin 2 rises to a certain value, pin 4 outputs a low potential, triggering VT2 to turn on, thereby controlling the on / off state of VT3 and achieving a reset function. The width of the reset pulse can be flexibly set by adjusting the parameters of components such as R3 and C2 to adapt to the needs of different data acquisition systems. The specific working process is as follows:

[0055] Signal Input and Filtering: The PWM transmit pin SIG_IN receives the periodic PWM signal from the data acquisition unit. This signal is filtered by a first-order CR passive high-pass filter circuit consisting of resistors R1 and R2 and capacitor C1. The function of the high-pass filter circuit is to filter out low-frequency interference signals, ensuring that the signal can continue to be transmitted only when the frequency of the PWM signal is higher than the cutoff frequency of the high-pass filter.

[0056] Signal detection and amplification: The filtered PWM signal is input to the base of transistor VT1. When the PWM signal is high, VT1 is turned on, allowing current to flow from the collector to the emitter and discharge capacitor C2 through resistor R3. At this time, the voltage at pin 2 of inverter N1 is pulled low.

[0057] When the PWM signal is low, VT1 is cut off, capacitor C2 is slowly charged through resistor R3, and the input voltage of inverter N1 gradually increases.

[0058] Inverting and Reset Logic: Inverter N1 inverts the input signal. When the voltage at input pin 2 is lower than the inverter's threshold, output pin 4 outputs a low level; otherwise, it outputs a high level.

[0059] Under normal operating conditions, the data acquisition unit periodically sends PWM signals, and VT1 is periodically turned on and off, keeping the output of inverter N1 at a high level, thus preventing a reset operation from being triggered.

[0060] Reset operation: If the data acquisition unit fails to send PWM signals normally due to program crashes or external interference, or if the frequency of the PWM signal is lower than the cutoff frequency of the high-pass filter, VT1 will remain in the cutoff state for a long time, and capacitor C2 will continue to charge.

[0061] When the input voltage of inverter N1 rises above the threshold, its output becomes low. This low-level signal is transmitted to the base of transistor VT2 through resistors R4 and R5, turning it on.

[0062] The conduction of VT2 pulls the gate of MOSFET VT3 low. Assuming VT3 is a PMOS transistor, VT3 is turned off, thus cutting off the power supply path from VCC to the data acquisition unit. Simultaneously, the reset pin DOG_RST, connected to GND through resistor R5, is pulled low, resetting the data acquisition unit.

[0063] Reset pulse width adjustment: By adjusting the values ​​of resistor R3 and capacitor C2, the charging time of capacitor C2 can be changed, thereby controlling the duration of the low level output of inverter N1, i.e., the reset pulse width. This design allows for flexible setting of the reset duration according to the needs of different systems.

[0064] The high-reliability external watchdog circuit of this invention effectively filters out external interference signals through a first-order CR passive high-pass filter circuit, ensuring the accuracy of the reset operation. At the same time, by adjusting the parameters of the RC charging and discharging circuit, the reset pulse width can be flexibly controlled, which not only improves the stability and reliability of the system, but also reduces hardware costs and maintenance difficulty.

[0065] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A high-reliability external watchdog circuit based on an inverter for a data acquisition unit, characterized in that, It includes: The signal input section includes the PWM transmit pin SIG_IN: which receives periodic PWM signals from the data acquisition unit; A first-order CR passive high-pass filter circuit includes a high-pass filter circuit composed of resistors R1 and R2 and capacitor C1, which filters out interference signals below a specific frequency; capacitor C1 works with resistors R1 and R2 to set the cutoff frequency of the high-pass filter. The signal amplification and inversion section includes transistor VT1, which acts as a signal amplifier. Its base receives the signal after high-pass filtering, and its collector outputs the amplified signal to the inverter. Inverter N1 inverts the signal output from VT1 and outputs it to the reset control section. The RC timed reset output circuit includes resistors R3 and R4 and capacitors C2 and C4, which control the width of the reset pulse. The reset output control section includes transistor VT2, which controls the on / off state of VT3 based on the output of inverter N1, thereby controlling the level state of the DOG_RST pin; MOSFETs VT3 (PMOS and NMOS) act as switching elements to control the power supply on / off state and realize the reset function; resistors R5, R6, and R7 work with VT2 and VT3 to ensure normal circuit operation; capacitor C5 helps stabilize the circuit state. The power supply section, including the power supply VCC, VDD, and GND, provides electrical energy to the entire circuit.

2. The high-reliability external watchdog circuit based on an inverter for the data acquisition device according to claim 1, characterized in that, The connection relationship of resistors R1, R2 and capacitor C1 in the first-order CR passive high-pass filter circuit is as follows: the PWM transmitting pin SIG_IN is connected to one end of resistor R1, the other end of resistor R1 is connected to one end of capacitor C1, the other end of capacitor C1 is connected to one end of resistor R2 and the base of transistor VT1, and the other end of resistor R2 and the emitter of transistor VT1 are both grounded.

3. The high-reliability external watchdog circuit based on an inverter for the data acquisition device according to claim 2, characterized in that, The collector of transistor VT1 is connected to one end of resistor R3, and also to one end of capacitor C2 and pin 2 of inverter N1; the other end of capacitor C2 is connected to pin 3 of inverter N1 and ground; pin 5 of inverter N1 is connected to power supply VCC and grounded through capacitor C3; pin 4 of inverter N1 is connected to one end of resistor R4, the other end of R4 is connected to the other end of resistor R3, one end of capacitor C4 and the reset pin DOG_RST; the other end of capacitor C4 is grounded.

4. The high-reliability external watchdog circuit based on an inverter for the data acquisition device according to claim 3, characterized in that, The reset pin DOG_RST is connected to one end of resistor R5, and the other end of R5 is connected to the base of transistor VT2. The emitter of transistor VT2 is grounded, and the collector is connected to one end of resistor R7. The other end of resistor R7 is connected to one end of resistor R6, one end of capacitor C5, and the gate of the PMOS transistor. The other end of capacitor C5 is connected to the other end of resistor R6, the source of the NMOS transistor, and the power supply VDD. The drain of the NMOS transistor is connected to the power supply VCC.

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