Novel shield gate metal-oxide semiconductor field effect transistor

Abstract

The utility model relates to the technical field of semiconductors, and discloses a novel shield grid metal-oxide semiconductor field effect transistor, which comprises a groove, grid polycrystalline silicon and source polycrystalline silicon are arranged in the groove, a first oxide layer is arranged at the top of the source polycrystalline silicon, and a second oxide layer is arranged at the bottom of the first oxide layer. And a second oxide layer is arranged on the source polycrystalline silicon at a position not lower than the middle part of the source polycrystalline silicon. Due to the existence of the first oxide layer, the electric field line is more inclined to vertically pass through the oxide layer, the bending degree of the electric field line is reduced, the peak value of local electric field intensity is reduced, the second oxide layer in the middle can prevent the electric field line from being excessively concentrated in the middle of the source electrode field plate, and the peak of the electric field intensity is prevented from being formed. Therefore, the distribution uniformity of the electric field in the whole device is improved, the electric field of the optimized device is close to ideal rectangular distribution when the device is broken down, the purpose of improving the BV and Rsp compromise characteristics is achieved, and the power loss of the device is further reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to a novel shielded gate metal-oxide-semiconductor field-effect transistor. Background Technology

[0002] MOSFETs, being single-stage devices with no minority carrier storage, offer the advantage of high switching speeds. However, with technological advancements, MOSFET device dimensions have become increasingly smaller, leading to a rapid increase in the resistance of planar MOSFET JFETs (junction field-effect transistors), making them unsuitable for technological development. To address this issue of rapidly increasing JFET resistance, U-MOSFETs were invented. U-MOSFETs eliminate the JFET resistance, thus their development is not limited by advancements in device miniaturization. However, the feedback capacitance Cgd of U-MOSFETs increases significantly with further miniaturization, resulting in a rapid increase in device switching losses.

[0003] To address the drawback of U-MOSFET feedback capacitance increasing rapidly as device size decreases, Baliga proposed the Shielded Gate Metal-Oxide-Semiconductor Field-Effect Transistor (SGT MOSFET) in 2002. Compared to traditional U-MOSFETs and planar MOSFETs, this type of MOSFET can significantly improve the trade-off characteristics of Rsp (specific on-resistance) and Qg (gate charge), thereby reducing energy consumption.

[0004] Although SGT MOSFETs have significantly improved the trade-off between Rsp and Qg, the breakdown voltage (BV) and Rsp still need to be improved during the device design process (Rsp increases with BV). Traditional SGT device structures have a suspension bridge-like electric field distribution during breakdown (breakdown voltage is the integral of the electric field; a rectangular electric field distribution is ideal), which prevents the full utilization of the structure's advantages. Furthermore, in practical designs, a 10% BV margin is typically maintained to prevent insufficient voltage and failure during early use (e.g., a 30V device designed with a breakdown voltage of 33V).

[0005] Therefore, in order to obtain an ideal rectangular electric field distribution, this invention optimizes the source field plate based on the traditional SGT MOSFET. The optimized device has an electric field distribution close to the ideal rectangular shape during breakdown, thus achieving the goal of improving the trade-off characteristics of BV and Rsp. Utility Model Content

[0006] To address the technical problem that the electric field distribution of traditional SGT devices is a suspension bridge distribution during breakdown, which prevents the full utilization of the advantages of the structure, and to prevent the device from failing due to insufficient voltage in the early stages of use, the device generally maintains a 10% BV margin in the actual design process, resulting in power loss, this utility model provides a novel shielded gate metal-oxide-semiconductor field-effect transistor.

[0007] This utility model is achieved by the following technical solution: a novel shielded gate metal-oxide-semiconductor field-effect transistor, comprising an N-type substrate, an N-type epitaxial layer, a P-type well region, a heavily doped N-type region, a heavily doped P-type region, and a trench, wherein the N-type epitaxial layer is located on the N-type substrate, the P-type well region is located on top of the N-type epitaxial layer, and both the heavily doped N-type region and the heavily doped P-type region are located on top of the P-type well region;

[0008] The N-type epitaxial layer and the central portion of the P-type well region are provided with a vertical trench. The trench is provided with gate polysilicon and source polysilicon. The top of the source polysilicon is provided with a first oxide layer, and the source polysilicon is provided with a second oxide layer at a position not lower than its middle part.

[0009] Preferably, a heavily doped N-type region is provided on both sides of the trench on the P-type well region, and a heavily doped P-type region is provided on both sides away from the trench. The heavily doped N-type region and the heavily doped P-type region are respectively connected to the source metal.

[0010] Preferably, a dielectric layer is provided between the gate polysilicon sidewall and the P-type well region and the heavily doped N-type region.

[0011] Preferably, the gate polysilicon and the source polysilicon are isolated by an intermediate oxide layer, and the insulating dielectric layer between the source polysilicon and the trench sidewall is composed of a sidewall oxide layer, silicon nitride, and another sidewall oxide layer.

[0012] Preferably, the insulating dielectric layer between the source polysilicon and the bottom of the trench is composed of other oxide layers.

[0013] Preferably, the back side of the N-type substrate is provided with drain metal.

[0014] Compared with the prior art, the beneficial effects of this utility model are:

[0015] This invention introduces a first oxide layer on top of the source polysilicon and a second oxide layer in the middle. The presence of the first oxide layer at the top makes the electric field lines more inclined to pass through the oxide layer perpendicularly, reducing the curvature of the electric field lines and thus reducing the peak value of the local electric field intensity. The second oxide layer in the middle can prevent the electric field lines from being excessively concentrated in the middle of the source field plate, avoiding the formation of electric field intensity spikes. This improves the uniformity of the electric field distribution inside the entire device, making the electric field of the optimized device close to the ideal rectangular distribution during breakdown. This achieves the purpose of improving the trade-off characteristics of BV and Rsp, and further reduces the power loss of the device. Attached Figure Description

[0016] Figure 1 Schematic diagram of the cross-section of the overall field-effect transistor provided by this utility model Figure 1 ;

[0017] Figure 2 This is a schematic cross-section of the field-effect transistor of this invention. Figure 2 .

[0018] In the figure: 1. N-type substrate; 2. N-type epitaxial layer; 3. P-type well region; 4. Heavily doped N-type region; 5. Heavily doped P-type region; 6. Trench; 7. Source metal; 8. Gate polysilicon; 9. Source polysilicon; 901. First oxide layer; 902. Second oxide layer; 10. Drain metal. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0020] Please see Figure 1 - Figure 2 This embodiment of a novel shielded gate metal-oxide-semiconductor field-effect transistor includes an N-type substrate 1, an N-type epitaxial layer 2, a P-type well region 3, a heavily doped N-type region 4, a heavily doped P-type region 5, and a trench 6. The N-type epitaxial layer 2 is located on the N-type substrate 1, the P-type well region 3 is located on top of the N-type epitaxial layer 2, and both the heavily doped N-type region 4 and the heavily doped P-type region 5 are located on the P-type well region 3.

[0021] Furthermore, a vertical trench 6 is provided in the middle part between the N-type epitaxial layer 2 and the P-type well region 3. A heavily doped N-type region 4 is provided on both sides of the trench 6 on the P-type well region 3, and a heavily doped P-type region 5 is provided on both sides away from the trench 6. The heavily doped N-type region 4 and the heavily doped P-type region 5 are respectively connected to the source metal 7. A dielectric layer is provided between the sidewall of the gate polysilicon 8 and the P-type well region 3 and the heavily doped N-type region 4.

[0022] Furthermore, the trench 6 is provided with a gate polysilicon 8 and a source polysilicon 9. The top of the source polysilicon 9 is provided with a first oxide layer 901, and the source polysilicon 9 is provided with a second oxide layer 902 at a position not lower than its middle part. The gate polysilicon 8 and the source polysilicon 9 are isolated by an intermediate oxide layer. The insulating dielectric layer between the source polysilicon 9 and the sidewall of the trench 6 is composed of a sidewall oxide layer-silicon nitride-sidewall oxide layer. The insulating dielectric layer between the source polysilicon 9 and the bottom of the trench 6 is composed of other oxide layers. The back side of the N-type substrate 1 is provided with a drain metal 10.

[0023] Specifically, when the SGT MOSFET is in the on state, since the gate voltage is higher than the threshold voltage, a conductive channel is formed between the source and the drain. Electrons flow from the source through the trench and into the drift region at the bottom of the trench gate to the drain. The entire device changes from the blocking state to the on state. When it is in the on state, the change of the gate voltage will affect the flow of electrons in the trench, thereby controlling the current between the source and the drain.

[0024] In this embodiment, a first oxide layer 901 is provided on the top of the source polysilicon 9. Without the first oxide layer 901 on the top, the electric field lines will bend or concentrate on the top of the source field plate, resulting in excessively high electric field strength. After the first oxide layer 901 is introduced, the presence of the top oxide layer makes the electric field lines more inclined to pass through the oxide layer perpendicularly, reducing the bending degree of the electric field lines and thus reducing the peak value of the local electric field strength.

[0025] In this embodiment, a second oxide layer 902 is provided on the source polysilicon 9 at a position not lower than its middle part. The second oxide layer 902 in the middle part can form an additional electric field barrier inside the source field plate, which can divide the source field plate into upper and lower parts, making the electric field distribution between the two parts more uniform. Specifically, the second oxide layer 902 in the middle part can prevent the electric field lines from being excessively concentrated in the middle of the source field plate, avoid the formation of electric field intensity peaks, and thus improve the uniformity of the electric field distribution inside the entire device.

[0026] Working principle: Through the optimized combination of the first oxide layer 901 and the second oxide layer 902 in the embodiments of this application, the electric field of the optimized device can be close to the ideal rectangular distribution during breakdown. The optimized electric field distribution is more uniform, the peak value of the electric field intensity is reduced, the device can withstand higher voltage, and the local resistance on the current conduction path is reduced. This achieves the purpose of improving the trade-off characteristics of BV and Rsp and reducing the power loss of the device.

[0027] In addition to the above embodiments, users may also introduce three or more thin oxide layers at other locations on the source field plate according to voltage requirements.

[0028] The above embodiments are merely preferred embodiments of this utility model and should not be construed as limiting the scope of protection of this utility model. Any non-substantial changes and substitutions made by those skilled in the art based on this utility model shall fall within the scope of protection claimed by this utility model.

Claims

1. A novel shielded gate metal-oxide-semiconductor field-effect transistor, characterized in that, It includes an N-type substrate, an N-type epitaxial layer, a P-type well region, a heavily doped N-type region, a heavily doped P-type region, and a trench. The N-type epitaxial layer is located on the N-type substrate, the P-type well region is located on top of the N-type epitaxial layer, and both the heavily doped N-type region and the heavily doped P-type region are located on top of the P-type well region. The N-type epitaxial layer and the central portion of the P-type well region are provided with a vertical trench. The trench is provided with gate polysilicon and source polysilicon. The top of the source polysilicon is provided with a first oxide layer, and the source polysilicon is provided with a second oxide layer at a position not lower than its middle part.

2. The novel shielded gate metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, A heavily doped N-type region is located on both sides of the trench in the P-type well region, and a heavily doped P-type region is located on both sides away from the trench. The heavily doped N-type region and the heavily doped P-type region are respectively connected to the source metal.

3. The novel shielded gate metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, A dielectric layer is provided between the gate polysilicon sidewall and the P-type well region and the heavily doped N-type region.

4. A novel shielded gate metal-oxide-semiconductor field-effect transistor according to claim 3, characterized in that, The gate polysilicon and the source polysilicon are isolated by an intermediate oxide layer, and the insulating dielectric layer between the source polysilicon and the trench sidewall is composed of a sidewall oxide layer, silicon nitride, and another sidewall oxide layer.

5. A novel shielded gate metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The insulating dielectric layer between the source polysilicon and the bottom of the trench is composed of other oxide layers.

6. A novel shielded gate metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The N-type substrate has a drain metal on its back side.

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