Heterojunction solar cell and heterojunction solar cell module
By employing a design that cross-connects fine grid lines and main grid lines in heterojunction solar cells, the distribution of grid line electrodes is optimized, solving the problems of photoelectric conversion efficiency and manufacturing cost in existing technologies, and achieving more efficient photoelectric conversion and cost reduction.
Patent Information
- Application Number
- CN202422923607.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-11-11
- Estimated Expiration
- 2034-11-28
AI Technical Summary
Existing grid electrode designs for heterojunction solar cells have issues that affect photoelectric conversion efficiency and manufacturing costs.
The design employs multiple fine gate lines, with adjacent sub-gate lines spaced apart and electrically connected through a transparent conductive film layer. This, combined with the cross-electrical connection between the main gate line and the fine gate line, optimizes the distribution of the gate line electrodes.
It improves photoelectric conversion efficiency, reduces resistance and manufacturing costs, and ensures printing quality.
Smart Images
Figure CN223540876U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of photovoltaic technology, and in particular to a heterojunction solar cell and a heterojunction solar cell module. Background Technology
[0002] Fossil fuels cause air pollution and have limited reserves, while solar energy has advantages such as being clean, pollution-free, and abundant. Therefore, solar energy is gradually becoming a core clean energy source to replace fossil fuels, and due to the excellent photoelectric conversion efficiency of solar cells, solar cells have become the focus of development in clean energy utilization.
[0003] Existing heterojunction solar cells have grid electrodes printed on their surface. The main function of these grid electrodes is to collect and transmit the current generated by the photovoltaic effect. Therefore, the design and optimization of these grid electrodes are crucial for improving the photoelectric conversion efficiency of heterojunction solar cells and modules, and for reducing manufacturing costs. Summary of the Invention
[0004] Therefore, it is necessary to provide a new heterojunction solar cell and a heterojunction solar cell module.
[0005] One technical solution of this application is: a heterojunction solar cell, comprising a semiconductor substrate, a transparent conductive film layer disposed on the semiconductor substrate, and grid line electrodes disposed on the transparent conductive film layer. The transparent conductive film layer is located between the semiconductor substrate and the grid line electrodes. The grid line electrodes include multiple fine grid lines, at least a portion of which include several sub-grid lines. Adjacent sub-grid lines are spaced apart to form a line gap, and adjacent sub-grid lines are electrically connected at the line gap through the transparent conductive film layer.
[0006] In one embodiment, the fine gate lines extend along a first direction, and multiple fine gate lines are distributed along a second direction; adjacent sub-gate lines are spaced apart in the first direction to form the line gap, and the width of the line gap ranges from 10μm to 800μm.
[0007] In one embodiment, two adjacent sub-gate lines of the fine gate line extend out of alignment in a first direction.
[0008] In one embodiment, the fine grid lines extend along a first direction, and multiple fine grid lines are spaced apart along a second direction; adjacent sub-grid lines of the fine grid lines are spaced apart in the second direction and form the line gap.
[0009] In one embodiment, the sub-gate line includes a widened gradient end, and the line gap is formed between two adjacent widened gradient ends.
[0010] In one embodiment, the fine gate lines extend along a first direction, and a plurality of the fine gate lines are distributed along a second direction; the gate line electrode further includes a plurality of main gate lines, the main gate lines extend at intervals along the second direction, the plurality of main gate lines are distributed at intervals along the first direction, and the main gate lines are electrically connected to the fine gate lines.
[0011] In one embodiment, at least one of the fine grid lines is spaced apart from adjacent sub-grid lines to form a gap, and the main grid line is provided with a bridging portion located at the gap and electrically bridging the two adjacent sub-grid lines that form the gap.
[0012] In one embodiment, the main gate line overlaps and is electrically connected to at least a portion of the fine gate lines in a second direction, and the sub-gate lines are provided with a widened gradient connection portion at the overlap.
[0013] In one embodiment, the sub-gate line includes a slit, and the main gate line includes a connecting portion at the slit that electrically connects the sub-gate line.
[0014] In one embodiment, the semiconductor substrate includes a first side and a second side disposed opposite to each other, wherein the transparent conductive film layer and the gate electrode are stacked on the first side and / or the second side; wherein, when the gate electrode is distributed on the first side and the second side, the gate electrode on the first side and the gate electrode on the second side are disposed symmetrically or asymmetrically.
[0015] This utility model also discloses a heterojunction solar cell module, which includes a solder strip and a plurality of heterojunction solar cells as described above, electrically connected by the solder strip.
[0016] The beneficial effects of this application are as follows: The grid electrode includes multiple fine grid lines, at least a portion of which include several sub-grid lines. Adjacent sub-grid lines are spaced apart to form a gap, and adjacent sub-grid lines are electrically connected at the gap through a transparent conductive film layer. The fine grid lines are distributed on the transparent conductive film layer, and the segmented arrangement of the fine grid lines forms several sub-grid lines. Adjacent sub-grid lines are electrically connected through the transparent conductive film layer that carries the sub-grid lines, ensuring the printing quality of the fine grid lines, saving paste, reducing resistance, improving photoelectric conversion efficiency, and reducing manufacturing costs. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the cross-sectional structure of the heterojunction solar cell of this application;
[0018] Figure 2 This is a schematic diagram of the layered structure of the semiconductor substrate of the heterojunction solar cell of this application;
[0019] Figure 3 This is a schematic diagram of the planar structure of the heterojunction solar cell of this application;
[0020] Figure 4 for Figure 3 Enlarged view of center circle A;
[0021] Figure 5 for Figure 3 Enlarged view of center circle B;
[0022] Figure 6 for Figure 3 An enlarged view of the center circle C;
[0023] Figure 7 for Figure 4 An enlarged schematic diagram of another embodiment;
[0024] Figure 8 for Figure 4 An enlarged schematic diagram of another embodiment;
[0025] Figure 9 for Figure 5 An enlarged schematic diagram of another embodiment;
[0026] Figure 10 This is a schematic diagram of another cross-sectional structure of the heterojunction solar cell of this application;
[0027] Figure 11 This is a schematic diagram of another cross-sectional structure of the heterojunction solar cell of this application;
[0028] Figure 12 This is a schematic diagram of another cross-sectional structure of the heterojunction solar cell of this application;
[0029] Figure 13 This is a schematic diagram of another partial planar structure of the heterojunction solar cell of this application;
[0030] Figure 14 This is a schematic diagram of another partial planar structure of the heterojunction solar cell of this application;
[0031] Figure 15 This is a schematic diagram of another partial planar structure of the heterojunction solar cell of this application. Detailed Implementation
[0032] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described below. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.
[0033] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0035] This invention discloses a heterojunction solar cell, comprising a semiconductor substrate, a transparent conductive film layer disposed on the semiconductor substrate, and grid electrodes disposed on the transparent conductive film layer. The transparent conductive film layer is located between the semiconductor substrate and the grid electrodes. The grid electrodes include multiple fine grid lines, at least a portion of which include several sub-grid lines. Adjacent sub-grid lines are spaced apart to form line gaps, and adjacent sub-grid lines are electrically connected at the line gaps through the transparent conductive film layer. The fine grid lines are distributed in the transparent conductive film layer, and the segmented fine grid lines form several sub-grid lines. Adjacent sub-grid lines are electrically connected through the transparent conductive film layer that carries the sub-grid lines, ensuring the printing quality of the fine grid lines, saving paste, reducing resistance, improving photoelectric conversion efficiency, and reducing manufacturing costs.
[0036] Preferably, the semiconductor substrate comprises a P-type silicon thin film, an intrinsic silicon thin film, an N-type silicon wafer, another intrinsic silicon thin film, and another N-type silicon thin film stacked sequentially. The transparent conductive film layer is an ITO conductive film.
[0037] Furthermore, the semiconductor substrate includes a first side and a second side disposed opposite to each other, with a transparent conductive film layer and gate electrodes stacked on the first side and / or the second side. Specifically, the transparent conductive film layer and gate electrodes are stacked on the first side; or, the transparent conductive film layer and gate electrodes are stacked on the second side; or, the first side and the second side are respectively stacked with a transparent conductive film layer and gate electrodes. When the gate electrodes are distributed on the first side and the second side, the gate electrodes on the first side and the gate electrodes on the second side are symmetrically or asymmetrically arranged. The gate electrodes on the first side and the second side can adopt the same design and layout, or they can adopt different designs and layouts.
[0038] In one embodiment, fine gate lines extend along a first direction, and multiple fine gate lines are spaced apart along a second direction; adjacent sub-gate lines are spaced apart in the first direction to form a gap, the width of which ranges from 10 μm to 800 μm. For example, the first direction is the X direction, and the second direction is a direction perpendicular to the first direction. Here, "along the first direction" includes: defining a 0-degree direction, extending towards the first direction within ±45° of the 0-degree direction; and also including being located on the same straight line in the same angular direction, or on two or more parallel straight lines that are staggered. For example, adjacent sub-gate lines of the fine gate lines extend in a staggered manner in the first direction. The second direction is similarly configured.
[0039] In one embodiment, two adjacent sub-grid lines of a fine grid are spaced apart in a second direction to form a line gap. The width of the line gap in the second direction is greater than or equal to the width of the sub-grid line and less than or equal to 1 / 2 the spacing width of the adjacent fine grid lines in the second direction. If adjacent sub-grid lines extend in a staggered manner in the first direction and overlap in projection in the second direction, then the line gap can be considered to be in the second direction, and the line gap satisfies the above requirements.
[0040] In one example, the sub-grid line includes widened gradient ends, with a line gap formed between adjacent widened gradient ends. The width of the ends is widened relative to other parts of the sub-grid line and gradually narrows towards the end. It can be set to its widest point at the top and then begin to narrow, or it can maintain a maximum width for a certain period before narrowing. It can gradually narrow to the width of the sub-grid line, or it can stop narrowing arbitrarily and abruptly reach the sub-grid line width via a step.
[0041] In one embodiment, the grid electrode further includes multiple main grid lines extending along a second direction and spaced apart along a first direction. The main grid lines are electrically connected to the fine grid lines. The heterojunction solar cell of this invention can be a gridless structure or a structure with main grids. The main grid lines extend continuously along the second direction and penetrate through each fine grid line. In other embodiments, the main grid lines extend discontinuously along the second direction or only include a fork-like structure at the ends, and are similarly electrically connected to the penetrating fine grid lines.
[0042] In one embodiment, at least one fine grid line has adjacent sub-grid lines spaced apart to form a gap, and the main grid line has a bridging portion located at the gap and electrically bridging the two adjacent sub-grid lines forming the gap. The fine grid line with the gap does not have a line spacing; instead, a gap is formed between adjacent sub-grid lines, and this gap is electrically connected through the bridging portion on the main grid line, thereby ensuring printing quality and expanding the design and optimization of the grid line electrodes.
[0043] In one embodiment, the main grid line overlaps and is electrically connected to at least a portion of the fine grid lines in a first direction, and the sub-grid lines are provided with a widened gradient connection at the overlap. The widened gradient connection includes a widened section and gradient sections extending from both ends of the widened section to both sides, ensuring electrical connection with the main grid line and effectively avoiding the risk of wire breakage during subsequent soldering.
[0044] In one embodiment, the sub-gate line includes a slit, and the main gate line includes a connecting portion at the slit that electrically connects the sub-gate line. The fine gate line may be further split and electrically connected through the connecting portion of the main gate line.
[0045] This utility model also discloses a heterojunction solar cell module, which includes a solder strip and a plurality of heterojunction solar cells as described above electrically connected by the solder strip, thereby improving photoelectric conversion efficiency and reducing manufacturing costs.
[0046] Please refer to the following: Figures 1 to 15 The heterojunction solar cell of this invention is described by way of example.
[0047] Please refer to Figures 1 to 6 This utility model discloses a heterojunction solar cell 100, which includes a semiconductor substrate 1, a transparent conductive film layer 2, and grid electrodes. The semiconductor substrate 1 includes a first side and a second side disposed opposite to each other. The transparent conductive film layer 2 and the grid electrodes are sequentially stacked on the first side, and the transparent conductive film layer 2 and the grid electrodes are sequentially stacked on the second side.
[0048] The semiconductor substrate 1 includes a P-type silicon thin film 11, an intrinsic silicon thin film 12, an N-type silicon wafer 13, an intrinsic silicon thin film 12, and an N-type silicon thin film 14, which are stacked sequentially. The side of the N-type silicon thin film 14 away from the intrinsic silicon thin film 12 is designated as the first side 141, and the side of the P-type silicon thin film 11 away from the intrinsic silicon thin film 12 is designated as the second side 111. The transparent conductive film layers 2 are ITO conductive films coated on the first side 141 and the second side 111, respectively.
[0049] The gate electrode includes multiple fine gate lines 3 and multiple main gate lines 4. The fine gate lines 3 are in direct contact with the ITO conductive film, and the main gate lines 4 are covered with both the fine gate lines 3 and the ITO conductive film. The fine gate lines 3 extend along a first direction X and are spaced apart along a second direction Y perpendicular to the first direction X; the main gate lines 4 extend along the second direction Y and are spaced apart along the first direction X. The main gate lines 4 intersect with each of the fine gate lines 3 and are electrically connected to the fine gate lines 3 at the intersection. Each fine gate line 3 includes several sub-gate lines 31, with adjacent sub-gate lines 31 spaced apart to form a line gap 32. Adjacent sub-gate lines 31 are electrically connected at the line gap 32 through the underlying transparent conductive film layer 2, ensuring the printing quality of the fine gate lines 3, saving paste, reducing resistance, improving photoelectric conversion efficiency, and reducing manufacturing costs. In other embodiments, the main gate lines 4 are in direct contact with the ITO conductive film, and the fine gate lines 3 cover both the main gate lines 4 and the ITO conductive film.
[0050] The line gap 32 has a width W ranging from 10 μm to 800 μm in the first direction X. A widened gradient connection portion is provided on the sub-gate line 31, comprising a widened section 311 and gradient sections 312 extending from both ends of the widened section 311 to both sides. When the main gate line 4 intersects with the sub-gate line 31, the main gate line 4 overlaps on the widened section 311 and achieves electrical connection. The main gate line 4 includes a harpoon structure 41 and a shuttle-shaped pad 42. The harpoon structure 41 is located at the end of the main gate line 4, and the shuttle-shaped pad 42 is located at the intersection with the sub-gate line 31 and is electrically connected to the sub-gate line 31.
[0051] Please refer to Figure 4 The sub-gate line 31 has a uniform width at its end at the line gap 32. In other embodiments, please refer to... Figure 7 The end of sub-grid line 31 is a widened gradient end 313, which gradually narrows from its widest point. Please refer to... Figure 8 The end of the sub-grid line 31 is a widened gradient end 314, which maintains a maximum width for a period of time and then gradually narrows.
[0052] Please refer to Figure 9 The sub-grid line 31 includes a slit 315, and the main grid line 4 includes a connecting portion 43 that electrically connects the sub-grid line 31 at the slit 315. The connecting portion 43 has a widened and gradually tapered structure and extends along a first direction to electrically connect the sub-grid line 31 at the slit 315. The sub-grid lines 31 can be uniformly arranged, widened, or broken when connected to the connecting portion 43.
[0053] Please refer to Figure 10 This invention discloses another heterojunction solar cell 200, which is a single-sided solar cell. The heterojunction solar cell 200 includes a semiconductor substrate 51, a transparent conductive film layer 52, and grid line electrodes. The transparent conductive film layer 52 and the grid line electrodes are disposed on a first side of the semiconductor substrate 51. The grid line electrodes include fine grid lines 53 and main grid lines 54. The fine grid lines 53 include a plurality of sub-grid lines 531. Adjacent sub-grid lines 531 are spaced apart to form a line gap 532. Adjacent sub-grid lines 531 are electrically connected at the line gap 532 through the transparent conductive film layer 52.
[0054] Please refer to Figure 11 This invention discloses another heterojunction solar cell 300, which is a gridless solar cell. The heterojunction solar cell 300 includes a semiconductor substrate 61, a transparent conductive film layer 62, and grid line electrodes. The transparent conductive film layer 62 and grid line electrodes are disposed on both the first and second sides of the semiconductor substrate 61. The grid line electrodes include fine grid lines 63, each fine grid line 63 comprising a plurality of sub-grid lines 631. Adjacent sub-grid lines 631 are spaced apart, forming a line gap 632. Adjacent sub-grid lines 631 are electrically connected at the line gap 632 through the transparent conductive film layer 62.
[0055] Please refer to Figure 12 This invention discloses another heterojunction solar cell 400, which differs from the heterojunction solar cell 300 in that the heterojunction solar cell 400 is a single-sided gridless cell.
[0056] Please refer to Figures 13 to 15 This illustrates the distribution of the gate line structure in other embodiments. Please refer to... Figure 13 The gate line structure includes a fine gate line 71 and a main gate line 72. The fine gate line 71 includes a sub-gate line 711 and a line gap 712. The fine gate line 71 extends along a first direction X, and the sub-gate line 711 extends in a staggered manner along the first direction X. The width W2 of the line gap 712 ranges from 10μm to 800μm. A widened gradient connection portion 7111 is provided on the sub-gate line 711, which overlaps with and is electrically connected to the main gate line 72.
[0057] Please refer to Figure 14 The gate structure includes fine gate lines 81 and main gate lines 82. The fine gate lines 81 include sub-gate lines 811 and line gaps 812. The fine gate lines 81 extend along a first direction X. The sub-gate lines 811 extend in a staggered manner in the first direction X and overlap in projection in the second direction Y. The width range W3 of the line gaps 812 in the second direction is greater than or equal to the width D of the sub-gate lines 811 and less than or equal to 1 / 2 the spacing width L of adjacent fine gate lines 81.
[0058] Please refer to Figure 15 The gate structure includes a first fine gate line 91, a second fine gate line 92, and a main gate line 93. The first fine gate line 91 includes a first sub-gate line 911 and a gap 912. The second fine gate line 92 includes a second sub-gate line 921 and a gap 922. The main gate line 93 is electrically connected to both the first fine gate line 91 and the second fine gate line 92. The main gate line 93 includes a bridging portion 931, which is located at the gap 922 and electrically connected to the second sub-gate lines 921 located on both sides of the gap 922. No gap is provided at the second sub-gate line 921 corresponding to the gap 912. The bridging portion 931 can be configured as a pad for the main gate line 93.
[0059] To make the above-described objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application have been described in detail above with reference to the accompanying drawings. Many specific details have been set forth in the above description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described above, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed above. Furthermore, the technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described; however, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.
[0060] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A heterojunction solar cell, characterized in that, It includes a semiconductor substrate, a transparent conductive film layer disposed on the semiconductor substrate, and a gate electrode disposed on the transparent conductive film layer. The transparent conductive film layer is located between the semiconductor substrate and the gate electrode. The gate electrode includes a plurality of fine gate lines, at least a portion of which include a plurality of sub-gate lines. Adjacent sub-gate lines are spaced apart to form a line gap, and adjacent sub-gate lines are electrically connected at the line gap through the transparent conductive film layer.
2. The heterojunction solar cell according to claim 1, characterized in that, The fine grid lines extend along a first direction, and multiple fine grid lines are spaced apart along a second direction; adjacent sub-grid lines are spaced apart in the first direction and form the line gap, the width of which ranges from 10μm to 800μm.
3. The heterojunction solar cell according to claim 2, characterized in that, The two adjacent sub-grid lines of the fine grid line extend out of alignment in a first direction.
4. The heterojunction solar cell according to claim 1, characterized in that, The fine grid lines extend along a first direction, and multiple fine grid lines are spaced apart along a second direction; adjacent sub-grid lines of the fine grid lines are spaced apart in the second direction and form the line gap.
5. The heterojunction solar cell according to claim 1, characterized in that, The sub-grid line includes a widened gradient end, and the line gap is formed between two adjacent widened gradient ends.
6. The heterojunction solar cell according to claim 1, characterized in that, The fine gate line extends along a first direction, and multiple fine gate lines are spaced apart along a second direction; the gate line electrode also includes multiple main gate lines, which extend along the second direction and are spaced apart along the first direction, and the main gate lines are electrically connected to the fine gate lines.
7. The heterojunction solar cell according to claim 6, characterized in that, At least one of the fine grid lines is spaced apart from adjacent sub-grid lines to form a gap, and the main grid line is provided with a bridging portion located at the gap and electrically bridging the two adjacent sub-grid lines that form the gap.
8. The heterojunction solar cell according to claim 6, characterized in that, The main grid line overlaps and is electrically connected to at least a portion of the fine grid lines in the second direction, and the sub-grid lines are provided with a widened gradient connection portion at the overlap.
9. The heterojunction solar cell according to claim 6, characterized in that, The sub-gate line includes a slit, and the main gate line includes a connecting portion at the slit that electrically connects the sub-gate line.
10. The heterojunction solar cell according to claim 1, characterized in that, The semiconductor substrate includes a first side and a second side disposed opposite to each other, wherein the transparent conductive film layer and the gate electrode are stacked on the first side and / or the second side; wherein, when the gate electrode is distributed on the first side and the second side, the gate electrode on the first side and the gate electrode on the second side are disposed symmetrically or asymmetrically.
11. A heterojunction solar cell module, characterized in that, It includes solder strips and several heterojunction solar cells as claimed in any one of claims 1 to 10, electrically connected by said solder strips.