FPGA hardware platform device
By simulating different chips under test using an FPGA hardware platform, the problems of long testing cycles and insufficient flexibility in traditional MCU functional verification testing are solved, achieving efficient and flexible functional verification testing.
Patent Information
- Application Number
- CN202422983393.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-12-04
AI Technical Summary
Traditional MCU functional verification and testing methods suffer from long verification and testing cycles and insufficient flexibility.
Using an FPGA hardware platform, configuration files are transmitted to the FPGA chip circuit via an external host computer to simulate different chips under test. Based on the functional program file, the functional module circuit is controlled to realize the functional verification test of the chip under test.
It improves the compatibility and flexibility of verification testing, reduces the testing cycle, and enhances the efficiency and accuracy of verification testing.
Smart Images
Figure CN223552096U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, and further to an FPGA hardware platform device. Background Technology
[0002] In traditional microcontroller (MCU) functional verification testing, the common practice is to connect one or more of the MCU's functional interfaces to a single circuit board to perform specific functional verifications. However, given that MCUs are typically equipped with a rich set of functional interfaces, this verification testing method has significant limitations. It not only significantly extends the verification testing cycle but also restricts the flexibility of the verification testing process. Utility Model Content
[0003] To address the aforementioned technical issues, this application provides an FPGA hardware platform device that not only reduces the verification and testing cycle but also improves the flexibility of the verification and testing process.
[0004] In a first aspect, this application provides an FPGA hardware platform device for functional verification testing of a chip, comprising: an FPGA test baseboard; a functional module circuit disposed on the FPGA test baseboard; and an FPGA core board disposed on the FPGA test baseboard, the FPGA core board including an FPGA chip circuit, a first connector, a second connector, and a third connector; the FPGA chip circuit is connected to the FPGA test baseboard via the first connector, the second connector, and the third connector, and is also connected to an external host computer; when the FPGA chip circuit receives a configuration file and a function program file sent by the external host computer, the FPGA chip circuit is configured to simulate the FPGA hardware platform device as the chip under test based on the configuration file, and the FPGA chip circuit is configured to control the functional module circuit based on the function program file to complete the functional verification test of the chip under test.
[0005] The FPGA hardware platform described above, through the transmission of configuration files from an external host computer to the FPGA chip circuit, can flexibly simulate different chips under test (DUTs). This high degree of configurability greatly enhances the compatibility of verification testing. Secondly, the FPGA chip circuit can control functional module circuits based on different functional program files, thereby enabling the verification testing of the peripheral functions of various DUTs. Due to the parallel processing capabilities of the FPGA, verification testing of all functional interfaces of the DUT can be completed on a single circuit board, not only reducing the verification testing cycle but also increasing the flexibility of the verification testing process.
[0006] In one implementation, the FPGA core board further includes: a flash memory chip circuit connected to the FPGA chip circuit, configured to receive the configuration file and simulate the FPGA hardware platform device as the chip under test based on the configuration file; and an oscillator chip circuit connected to the FPGA chip circuit, configured to provide a clock signal to the FPGA hardware platform device.
[0007] The FPGA hardware platform described above transmits the configuration file to the FPGA chip circuit via an external host computer, allowing users to perform single verification tests on the chip under test (DUT). Furthermore, after the FPGA hardware platform is powered on again, a new configuration file can be transmitted via the host computer to accommodate the functional verification test requirements of different DUTs. Secondly, for DUTs requiring multiple functional verification tests, users can choose to transmit the configuration file to the non-volatile memory in the flash memory chip circuit. This way, even after the FPGA hardware platform is powered off and on again, the configuration file is retained, allowing users to perform functional verification tests again without repeatedly transmitting the configuration file, thus improving verification testing efficiency and flexibility.
[0008] In one implementation, the functional module circuit includes: a plurality of USB circuits, each connected to the FPGA chip circuit and configured to perform USB function verification tests on the chip under test; and a CAN module circuit, connected to the FPGA chip circuit and configured to perform CAN function verification tests on the chip under test.
[0009] In one implementation, the plurality of USB circuits includes a first USB circuit, the first USB circuit comprising: a fourth connector connected to the FPGA chip circuit via a ribbon cable; a first USB transceiver chip connected to the fourth connector; and a first USB interface chip, wherein the differential data positive pin and differential data negative pin of the first USB interface chip are respectively connected to the differential data positive pin and differential data negative pin of the first USB transceiver chip; the differential data negative pin of the first USB interface chip is connected to a first power supply via a first pull-up resistor and is configured to verify and test a full-speed USB device.
[0010] The above FPGA hardware platform device can simulate full-speed and non-full-speed USB devices by adjusting the pull-up resistors of the differential data pins D- and D+ of the first USB interface chip, thereby performing comprehensive verification tests on the USB function of the chip under test and improving the flexibility and accuracy of the verification tests.
[0011] In one implementation, the differential data positive pin of the first USB interface chip is connected to the first power supply via a second pull-up resistor and is configured to verify and test non-full-speed USB devices.
[0012] In one implementation, the plurality of USB circuits further includes a second USB circuit, the second USB circuit comprising: a second USB transceiver chip connected to the FPGA chip circuit via multiple sets of isolation resistors; and a second USB interface chip, wherein the positive and negative data line pins of the second USB interface chip are respectively connected to the positive and negative data line pins of the second USB transceiver chip.
[0013] In one implementation, the second USB circuit further includes: a power supply chip connected to the second USB transceiver chip, wherein the input terminal of the power supply chip is connected to the first power supply through the isolation resistor, and the output terminal of the power supply chip is grounded through a first resistor and a second resistor connected in series; and a clock circuit connected to the second USB transceiver chip and configured to provide a clock signal to the second USB transceiver chip.
[0014] In one implementation, the CAN module circuit includes: a fifth connector, the data transmission pin and data reception pin of the fifth connector being connected to the FPGA chip circuit via jumper caps; a CAN transceiver chip, the data transmission pin and data reception pin of the CAN transceiver chip being respectively connected to the data reception pin and data transmission pin of the fifth connector; and a CAN interface chip, connected to the CAN transceiver chip.
[0015] In one implementation, the FPGA chip circuit includes an FPGA chip, the flash memory chip circuit includes a flash memory chip, and the oscillator chip circuit includes an oscillator chip; the FPGA chip is connected to the external host computer and the flash memory chip respectively; the output terminal of the oscillator chip is connected to the clock pin of the FPGA chip.
[0016] In one implementation, the functional module circuit further includes: an Ethernet interface circuit configured to perform Ethernet function testing of the chip under test; and a button circuit configured to perform button function testing of the chip under test.
[0017] Compared with the prior art, the present invention has at least one of the following beneficial effects:
[0018] 1. By transmitting configuration files to the FPGA chip circuit via an external host computer, the FPGA hardware platform can be flexibly simulated as different chips under test (DUTs). This high configurability greatly enhances the compatibility of verification testing. Secondly, the FPGA chip circuit can control functional module circuits based on different functional program files, thereby enabling verification testing of the peripheral functions of various DUTs. Due to the parallel processing capabilities of the FPGA, verification testing of all functional interfaces of the DUT can be completed on a single circuit board, reducing the verification testing cycle and increasing the flexibility of the verification testing process.
[0019] 2. The configuration file can be transferred to the FPGA chip circuit via an external host computer, allowing users to perform single verification tests on the chip under test (DUT). Furthermore, after the FPGA hardware platform is powered on again, a new configuration file can be transferred via the host computer to accommodate the functional verification test requirements of different DUTs. Secondly, for DUTs requiring multiple functional verification tests, users can choose to transfer the configuration file to the non-volatile memory in the flash memory chip circuit. This way, the configuration file is retained even after the FPGA hardware platform is powered off and on again, allowing users to perform functional verification tests again without repeatedly transferring the configuration file, improving verification testing efficiency and flexibility.
[0020] 3. By adjusting the pull-up resistors of the differential data pins D- and D+ of the first USB interface chip, full-speed and non-full-speed USB devices can be simulated, thereby enabling comprehensive verification testing of the USB function of the chip under test and improving the flexibility and accuracy of the verification test. Attached Figure Description
[0021] The preferred embodiments will be described below in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages and implementation methods of this utility model.
[0022] Figure 1 This paper shows a structural block diagram of an FPGA hardware platform device provided in an embodiment of the present application;
[0023] Figure 2 This paper shows a structural block diagram of an FPGA core board provided in an embodiment of this application;
[0024] Figure 3 A circuit diagram of an FPGA chip circuit provided in an embodiment of this application is shown;
[0025] Figure 4 A circuit diagram of a flash memory chip circuit provided in an embodiment of this application is shown;
[0026] Figure 5A circuit diagram of an oscillator chip circuit provided in an embodiment of this application is shown;
[0027] Figure 6 A circuit diagram of a first USB circuit provided in an embodiment of this application is shown;
[0028] Figure 7 A circuit diagram of a second USB circuit provided in an embodiment of this application is shown;
[0029] Figure 8 A circuit diagram of a multi-group isolation resistor provided in an embodiment of this application is shown;
[0030] Figure 9 A circuit diagram of a CAN module circuit provided in an embodiment of this application is shown;
[0031] Figure 10 A circuit diagram of a first download circuit provided in an embodiment of this application is shown. Detailed Implementation
[0032] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the specific implementation methods of this utility model will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of this utility model. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.
[0033] To keep the drawings concise, each figure only schematically shows the parts relevant to the utility model, and these do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of the components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."
[0034] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0035] In this document, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0036] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0037] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of this utility model. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.
[0038] An FPGA (Field-Programmable Gate Array) is a programmable semiconductor device that allows users to program and reconfigure its hardware logic using software tools to achieve specific functions. For example, FPGAs can be programmed after production, allowing users to customize hardware functions as needed. Furthermore, FPGAs can execute multiple operations simultaneously, making them highly efficient in handling complex algorithms and real-time tasks. This application's embodiments construct an FPGA hardware platform device by setting up an FPGA core board and functional module circuits on an FPGA test baseboard, and transmitting the configuration file (or bit file converted from RTL) to the FPGA core board, so that the FPGA hardware platform device simulates the chip under test (or the MCU chip under test). Simultaneously, the functional program file of the chip under test is transmitted to the FPGA core board, thereby completing the functional verification test of the chip under test. This achieves at least one of the following beneficial effects: verification testing of all functional interfaces of the chip under test can be completed on a single circuit board, not only reducing the verification test cycle but also improving the flexibility of the verification test process; or functional testing and verification of the chip under test can be performed during the design phase of the chip under test; and multiple chips under test can be simulated to achieve functional verification testing of multiple chips under test, thereby improving the compatibility of verification testing.
[0039] Reference Appendix Figure 1 This illustrates a structural block diagram of an FPGA hardware platform device provided in an embodiment of this application. Figure 1 As shown, it includes: FPGA test baseboard, functional module circuit ( Figure 1 (Not shown), FPGA core board. Both the FPGA core board and functional module circuits are mounted on the FPGA test baseboard (the FPGA core board is connected to the FPGA test baseboard via a precision connector). The FPGA core board includes the FPGA chip circuitry (…). Figure 1 (not shown), first connector (see attached) Figure 1 FX10A-168S connector 1), second connector (see attached) Figure 1FX10A-168S connector 2) and third connector (see attached) Figure 1 The FPGA chip circuit is connected to the FPGA test baseboard via the first connector, the second connector, and the third connector, and is also connected to an external host computer. When the FPGA chip circuit receives the configuration file and function program file sent by the external host computer, the FPGA chip circuit is configured to simulate the FPGA hardware platform device as the chip under test based on the configuration file, and the FPGA chip circuit is configured to control the function module circuit based on the function program file to complete the functional verification test of the chip under test.
[0040] The FPGA hardware platform device uses the first download circuit (see attached diagram). Figure 1 The FPGA hardware platform device is connected to an external host computer via a first download circuit (XILINX JTAG) and a second download circuit (ARM JTAG), and is also connected to an external power supply. The external host computer transmits the configuration file to the FPGA chip circuit on the FPGA hardware platform device via the first download circuit. The FPGA chip circuit then simulates the FPGA hardware platform device as the chip under test (DUT) based on the configuration file. Next, the external host computer transmits the function program files for different peripherals of the DUT to the FPGA chip circuit via the second download circuit, enabling the FPGA chip circuit to control the function module circuits based on the function program files to complete the functional verification test of the DUT. Different configuration files can simulate the FPGA hardware platform device as different DUTs, and thus, different DUTs can be functionally verified using the function program files for their corresponding peripherals. The function module circuits include a 12V power input circuit, a 12V to 1.8V step-down power supply circuit, a 12V to 3.3V step-down power supply circuit, and a 12V to 5V step-down power supply circuit, which can provide 12V, 5V, 3.3V, and 1.8V voltages to the FPGA hardware platform device.
[0041] This application embodiment transmits configuration files to the FPGA chip circuit via an external host computer, enabling the FPGA hardware platform device to flexibly simulate different chips under test. This high degree of configurability greatly improves the compatibility of verification testing. Secondly, the FPGA chip circuit can control functional module circuits based on different functional program files, thereby realizing the verification testing of the peripheral functions of various chips under test. Due to the parallel processing capability of the FPGA, the verification testing of all functional interfaces of the chip under test can be completed on a single circuit board, which not only reduces the verification testing cycle but also improves the flexibility of the verification testing process.
[0042] Reference Appendix Figure 2 This illustrates a structural block diagram of an FPGA core board provided in an embodiment of this application. Figure 2As shown, it includes: FPGA chip circuit (see attached diagram). Figure 2 The KU060 FPGA chip and flash memory chip circuit are shown in the attached document. Figure 2 The MT25QL256 chip and oscillator chip circuit are shown in the attached diagram. Figure 2 The SIT80088 chip is used in this example. The flash memory chip circuit is connected to the FPGA chip circuit and is configured to receive a configuration file and simulate the FPGA hardware platform device as the chip under test based on the configuration file. The oscillator chip circuit is connected to the FPGA chip circuit and is configured to provide a clock signal to the FPGA hardware platform device (the oscillator chip circuit can provide a 100MHz clock signal to the FPGA hardware platform device).
[0043] An external host computer can transfer configuration files to the FPGA chip circuitry, or vice versa, from the FPGA chip circuitry to the non-volatile memory in the flash memory chip circuitry. When a user performs a functional verification test on a specific chip under test, the configuration file can be transferred to the FPGA chip circuitry. When the FPGA hardware platform is powered off and then powered on again, the FPGA chip circuitry will not save the configuration file. Furthermore, the user can transfer a new configuration file to the FPGA chip circuitry or the flash memory chip circuitry again via the external host computer, thereby completing the functional verification test of the new chip under test.
[0044] Furthermore, if a user needs to perform multiple functional verification tests on a certain chip under test, the configuration file can be transferred to the non-volatile memory in the flash memory chip circuit. In this way, when the FPGA hardware platform device is powered off and then powered on again, the flash memory chip circuit still stores the configuration file, and the functional verification test can be performed on the chip under test again.
[0045] Non-volatile memory includes, but is not limited to, read-only memory (ROM), programmable read-only memory (PROM), electrically rewritable read-only memory (EAROM), erasable programmable read-only memory (EPROM), and flash memory.
[0046] This application embodiment transmits the configuration file to the FPGA chip circuit via an external host computer, allowing the user to perform a single verification test on the chip under test (DUT). Furthermore, after the FPGA hardware platform device is powered on again, a new configuration file can be transmitted via the host computer to accommodate the functional verification test requirements of different DUT chips. Secondly, for DUT chips requiring multiple functional verification tests, the user can choose to transmit the configuration file to the non-volatile memory in the flash memory chip circuit. This way, even after the FPGA hardware platform device is powered off and on again, the configuration file is retained, allowing the user to perform functional verification tests again without repeatedly transmitting the configuration file, thus improving verification test efficiency and flexibility.
[0047] Reference Appendix Figure 3 , 4 Figures 5 and 6 respectively illustrate circuit diagrams of an FPGA chip circuit, a flash memory chip circuit, and an oscillator chip circuit provided in embodiments of this application. Figure 3 As shown, it includes: an FPGA chip (see attached document). Figure 3 (U2A and U2J chips in the example). Figure 4 As shown, it includes: flash memory chips (see attached document). Figure 4 (U1 chip), resistors R1, R2, and R3. For example... Figure 5 As shown, it includes: an oscillator chip (see attached document). Figure 5 (XT2 chip in the middle).
[0048] The FPGA chip's pins JTAG_TCK, JTAG_TDI, JTAG_TDO, and JTAG_TMS are connected via the first download circuit (see attached). Figure 10 Peripheral function downloader J8 is connected to the peripheral via connector J15. Figure 10 The illustrated FX10A-168S-SV connector connects to an external host computer to receive configuration files sent by the host computer. The FPGA chip connects to the flash memory chip via a series of FLASH pins. The FPGA chip connects to the OUT terminal of the oscillator chip via the clock pin CLK_100M to receive the clock signal generated by the oscillator chip. The flash memory chip is connected to the 3.3V_VCCIO power supply via resistors R1, R2, and R3, which are used for voltage division. The VOD terminal of the oscillator chip is connected to the 3.3V_VCCIO power supply, and the oscillator chip's ground terminal GND is grounded.
[0049] When users perform functional verification tests on the chip under test, the configuration file can be transferred to the FPGA chip or flash memory chip according to user requirements. At the same time, the functional program file of the chip under test can be transferred to the FPGA chip so that the FPGA chip can control the functional module circuit to complete the functional verification test of the chip under test.
[0050] In one embodiment of this application, the functional module circuit includes multiple USB circuits, each connected to an FPGA chip circuit and configured to perform USB function verification tests on the chip under test; a CAN module circuit, connected to the FPGA chip circuit, is configured to perform CAN function verification tests on the chip under test. The multiple USB circuits include a first USB circuit and a second USB circuit. (See attached document.) Figure 1 The first USB circuit consists of a USB 1.1 PHY chip, a USB 1.1 Type-B interface, and a separate USB 1.1 PHY interface I / O; the second USB circuit includes... Figure 1 The circuit includes a USB 2.0 PHY chip and a USB 2.0B interface; the CAN module circuit includes a CAN PHY chip and a separate CAN interface.
[0051] Reference Appendix Figure 6 This illustrates a circuit diagram of a first USB circuit provided in an embodiment of this application. Figure 6 As shown, it includes: the fourth connector J26 (equivalent to the attached...) Figure 1 The independent USB 1.1 PHY interface IO), the first USB transceiver chip U42 (equivalent to the attached) Figure 1 The USB 1.1 PHY chip and the first USB interface chip J14 (equivalent to the attached) Figure 1 The fourth connector J26 is connected to the FPGA chip circuit via a ribbon cable (i.e., the fourth connector J26 is connected to the FPGA chip via a ribbon cable); the first USB transceiver chip U42 is connected to the fourth connector J26; the differential data positive pin D+ and differential data negative pin D- of the first USB interface chip J14 are respectively connected to the differential data positive pin D+ and differential data negative pin D- of the first USB transceiver chip U42; the differential data negative pin D- of the first USB interface chip J14 is connected to the first power supply VCC_3V3 through the first pull-up resistor R54, and is configured to verify and test full-speed USB devices. The differential data positive pin D+ of the first USB interface chip J14 is connected to the first power supply VCC_3V3 through the second pull-up resistor R55, and is configured to verify and test non-full-speed USB devices. The differential data positive pin D+ and differential data negative pin D- of the first USB interface chip J14 are connected to external USB devices.
[0052] When users perform functional verification tests on the chip under test (DUT), configuration files can be transferred to the FPGA chip or flash memory chip according to user requirements. The FPGA hardware platform device is then used to simulate the DUT, and the DUT's functional program files are transferred to the FPGA chip. This allows for functional verification testing of the DUT. For example, to verify the USB function of the DUT, the FPGA chip sends a USB function verification test signal to the first USB transceiver chip U42 via the fourth connector. The first USB transceiver chip U42 converts the function verification test signal into the USB protocol and sends it to the first USB interface chip J14. The first USB interface chip J14 then interfaces with an external USB device according to the converted USB protocol, thereby completing the USB function verification test of the DUT.
[0053] Furthermore, if, during the USB function verification test, the differential data negative pin D- of the first USB interface chip J14 is connected to the first power supply VCC_3V3 through the first pull-up resistor R54, and the differential data positive pin D+ of the first USB interface chip J14 is not connected to the second pull-up resistor R55, then the USB function verification test of the chip under test is essentially a verification test of a full-speed USB device. Similarly, if the differential data negative pin D- of the first USB interface chip J14 is not connected to the first pull-up resistor R54, and the differential data positive pin D+ of the first USB interface chip J14 is connected to the first power supply VCC_3V3 through the second pull-up resistor R55, then the USB function verification test of the chip under test is essentially a verification test of a non-full-speed USB device (or a low-speed USB device).
[0054] In this embodiment, by adjusting the pull-up resistors of the differential data pins D- and D+ of the first interface chip, full-speed and non-full-speed USB devices can be simulated, thereby enabling comprehensive verification testing of the USB function of the chip under test and improving the flexibility and accuracy of the verification test.
[0055] Reference Appendix Figure 7 This illustrates a circuit diagram of a second USB circuit provided in an embodiment of this application. Figure 7 As shown, it includes: a second USB transceiver chip U41 (equivalent to an attached...) Figure 1 The USB 2.0 PHY chip and the second USB interface chip J13 (equivalent to the attached) Figure 1 The second USB transceiver chip U41 is connected to the FPGA chip circuit through multiple sets of isolation resistors; the positive data line pin DP and the negative data line pin DM of the second USB interface chip J13 are respectively connected to the positive data line pin DP and the negative data line pin DM of the second USB transceiver chip.
[0056] The second USB transceiver chip U41 is connected to the FPGA chip's I / O interface in the FPGA chip circuit through multiple sets of isolation resistors, wherein the multiple sets of isolation resistors (see attached) Figure 8 The resistance of the first resistor is 0 ohms. A 0-ohm resistor can serve functions such as attenuation, isolation, and matching. The positive data line pin DP and the negative data line pin DM of the second USB interface chip J13 are connected to the external USB device, respectively.
[0057] When users perform functional verification tests on the chip under test (DUT), configuration files can be transferred to the FPGA chip or flash memory chip according to user requirements. The FPGA hardware platform device is then used to simulate the DUT, and the functional program files of the DUT are transferred to the FPGA chip. This allows for functional verification testing of the DUT. For example, to verify the USB function of the DUT, the FPGA chip sends the USB function verification test signal to the second USB transceiver chip U41 through multiple sets of isolation resistors. The second USB transceiver chip U41 converts the function verification test signal into the USB protocol and sends it to the second USB interface chip J13. The second USB interface chip J13 then interfaces with the external USB device according to the converted USB protocol, thereby completing the USB function verification test of the DUT.
[0058] In one embodiment of this application, reference is made to the appendix. Figure 7 The second USB circuit also includes: a power supply chip U43, connected to the second USB transceiver chip U41, with the input terminal VIN of the power supply chip U43 connected to the first power supply VCC_3V3 through an isolation resistor R90, and the output terminal VOUT of the power supply chip U43 grounded after being connected in series with a first resistor R1 and a second resistor R2. A clock circuit, connected to the second USB transceiver chip U41, is configured to provide a clock signal to the second USB transceiver chip U41.
[0059] The voltage at the output terminal VOUT of power chip U43 is related to the first resistor R1 and the second resistor R2. By changing the resistance values of the first resistor R1 and the second resistor R2, the voltage at the output terminal VOUT of power chip U43 is changed. Specifically, the voltage at the output terminal VOUT of power chip U43 is 1.25*(1+R2 / R1).
[0060] The clock circuit includes a clock chip X1. The XI pin of clock chip X1 is connected to the XI pin of the second USB transceiver chip U41 and grounded through capacitor C114. The XO pin of clock chip X1 is connected to the XO pin of the second USB transceiver chip U41 and grounded through capacitor C113. Clock chip X1 provides a 24MHz clock signal to the second USB transceiver chip U41.
[0061] Reference Appendix Figure 9The diagram illustrates a circuit diagram of a CAN module circuit provided in an embodiment of this application. Figure 9 As shown, it includes: fifth connector J33, CAN transceiver chip U45 (equivalent to the attached...) Figure 1 The CAN PHY chip in the middle), CAN interface chip J32 (equivalent to the attached chip) Figure 1 (Independent CAN interface). The data transmit pin CAN_TXD and data receive pin CAN_RXD of the fifth connector J33 are connected to the FPGA chip circuit via jumper caps; the data transmit pin CAN_TXD and data receive pin CAN_RXD of the CAN transceiver chip U45 are respectively connected to the data receive pin CAN_RXD and data transmit pin CAN_TXD of the fifth connector J33; the CAN interface chip J32 is connected to the CAN transceiver chip U45.
[0062] The data transmit pin CAN_TXD and data receive pin CAN_RXD of the fifth connector J33 are connected to the FPGA chip in the FPGA chip circuit via jumper caps; the CAN_H pin and CAN_L pin of the CAN transceiver chip U45 are connected to the CAN interface chip J32. The CAN interface chip J32 is also connected to resistors R60 and R61, which are used to match the characteristic impedance of the CAN bus, reduce signal reflection, and improve communication reliability. The CAN interface chip J32 also connects to external CAN devices via the CAN bus.
[0063] When users perform functional verification tests on the chip under test (DUT), configuration files can be transferred to the FPGA chip or flash memory chip according to user requirements. The FPGA hardware platform device simulates the DUT, and the functional program files of the DUT are simultaneously transferred to the FPGA chip, enabling functional verification testing. For example, to verify the CAN function of the DUT, the FPGA chip sends the CAN function verification test signal to the CAN transceiver chip U45 via the fifth connector J33. The CAN transceiver chip U45 converts the CAN function verification test signal into the CAN protocol and sends it to the CAN interface chip J32. The CAN interface chip J32 then interfaces with an external CAN device according to the converted CAN protocol, thereby completing the CAN function verification test of the DUT.
[0064] Furthermore, in different configuration files, the CAN module circuit will have multiple data transmission pins CAN_TXD and data reception pins CAN_RXD. That is, the FPGA chip can allocate multiple pins to connect multiple data transmission pins CAN_TXD and data reception pins CAN_RXD in the CAN module circuit through jumper caps, thereby enabling multiple sets of CAN function verification tests to be completed.
[0065] In one embodiment of this application, reference is made to the appendix. Figure 1 The functional module circuit also includes an Ethernet interface circuit, configured to perform Ethernet function tests on the chip under test; and a button circuit (see attached diagram). Figure 1 The circuit includes a KEY button circuit, configured to perform button function tests on the chip under test; an SD card circuit and independent SD interface I / O; an SPI function circuit and independent SPI interface I / O; an I2C function circuit and independent I2C interface I / O; and a UART function circuit and independent UART interface I / O.
[0066] The Ethernet interface circuit supports direct connection to an Ethernet module for testing, and the connection between the Ethernet interface and the FPGA chip I / O is shorted using a jumper cap. The SD card circuit supports direct insertion of an SD card for testing, and the connection between the independent SD interface I / O and the FPGA chip I / O is shorted using a jumper cap. The SPI function circuit uses a W25Q128 flash chip, and the independent SPI interface I / O can be connected to different pins of the FPGA chip via a connecting wire, allowing testing of multiple SPI functions. The I2C function circuit uses an AT24C02 chip, and the independent I2C interface I / O can be connected to different pins of the FPGA chip via a connecting wire, allowing testing of multiple I2C functions. The UART function circuit uses a CH340 chip and a USB_B connector, and the USART function can be tested by connecting a USB cable. The independent UART interface I / O can be connected to different pins of the FPGA chip via a connecting wire, allowing testing of multiple USART functions.
[0067] In one embodiment of this application, reference is made to the appendix. Figure 1 The FPGA test baseboard also has reserved I / O interfaces for expanding functionality.
[0068] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of this utility model. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.
Claims
1. An FPGA hardware platform device for functional verification testing of a chip, characterized in that, include: FPGA test baseboard; Functional module circuit, wherein the functional module circuit is mounted on the FPGA test baseboard; An FPGA core board is mounted on the FPGA test baseboard, and the FPGA core board includes an FPGA chip circuit, a first connector, a second connector, and a third connector. The FPGA chip circuit is connected to the FPGA test baseboard through the first connector, the second connector and the third connector respectively, and the FPGA chip circuit is also connected to an external host computer. When the FPGA chip circuit receives the configuration file and function program file sent by the external host computer, the FPGA chip circuit is configured to simulate the FPGA hardware platform device as the chip under test based on the configuration file, and the FPGA chip circuit is configured to control the function module circuit based on the function program file to complete the functional verification test of the chip under test.
2. The FPGA hardware platform device according to claim 1, characterized in that, The FPGA core board also includes: A flash memory chip circuit, connected to the FPGA chip circuit, is configured to receive the configuration file and, based on the configuration file, simulate the FPGA hardware platform device as the chip under test. An oscillator chip circuit, connected to the FPGA chip circuit, is configured to provide a clock signal to the FPGA hardware platform device.
3. The FPGA hardware platform device according to claim 1, characterized in that, The functional module circuit includes: Multiple USB circuits are connected to the FPGA chip circuit and are configured to perform USB function verification tests on the chip under test. The CAN module circuit is connected to the FPGA chip circuit and is configured to perform CAN function verification tests on the chip under test.
4. The FPGA hardware platform device according to claim 3, characterized in that, The plurality of USB circuits include a first USB circuit, the first USB circuit comprising: The fourth connector is connected to the FPGA chip circuit via a ribbon cable; The first USB transceiver chip is connected to the fourth connector; The first USB interface chip has its differential data positive pin and differential data negative pin connected to the differential data positive pin and differential data negative pin of the first USB transceiver chip, respectively. The differential data negative pin of the first USB interface chip is connected to the first power supply through the first pull-up resistor and is configured to verify and test full-speed USB devices.
5. The FPGA hardware platform device according to claim 4, characterized in that, The differential data positive pin of the first USB interface chip is connected to the first power supply through a second pull-up resistor and is configured to verify and test non-full-speed USB devices.
6. The FPGA hardware platform device according to claim 3, characterized in that, The plurality of USB circuits further include a second USB circuit, the second USB circuit comprising: The second USB transceiver chip is connected to the FPGA chip circuit through multiple sets of isolation resistors; The second USB interface chip has its positive and negative data line pins connected to the positive and negative data line pins of the second USB transceiver chip, respectively.
7. The FPGA hardware platform device according to claim 6, characterized in that, The second USB circuit also includes: A power chip is connected to the second USB transceiver chip, and the input terminal of the power chip is connected to the first power supply through the isolation resistor. The output terminal of the power chip is grounded after being connected in series with the first resistor and the second resistor. A clock circuit, connected to the second USB transceiver chip, is configured to provide a clock signal to the second USB transceiver chip.
8. The FPGA hardware platform device according to claim 3, characterized in that, The CAN module circuit includes: The fifth connector, wherein the data transmission pin and the data reception pin of the fifth connector are connected to the FPGA chip circuit via jumper caps; A CAN transceiver chip, wherein the data transmit pin and data receive pin of the CAN transceiver chip are respectively connected to the data receive pin and data transmit pin of the fifth connector; A CAN interface chip is connected to the CAN transceiver chip.
9. The FPGA hardware platform device according to claim 2, characterized in that, The FPGA chip circuit includes an FPGA chip, the flash memory chip circuit includes a flash memory chip, and the oscillator chip circuit includes an oscillator chip. The FPGA chip is connected to the external host computer and the flash memory chip respectively; The output of the oscillator chip is connected to the clock pin of the FPGA chip.
10. The FPGA hardware platform device according to claim 1, characterized in that, The functional module circuit also includes: An Ethernet interface circuit is configured to perform Ethernet function tests on the chip under test. The button circuit is configured to perform button function tests on the chip under test.