Chip test board, chip test device and test system
By designing a chip test board and device compatible with multiple memory chips, the problem of only being able to test a single chip in the existing technology has been solved, and efficient multi-chip compatibility testing and automated detection have been achieved.
Patent Information
- Application Number
- CN202422483349.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-10-14
AI Technical Summary
In the existing technology, the testing equipment for memory chips can only test one type of chip, resulting in low testing efficiency. Furthermore, the equipment needs to be changed when different types of chips are replaced, which consumes time and manpower.
Design a chip test board that integrates different types of connectors to adapt to various memory chips, and combines a chip test socket and a robotic arm to achieve automated batch testing, supporting compatibility testing of various memory chips.
It enables compatibility testing of various memory chips, improves testing efficiency, reduces the time and manpower costs of replacing equipment, and supports large-scale automated testing.
Smart Images
Figure CN223552255U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, and in particular to a chip test board, a chip test device, and a test system. Background Technology
[0002] With the development of information technology, memory chips are widely used as carriers of information, and various types of memory chips have been developed to meet different application needs. After an application system is developed or designed, it is usually necessary to conduct compatibility tests on multiple different types of memory chips in order to perform corresponding checks and debugging based on test failures.
[0003] Traditional testing methods use a single testing device. The memory chip to be tested is integrated into this device, which communicates with a PC to perform testing. Especially when testing different types of memory chips, a separate, compatible testing device must be used, making it impossible to perform multi-chip compatible testing and resulting in low testing efficiency. Utility Model Content
[0004] The purpose of this application is to provide a chip test board, a chip test device, and a test system to simultaneously perform compatibility tests on different types of memory chips, thereby improving test efficiency.
[0005] This application discloses a chip test board, which includes a circuit board, gold fingers, a power chip, and multiple connectors. The gold fingers are disposed on one side of the circuit board, and the power chip and the connectors are disposed on the surface of the circuit board. The connectors are electrically connected to the gold fingers and the power chip, respectively. The connectors are at least divided into a first connector and a second connector, and the first connector and the second connector are respectively connected to different types of chip test sockets.
[0006] Optionally, the circuit board includes a first arrangement area, a second arrangement area, and a third arrangement area, wherein the second arrangement area is located between the first arrangement area and the third arrangement area; the chip test board includes a plurality of first connectors and a plurality of second connectors, wherein the plurality of first connectors are disposed in the first arrangement area and the third arrangement area, and the plurality of second connectors are disposed in the second arrangement area.
[0007] Optionally, the first arrangement area and the third arrangement area have the same area, and a plurality of the first connectors are arranged in arrays in the first arrangement area and the third arrangement area respectively; the area of the second arrangement area is smaller than the area of the first arrangement area, and a plurality of the second connectors are arranged in the second arrangement area along the length direction of the second arrangement area.
[0008] Optionally, the first connector includes a first connection port and a second connection port, which are arranged side-by-side on the circuit board, and one of the first connection ports and one of the second connection ports are simultaneously connected to a chip test socket; the second connector includes a third connection port, a fourth connection port and a fifth connection port, which are arranged side-by-side on the circuit board, and one of the third connection port, one of the fourth connection port and one of the fifth connection ports are simultaneously connected to a chip test socket.
[0009] Optionally, the number of pins in the first connection port is different from the number of pins in the second connection port, and the number of pins in the third connection port is different from the number of pins in the fifth connection port.
[0010] Optionally, the power chip and the circuit board are detachably connected.
[0011] This application also discloses a chip testing device, which includes multiple different types of chip test sockets and a chip test board as described above. The multiple different types of chip test sockets are connected to multiple connectors in the chip test board. The chip test sockets are provided with test positions for placing the chip to be tested.
[0012] Optionally, the chip test socket and the connector are detachably connected.
[0013] Optionally, the chip test socket is equipped with a main control chip, which is used to read the NAND ID of the chip under test.
[0014] This application also discloses a testing system, which includes a robotic arm and a chip testing device as described above. The robotic arm is used to simultaneously place multiple chips under test into the test positions of multiple chip test sockets.
[0015] The beneficial effects of this application are as follows: Compared with the current test devices that can only test one type of memory chip, or test devices that can only test one type of memory chip, this application integrates at least two different types of connectors, namely the first connector and the second connector, onto the circuit board to adapt to different types of chip test sockets, thereby testing different types of memory chips, realizing compatible testing of multiple memory chips, and testing a large number of chips at once with high testing efficiency. Attached Figure Description
[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:
[0017] Figure 1 This is a planar schematic diagram of a chip test board provided in an embodiment of this application;
[0018] Figure 2 This is a side view of a chip test board provided in an embodiment of this application;
[0019] Figure 3 This is a schematic block diagram of a chip test board provided in an embodiment of this application;
[0020] Figure 4 This is a planar schematic diagram of a first connector provided in an embodiment of this application;
[0021] Figure 5 This is a planar schematic diagram of a second connector provided in an embodiment of this application;
[0022] Figure 6 This is a cross-sectional schematic diagram of a chip testing device provided in an embodiment of this application.
[0023] Among them, 10 is a chip testing device; 100 is a chip testing board; 110 is a circuit board; 111 is a first layout area; 112 is a second layout area; 113 is a third layout area; 114 is a fixing hole; 120 is a gold finger; 130 is a power chip; 140 is a connector; 141 is a first connector; 142 is a second connector; 143 is a first connection port; 144 is a second connection port; 145 is a third connection port; 146 is a fourth connection port; 147 is a fifth connection port; 148 is a pin; 150 is a communication module; 200 is a chip testing socket; and 210 is a test position. Detailed Implementation
[0024] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.
[0025] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Furthermore, terms indicating orientation or positional relationships, such as "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are based on the orientation or relative positional relationships shown in the accompanying drawings and are merely for the purpose of simplifying the description of this application. They do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this application.
[0026] Because memory chips require multiple tests such as card opening, RDT, and BIT, the current method is to integrate the memory chips to be tested onto a test device, and then the test device communicates with the PC through gold fingers to perform the test on the memory chip. Moreover, the current test device and memory chip are in a one-to-one manner, with one test device corresponding to one type of memory chip.
[0027] However, due to the large variety of memory chips, different compatible testing devices must be used to test different memory chips, and the number of tests is small each time, making it impossible to achieve compatibility testing of multiple memory chips. Different testing devices need to be changed when testing different types of memory chips, which consumes a lot of time and manpower, resulting in low testing efficiency.
[0028] Based on the above problems, this application provides a chip test board 100, such as... Figure 1 and Figure 2 As shown, the chip test board 100 includes a circuit board 110, gold fingers 120, a power chip 130, and multiple connectors 140. The gold fingers 120 are disposed on one side of the circuit board 110 for communication with a PC. The power chip 130 and the connectors 140 are disposed on the surface of the circuit board 110, and the connectors 140 are electrically connected to the gold fingers 120 and the power chip 130, respectively. The connectors 140 are at least divided into a first connector 141 and a second connector 142. The first connector 141 and the second connector 142 are respectively connected to different types of chip test sockets 200 to test different types of memory chips.
[0029] In addition, such as Figure 3 As shown, the chip test board 100 also includes a communication module 150, which connects the connector 140 and the gold finger 120. The connector 140 is used to realize signal conversion, and the connector 140 and the gold finger 120 are also connected to the power chip 130.
[0030] The embodiments of this application aim to solve the problem of batch integration testing of multiple memory chips. Compared with the current testing devices that can only test one memory chip or only one type of memory chip, this application integrates at least two different types of connectors 140, namely the first connector 141 and the second connector 142, onto the circuit board 110 to adapt to different types of chip test sockets 200, thereby testing different types of memory chips, realizing compatible testing of multiple memory chips, and testing a large number of chips at one time with high testing efficiency.
[0031] As a specific example, such as Figure 1 As shown, the surface of the circuit board 110 is divided into a test area and a border area. The border area surrounds the test area, and the connectors 140 are all distributed in the test area, while the gold fingers 120 are distributed in the border area. The test area of the circuit board 110 includes a first arrangement area 111, a second arrangement area 112, and a third arrangement area 113 arranged in parallel. The second arrangement area 112 is located between the first arrangement area 111 and the third arrangement area 113. The first arrangement area 111 and the third arrangement area 113 have the same area, and both are larger than the area of the second arrangement area 112. The chip test board 100 includes a plurality of first connectors 141 and a plurality of second connectors 142. The plurality of first connectors 141 are respectively disposed in the first arrangement area 111 and the third arrangement area 113, and the plurality of second connectors 142 are disposed in the second arrangement area 112.
[0032] In this example, there are a large number of first connectors 141 on the circuit board 110. The first connectors 141 and their chip test sockets 200 are used to perform large-scale testing on commonly used test chips or memory chips with high production volume, while the second connectors 142 and their chip test sockets 200 are used to perform small-batch testing on special models or new types of memory chips, thereby meeting different needs and improving testing efficiency.
[0033] Furthermore, in this example, the first arrangement area 111 and the third arrangement area 113 have the same area, and a plurality of first connectors 141 are arranged in arrays in the first arrangement area 111 and the third arrangement area 113 respectively. The number and arrangement of the plurality of first connectors 141 in the first arrangement area 111 and the number and arrangement of the plurality of first connectors 141 in the second arrangement area 112 are the same.
[0034] The area of the second arrangement area 112 is smaller than the area of the first arrangement area 111, and a plurality of second connectors 142 are arranged in the second arrangement area 112 along the length direction of the second arrangement area 112.
[0035] The above-described arrangement design of connector 140 allows for a greater number of connectors to be distributed on circuit board 110, improving the space utilization of circuit board 110 and enhancing the aesthetics of chip test board 100.
[0036] like Figure 4 As shown, in this example, the first connector 141 includes a first connection port 143 and a second connection port 144. The first connection port 143 and the second connection port 144 are arranged side by side on the circuit board 110. One of the first connection ports 143 and the second connection port 144 are simultaneously connected to a chip test socket 200.
[0037] like Figure 5 As shown, the second connector 142 includes a third connection port 145, a fourth connection port 146, and a fifth connection port 147. The third connection port 145, the fourth connection port 146, and the fifth connection port 147 are arranged side by side on the circuit board 110. One of the third connection ports 145, one of the fourth connection ports 146, and one of the fifth connection ports 147 are simultaneously connected to a chip test socket 200.
[0038] The connectors 140 located in the first row area 111 and the third row area 113 are only compatible with chip test sockets 200 with two connection ports, and the connectors 140 located in the third row area 113 are only compatible with chip test sockets 200 with three connection ports. This enables the chip test board 100 to be paired with two different types of chip test sockets 200 to test two different types of memory chips.
[0039] Furthermore, in this example, the installation of the chip test socket 200 is designed to prevent mistakes. Specifically, the connection port has multiple pins 148, and the interface of the chip test socket 200 also has multiple connection pins. The connection pins in the chip test socket 200 correspond one-to-one with the pins 148 in the connection port. Among them, the number of pins 148 in the first connection port 143 is different from the number of pins 148 in the second connection port 144, and the number of pins 148 in the third connection port 145 is different from the number of pins 148 in the fifth connection port 147.
[0040] Specifically, the first connection port 143 has 12 pins 148, the second connection port 144 has 13 pins 148, the third connection port 145 has 12 pins 148, the fourth connection port 146 has 13 pins 148, and the fifth connection port 147 has 13 pins 148.
[0041] With the above design, when installing the chip test socket 200, the chip test socket 200 can only be installed into the corresponding connector 140 in the forward direction. If the chip test socket 200 is reversed, it cannot be installed. This achieves foolproof installation of the chip test socket 200 and improves the installation efficiency of the chip test socket 200.
[0042] It should be noted that the circuit board 110 in this embodiment includes two or four different sections, each section corresponding to a different type of connector 140; or, the circuit board 110 may not be divided into sections, and different types of connectors 140 may be dispersed and mixed on the circuit board 110.
[0043] It should be noted that the connector 140 in this embodiment can also be paired with different types of chip test sockets 200 to test different types of memory chips, as long as these chip test sockets 200 have the same interface and can be adapted to the connector 140.
[0044] It should be noted that the chip test board 100 in this embodiment, combined with the corresponding chip test socket 200, can simultaneously test three different types of memory chips, four different types of memory chips, or more types of memory chips, depending on the actual situation.
[0045] In this embodiment, the circuit board 110 also has multiple fixing holes 114. Some of the fixing holes 114 are distributed around the edge of the circuit board 110. During the process of installing the chip test socket 200 onto the chip test board 100, and during the testing of the memory chip, the chip test board 100 can be fixed in place by inserting pins on the machine into the fixing holes 114 to prevent the chip test board 100 from shifting. The other part of the fixing holes 114 are distributed near the multiple connectors 140, making the connectors 140 more stable when subjected to force.
[0046] In this embodiment, the power chip 130 and the circuit board 110 are detachably connected. The power chip 130 can be removed and replaced as needed to provide different currents to meet different usage requirements.
[0047] like Figure 6 As shown, this application embodiment also provides a chip testing device 10, which includes a plurality of different types of chip test sockets 200 and a chip test board 100 as described above. The plurality of different types of chip test sockets 200 are correspondingly connected to a plurality of connectors 140 in the chip test board 100. The chip test sockets 200 are provided with test positions 210, which are used to place the chip to be tested.
[0048] In this embodiment, the chip test socket 200 and the connector 140 are detachably connected. The number of chip test sockets 200 to be installed into the chip test board 100 and the distribution position of the chip test sockets 200 on the chip test board 100 can be selected according to the actual situation to meet the usage requirements of various different scenarios.
[0049] The chip testing device 10 in this embodiment can perform card opening tests, RDT tests, and other tests on the memory chip. During the card opening test, the chip test socket 200 is equipped with a main control chip, which is used to read the NAND ID of the chip under test. After the memory chip is placed in the test position 210, when a test command is received from the PC, the main control chip reads the NAND ID of the memory chip. After reading the NAND ID, the card opening tool compares the read NAND ID with all NAND IDs in its built-in database to deduce information such as the memory chip's serial number, capacity, number of channels, and flash memory type (SLC / MLC / TLC / QLC), which are then set by the user.
[0050] During RDT testing, no main control chip is required in the chip test socket 200. The chip test device 10 only needs to be powered. During the test, the gold fingers 120 of the chip test device 10 communicate with the PC to transmit the test results of the entire chip test device 10 to the PC for display. When different memory chips need to be tested, only the chip test socket 200 compatible with the memory chip needs to be replaced. There is no need to replace the entire chip test device 10. This allows one test device to be compatible with testing multiple memory chips at the same time, thereby saving time and manpower costs.
[0051] This application also discloses a testing system, which includes a robotic arm and a chip testing device 10 as described above. The robotic arm is used to simultaneously place multiple chips under test into the test positions 210 of multiple chip test sockets 200 or to replace the memory chips under test, making the batch testing process more convenient and greatly improving efficiency.
[0052] This application provides a testing device compatible with various memory chips, enabling automated batch testing of various memory chips, including automated detection and the use of automated control technologies. Testing includes card opening, RDT (Real-Time Testing), and other tests. Memory chips include, but are not limited to, controllers, power chips, and M.2 NVMe SLC, MLC, TLC, and QLC chips. The testing device is not limited to manual or semi-automatic operation, thus meeting the needs of most chip testing and chip production.
[0053] Furthermore, the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.
[0054] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.
Claims
1. A chip test board, characterized in that, The device includes a circuit board, gold fingers, a power chip, and multiple connectors. The gold fingers are disposed on one side of the circuit board, and the power chip and the connectors are disposed on the surface of the circuit board. The connectors are electrically connected to the gold fingers and the power chip, respectively. The connector is at least divided into a first connector and a second connector, which are respectively connected to different types of chip test sockets.
2. The chip test board as described in claim 1, characterized in that, The circuit board includes a first arrangement area, a second arrangement area, and a third arrangement area, wherein the second arrangement area is located between the first arrangement area and the third arrangement area; The chip test board includes multiple first connectors and multiple second connectors, with the multiple first connectors arranged in the first arrangement area and the third arrangement area, and the multiple second connectors arranged in the second arrangement area.
3. The chip test board as described in claim 2, characterized in that, The first arrangement area and the third arrangement area have the same area, and multiple first connectors are arranged in arrays in the first arrangement area and the third arrangement area respectively; the area of the second arrangement area is smaller than the area of the first arrangement area, and multiple second connectors are arranged in the second arrangement area along the length direction of the second arrangement area.
4. The chip test board as described in any one of claims 1-3, characterized in that, The first connector includes a first connection port and a second connection port, which are arranged side by side on the circuit board. One of the first connection ports and one of the second connection ports are simultaneously connected to a chip test socket. The second connector includes a third connection port, a fourth connection port, and a fifth connection port, which are arranged side by side on the circuit board. One of the third connection ports, one of the fourth connection ports, and one of the fifth connection ports are simultaneously connected to a chip test socket.
5. The chip test board as described in claim 4, characterized in that, The number of pins in the first connection port is different from the number of pins in the second connection port, and the number of pins in the third connection port is different from the number of pins in the fifth connection port.
6. The chip test board as described in claim 1, characterized in that, The power chip and the circuit board are detachably connected.
7. A chip testing device, characterized in that, It includes multiple different types of chip test sockets and a chip test board as described in any one of claims 1-6, wherein the multiple different types of chip test sockets are connected to multiple connectors in the chip test board, and the chip test sockets are provided with test positions for placing the chip under test.
8. The chip testing apparatus as described in claim 7, characterized in that, The chip test socket and the connector are detachably connected.
9. The chip testing apparatus as described in claim 7, characterized in that, The chip test socket is equipped with a main control chip, which is used to read the NAND ID of the chip under test.
10. A testing system comprising a robotic arm and a chip testing apparatus as described in any one of claims 7-9, wherein the robotic arm is used to simultaneously place multiple chips to be tested into test positions of multiple chip test sockets.