High-frequency multilayer chip ceramic capacitor
By creating a cavity inside a multilayer ceramic capacitor and filling it with a gaseous dielectric, an edge-effect capacitor is formed, which solves the problem of unstable high-frequency performance of traditional ceramic capacitors and achieves stable high-frequency performance and improved capacitance.
Patent Information
- Application Number
- CN202422810384.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-11-18
AI Technical Summary
Traditional multilayer ceramic capacitors suffer from high-frequency performance suppression, making it difficult to achieve stable high-frequency performance.
Cavities are created inside a multilayer conductive structure and filled with a gas dielectric to form edge-effect capacitors to enhance high-frequency performance.
This invention achieves stable high-frequency performance of multilayer ceramic chip capacitors, prevents short circuits, and improves the high-frequency capacitance of capacitors.
Smart Images
Figure CN223552405U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of multilayer ceramic chip capacitor technology, and in particular to a high-frequency multilayer ceramic chip capacitor. Background Technology
[0002] Many wireless communication systems, including satellite, GPS, mobile phone applications, and high-speed processor applications, require capacitor technology to regulate high-frequency operations. Long-distance communication, especially fiber optic applications, demands wide bandwidth with optimal high-frequency performance. Ceramic dielectric materials, with dielectric constants ranging from 10 to 4000, can provide capacitance values in the microfarad range.
[0003] Traditional multilayer ceramic capacitors are constructed by stacking ceramic films, using typical organic adhesives and solvents to bond thin sheets of ceramic powder dielectric material together. These sheets are typically (but not always) 5 inches x 5 inches, with approximately 30 to 1000 layers. Before stacking, conductive electrodes are printed onto the surface of the ceramic layers, forming internal conductive plates to generate the desired capacitance. The stacked structure is then compressed and divided into individual devices. Based on the desired time-temperature profile, the compressed individual green devices are heated in a furnace under a specific atmosphere to separate the organic binder and sinter or fuse the powdered ceramic material into a monolithic structure. Each device is then immersed in a conductive material (usually silver or copper paste) to form the conductive end, and finally, a solder layer is plated at the end for soldering to a surface mount board or bonding leads to the circuit for application. However, it has been confirmed that the ceramic dielectric material actually inhibits the optimal high-frequency performance of the capacitor product; therefore, it is essential to develop a capacitor product that can achieve more stable high-frequency performance. Utility Model Content
[0004] The purpose of this invention is to provide a high-frequency multilayer ceramic chip capacitor. By artificially creating a cavity inside the capacitor and filling the cavity with a gaseous dielectric, an edge effect capacitor can be formed in the multilayer conductive structure, enabling the multilayer ceramic chip capacitor to generate additional high-frequency capacitance, thereby obtaining more stable high-frequency performance.
[0005] To achieve the above objectives, one aspect of the technical solution adopted by this utility model is as follows:
[0006] A high-frequency multilayer ceramic chip capacitor includes a first external electrode, a second external electrode, and a multilayer conductive structure formed by alternating stacking of a first internal electrode layer, a ceramic material layer, and a second internal electrode layer; the first external electrode and the second external electrode are arranged side by side, the first external electrode is connected to the first internal electrode, and the second external electrode is connected to the second internal electrode; the multilayer conductive structure has at least one cavity inside, and the cavity is filled with a gaseous dielectric.
[0007] The cavity is formed in the ceramic material layer, and the upper cavity wall is the first inner electrode layer or the second inner electrode layer. Correspondingly, the lower cavity wall is the second inner electrode layer or the first inner electrode layer.
[0008] As a preferred embodiment of the above-mentioned high-frequency multilayer ceramic chip capacitor, when the cavity is formed in the ceramic material layer, the number of cavities is one, and the cavity is located near the upper side of the ceramic material layer or near the lower side of the ceramic material layer.
[0009] As a preferred embodiment of the above-mentioned high-frequency multilayer ceramic chip capacitor, when the cavity is formed in the ceramic material layer, the number of cavities is two, and the two cavities are respectively disposed near the upper side of the ceramic material layer and near the lower side of the ceramic material layer.
[0010] As a preferred embodiment of the above-mentioned high-frequency multilayer ceramic chip capacitor, the gaseous dielectric is air, nitrogen, or argon.
[0011] To achieve the above objectives, another aspect of the present invention adopts the following technical solution:
[0012] A high-frequency multilayer ceramic chip capacitor includes a first external electrode, a second external electrode, and a multilayer conductive structure formed by alternating stacking of a first internal electrode layer, a ceramic material layer, and a second internal electrode layer; the first external electrode and the second external electrode are arranged side by side, the first external electrode is connected to the first internal electrode, and the second external electrode is connected to the second internal electrode; the multilayer conductive structure has at least one cavity inside, and the cavity is filled with a gaseous dielectric.
[0013] The cavity is formed between two adjacent ceramic material layers, and the first inner electrode layer or the second inner electrode layer is provided with a hollow hole that communicates with the cavity.
[0014] As a preferred embodiment of the above-mentioned high-frequency multilayer ceramic chip capacitor, when the cavity is formed in the ceramic material layer, the number of cavities is one, and the cavity is located near the upper side of the ceramic material layer or near the lower side of the ceramic material layer.
[0015] As a preferred embodiment of the above-mentioned high-frequency multilayer ceramic chip capacitor, when the cavity is formed in the ceramic material layer, the number of cavities is two, and the two cavities are respectively disposed near the upper side of the ceramic material layer and near the lower side of the ceramic material layer.
[0016] As a preferred embodiment of the above-mentioned high-frequency multilayer ceramic chip capacitor, the gaseous dielectric is air, nitrogen, or argon.
[0017] The advantages of implementing the high-frequency multilayer chip ceramic capacitor provided by this utility model compared with the prior art are as follows:
[0018] This invention provides at least one cavity within a multilayer conductive structure, the cavity being formed within the ceramic material layers. The upper wall of the cavity is either the first inner electrode layer or the second inner electrode layer, and correspondingly, the lower wall of the cavity is either the second inner electrode layer or the first inner electrode layer. Alternatively, the cavity is formed between two adjacent ceramic material layers, with a perforated hole communicating with the cavity on the first or second inner electrode layer. The cavity is filled with a gaseous dielectric, enabling the formation of edge-effect capacitance within the multilayer conductive structure. This results in a more stable high-frequency performance for the multilayer chip ceramic capacitor. Attached Figure Description
[0019] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings of the embodiments will be briefly described below.
[0020] Figure 1 This is one of the structural schematic diagrams of a high-frequency multilayer chip ceramic capacitor provided in Embodiment 1 of this utility model;
[0021] Figure 2 This is the second schematic diagram of the structure of a high-frequency multilayer chip ceramic capacitor provided in Embodiment 1 of this utility model;
[0022] Figure 3 This is one of the structural schematic diagrams of a high-frequency multilayer chip ceramic capacitor provided in Embodiment 2 of this utility model;
[0023] Figure 4 This is the second schematic diagram of the structure of a high-frequency multilayer chip ceramic capacitor provided in Embodiment 2 of this utility model.
[0024] Marked in the image:
[0025] 1. First external electrode; 2. Second external electrode; 3. Multilayer conductive structure; 31. First internal electrode layer; 32. Ceramic material layer; 33. Second internal electrode layer; 4. Cavity. Detailed Implementation
[0026] The specific embodiments of this utility model will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this utility model, but are not intended to limit its scope.
[0027] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," "top," and "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this utility model and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. It should also be understood that the terms "first," "second," etc., are used in this utility model to describe various information, but this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this utility model, "first" information can also be referred to as "second" information, and similarly, "second" information can also be referred to as "first" information.
[0028] Example 1
[0029] Please see Figures 1 to 2 This embodiment provides a high-frequency multilayer ceramic chip capacitor, which includes a first external electrode 1, a second external electrode 2, and a multilayer conductive structure 3 formed by alternating stacking of a first internal electrode layer 31, a ceramic material layer 32, and a second internal electrode layer 33. The first external electrode 1 and the second external electrode 2 are arranged side-by-side, with the first external electrode 1 connected to the first internal electrode and the second external electrode 2 connected to the second internal electrode. The multilayer conductive structure 3 has at least one cavity 4 inside, which is filled with a gaseous dielectric. The gaseous dielectric can be air, nitrogen, or argon.
[0030] The cavity 4 is formed in the ceramic material layer 32. The upper cavity wall of the cavity 4 is the first inner electrode layer 31 or the second inner electrode layer 33. Correspondingly, the lower cavity wall of the cavity 4 is the second inner electrode layer 33 or the first inner electrode layer 31.
[0031] According to the high-frequency multilayer ceramic chip capacitor of Embodiment 1 of this utility model, since the cavity 4 is filled with a gaseous dielectric, and the upper cavity wall of the cavity 4 is the first inner electrode layer 31 or the second inner electrode layer 33, and correspondingly, the lower cavity wall of the cavity 4 is the second inner electrode layer 33 or the first inner electrode layer 31, after energization, since the charges of the first inner electrode layer 31 and the second inner electrode layer 33 are opposite, and at the same time, the cavity 4 has a certain depth, which can prevent the current from moving between the first inner electrode layer 31 and the second inner electrode layer 33, an electric field can be generated in the cavity 4, and an edge effect capacitor can be formed in the multilayer conductive structure 3. Thus, the multilayer ceramic chip capacitor obtains a relatively stable high-frequency performance.
[0032] For example, such as Figure 1 As shown, the number of cavities 4 is preferably one, and the cavity 4 is disposed near the upper side or near the lower side of the ceramic material layer 32. In the multilayer conductor structure 3, the portion corresponding to the cavity 4 is the high-frequency, low-capacitance portion, while the remaining portions are the low-frequency, high-capacitance portions. Furthermore, since the thickness of the ceramic material layer 32 containing the cavity 4 is greater than the thickness of the other ceramic material layers, short circuits in the multilayer chip ceramic capacitor can be prevented.
[0033] For example, such as Figure 2 As shown, the number of cavities 4 is preferably two, with the two cavities 4 respectively located near the upper ceramic material layer 32 and near the lower ceramic material layer 32. As described above, the portion corresponding to the cavity 4 in the multilayer conductor structure 3 is the high-frequency, low-capacitance portion, while the remaining portion is the low-frequency, high-capacitance portion. Therefore, Figure 2 The corresponding structure, from top to bottom, consists of a high-frequency low-capacitance section, a low-frequency high-capacitance section, and a high-frequency low-capacitance section.
[0034] Example 2
[0035] Please see Figures 3 to 4 This embodiment provides a high-frequency multilayer ceramic chip capacitor. Compared with the first embodiment, the only difference is that the cavity 4 is formed between two adjacent ceramic material layers 32, and the first inner electrode layer 31 or the second inner electrode layer 33 is provided with a hollow hole that communicates with the cavity 4.
[0036] According to the high-frequency multilayer ceramic chip capacitor of Embodiment 2 of this utility model, since the cavity 4 is filled with a gaseous dielectric, and the first inner electrode layer 31 or the second inner electrode layer 33 is provided with a hollow hole communicating with the cavity 4, the inner electrode layer corresponding to the ceramic material layer located on the upper or lower side of the cavity is either the second inner electrode layer 33 or the first inner electrode layer 31. Therefore, after energizing, since the charges of the first inner electrode layer 31 and the second inner electrode layer 33 are opposite, and the cavity 4 has a certain depth, it can prevent the current from moving between the first inner electrode layer 31 and the second inner electrode layer 33. Thus, an electric field can be generated in the cavity 4, and an edge effect capacitor can be formed in the multilayer conductive structure 3. As a result, the multilayer ceramic chip capacitor obtains a relatively stable high-frequency performance.
[0037] For example, such as Figure 3 As shown, the number of cavities is preferably one, and the cavity is located near the upper ceramic material layer or near the lower ceramic material layer. The number of cavities 4 is preferably one, and the cavity 4 is located near the upper ceramic material layer 32 or near the lower ceramic material layer 32. In the multilayer conductor structure 3, the portion corresponding to cavity 4 is the high-frequency, low-capacitance portion, and the remaining portions are the low-frequency, high-capacitance portions. Furthermore, since the thickness of the ceramic material layer 32 where cavity 4 is located is greater than the thickness of the other ceramic material layers, short circuits in the multilayer chip ceramic capacitor can be prevented.
[0038] For example, such as Figure 4 As shown, the number of cavities 4 is preferably two, with the two cavities 4 respectively located near the upper ceramic material layer 32 and near the lower ceramic material layer 32. As described above, the portion corresponding to the cavity 4 in the multilayer conductor structure 3 is the high-frequency, low-capacitance portion, while the remaining portion is the low-frequency, high-capacitance portion. Therefore, Figure 4 The corresponding structure, from top to bottom, consists of a high-frequency low-capacitance section, a low-frequency high-capacitance section, and a high-frequency low-capacitance section.
[0039] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0040] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present utility model, and these improvements and substitutions should also be considered within the protection scope of the present utility model.
Claims
1. A high-frequency multilayer ceramic chip capacitor, characterized in that, The structure includes a first external electrode, a second external electrode, and a multilayer conductive structure formed by alternating stacking of a first internal electrode layer, a ceramic material layer, and a second internal electrode layer. The first external electrode and the second external electrode are arranged side by side, with the first external electrode connected to the first internal electrode and the second external electrode connected to the second internal electrode. The multilayer conductive structure has at least one cavity inside, which is filled with a gaseous dielectric. The cavity is formed in the ceramic material layer, and the upper cavity wall is the first inner electrode layer or the second inner electrode layer. Correspondingly, the lower cavity wall is the second inner electrode layer or the first inner electrode layer.
2. The high-frequency multilayer ceramic chip capacitor according to claim 1, characterized in that, The cavity is one in number, and the cavity is located near the upper ceramic material layer or near the lower ceramic material layer.
3. The high-frequency multilayer ceramic chip capacitor according to claim 1, characterized in that, The number of cavities is two, and the two cavities are respectively located near the upper ceramic material layer and near the lower ceramic material layer.
4. The high-frequency multilayer ceramic chip capacitor according to claim 1, characterized in that, The gaseous dielectric medium is air, nitrogen, or argon.
5. A high-frequency multilayer ceramic chip capacitor, characterized in that, The structure includes a first external electrode, a second external electrode, and a multilayer conductive structure formed by alternating stacking of a first internal electrode layer, a ceramic material layer, and a second internal electrode layer. The first external electrode and the second external electrode are arranged side by side, with the first external electrode connected to the first internal electrode and the second external electrode connected to the second internal electrode. The multilayer conductive structure has at least one cavity inside, which is filled with a gaseous dielectric. The cavity is formed between two adjacent ceramic material layers, and the first inner electrode layer or the second inner electrode layer is provided with a hollow hole that communicates with the cavity.
6. The high-frequency multilayer ceramic chip capacitor according to claim 5, characterized in that, The cavity is one in number, and the cavity is located near the upper ceramic material layer or near the lower ceramic material layer.
7. The high-frequency multilayer ceramic chip capacitor according to claim 5, characterized in that, The number of cavities is two, and the two cavities are respectively located near the upper ceramic material layer and near the lower ceramic material layer.
8. The high-frequency multilayer ceramic chip capacitor according to claim 5, characterized in that, The gaseous dielectric medium is air, nitrogen, or argon.