Structure for preparing wafer-level system packaging chip by utilizing Hybrid Bonding and FOWLP technologies

Abstract

A wafer-level system packaging chip structure is prepared by utilizing Hybrid Bonding and FOWLP technologies, and the wafer-level system packaging chip structure comprises a wafer-level CIS chip, a silicon-based bearing sheet and a wafer-level CID chip; the front surface of the wafer-level CIS chip is provided with an adhesive film layer and a glass layer; carrying out thinning processing on the back surface of the wafer-level CIS chip and forming a non-bonding layer; a conductive through hole structure is arranged on the back surface of the wafer-level CIS chip; arranging a conductive structure on the back surface of the wafer-level CIS chip; arranging a conductive through hole structure on the silicon-based bearing sheet; arranging a conductive structure on the silicon-based bearing sheet; bonding the wafer-level CID chip and the silicon-based bearing sheet together, thinning the wafer-level CID chip and the silicon-based bearing sheet to form a groove structure, and pasting a second type of chip in the groove structure; a first insulating layer is arranged on the bonded wafer, and a first metal rewiring layer is arranged on the first insulating layer; arranging a second insulating layer on the bonded wafer, and arranging a second metal rewiring layer; planting balls on the second metal rewiring layer; and cutting to obtain a single Die. According to the packaging structure, the packaging efficiency can be greatly improved, and the processing cost is remarkably reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor chip packaging technology, and in particular to a structure for fabricating wafer-level system-on-a-chip using Hybrid Bonding and FOWLP technologies. Background Technology

[0002] Hybrid bonding technology refers to bonding two wafers (or chips) together not only through copper bumps recessed at room temperature, but also by attaching other non-conductive parts of the two wafers (or chips) facing each other. After the hybrid bonding process, there are no gaps between the wafers (or chips) and no need to fill them with epoxy resin. A flowchart of the hybrid bonding process is shown below. Figure 1 As shown.

[0003] Currently, advanced packaging technologies mainly refer to flip chip (FC), wafer-level package (WLP), 2.5D packaging (interposer), and 3D packaging through silicon via (TSV) technology. In terms of advanced packaging technology platforms, FC technology is the most widely used, accounting for approximately 75% of the market share, followed by fan-in wafer-level package (FIWLP) and fan-out wafer-level package (FOWLP). Looking at future growth rates, consulting firm Yole Intelligence predicts that FOWLP will experience rapid growth from 2018 to 2024 due to its vast future market potential, maintaining a compound annual growth rate of 26%. This technology will primarily be used in the mobile internet, networking, and automotive sectors.

[0004] FOWLP is a novel packaging technology that integrates multiple chips onto a single wafer, achieving high integration. It utilizes external I / O routing outside the chip's surface area, increasing the number of I / O contacts. Furthermore, the use of a metal redistribution layer further expands the usable routing area, maximizing the chip's effective surface area and creating a fan-shaped structure. This packaging technology connects the signal and power lines of multiple chips together, reducing inter-chip wiring, lowering power consumption, and reducing signal transmission delay. After solder ball bonding, FOWLP allows direct soldering onto a printed circuit board without a carrier board, shortening signal transmission distances and improving electrical performance. This technology significantly enhances chip integration and performance, reduces cost and power consumption, and minimizes package size and weight, thus simplifying manufacturing. FOWLP has a wide range of applications, including processors, memory, and sensors. Moreover, fan-out wafer-level packaging can be applied in various fields, including communications, computers, medical devices, and automotive. Compared to other advanced packaging technologies, FOWLP technology's advantage lies in its ability to utilize high-density wiring manufacturing processes to create chip package structures with lower power loss and enhanced functionality, offering a more significant advantage for system-level packaging technologies. The first generation of FOWLP technology was the Embedded Wafer Level Ball Grid Array (eWLB) technology developed by Infineon in Germany. Subsequently, TSMC's Integrated Fan-Out Package (InFO) technology and Freescale's Redistributed Chip Package (RCP) technology emerged. Due to its relatively low cost and powerful functionality, it has gradually been accepted by the market. For example, Apple has already adopted fan-out packaging in the mass production of its A12 processor. Furthermore, it is not only developing rapidly in the wireless field but is now also penetrating automotive and medical applications. It is believed that most devices in our lives will adopt fan-out wafer-level packaging technology in the future. As one of the next-generation packaging technologies, FOWLP has seen strong growth in recent years, primarily driven by TSMC's provision of InFO to the Apple ecosystem. Fan-out wafer-level packaging is currently experiencing rapid growth. According to a recent report by Yole Intelligence, the FOWLP market is undergoing strong growth, with an overall CAGR of 15.1% between 2020 and 2026, reaching a market size of $3.425 billion by the end of 2026.Of these, the mobile and consumer sector accounted for $1.613 billion, the telecommunications and infrastructure sector accounted for $1.597 billion, and the automotive and mobility sector accounted for $216 million.

[0005] An image sensor chip (CMOS Image Sensor, CIS) is an image sensor based on semiconductor CMOS technology, which began to be widely used commercially in the late 1990s. Currently, CIS chips are widely used in mobile phones, cameras, automotive electronics, security, and many other fields.

[0006] As mobile consumer electronics products such as smartphones, computers, and digital cameras place increasingly higher demands on the packaging of high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system-in-package (SIP) products, high-density, multi-type chip system-in-package (SiP) products are gradually becoming mainstream in next-generation electronic products. Therefore, combining CIS chips with FOWLP technology to form SIP products has always been a hot research topic in the field of chip packaging. Utility Model Content

[0007] To address the aforementioned technical problems, the purpose of this invention is to provide a structure for fabricating wafer-level system-on-a-chip (SoC) packages using Hybrid Bonding and FOWLP technologies. This packaging structure enables the integration of CIS chips with other types of chips and completes the packaging structure using FOWLP technology. While achieving the integration of different types of chips, it significantly improves packaging efficiency and substantially reduces processing costs.

[0008] A wafer-level system-on-a-chip (SoC) structure fabricated using Hybrid Bonding and FOWLP technologies includes a wafer-level CIS chip, a silicon-based carrier wafer, and a wafer-level CID chip; the wafer-level CIS chip has an adhesive film layer and a glass layer on its front side;

[0009] Thinning is performed on the back side of the wafer-level CIS chip to form a non-bonded layer; conductive via structures are formed on the back side of the wafer-level CIS chip; conductive structures are formed on the back side of the wafer-level CIS chip; a non-bonded layer is formed on a silicon-based carrier; conductive via structures are formed on a silicon-based carrier; conductive structures are formed on a silicon-based carrier; the wafer-level CID chip and the silicon-based carrier are bonded together; after bonding, the back side of the silicon-based carrier is thinned to form a groove structure; a second type of chip is attached within the groove structure of the bonding wafer; a first insulating layer is formed on the bonded wafer; a first metal redistribution layer is formed on the bonded wafer; a second insulating layer is formed on the bonded wafer; a second metal redistribution layer is formed on the bonded wafer; balls are implanted on the second metal redistribution layer of the bonded wafer; and a single die is obtained by dicing.

[0010] Furthermore, the wafer-level CIS chip includes a CIS chip (10), a photosensitive area disposed on the upper surface of the CIS chip (10), and a CIS chip conductive structure (12).

[0011] Furthermore, a bonding film layer (13) with high light transmittance and a glass layer (14) with high light transmittance are sequentially disposed on the upper surface of the wafer-level CIS chip.

[0012] Furthermore, the back side of the wafer-level CIS chip is thinned and a first non-conductive layer (15) is formed. A first conductive structure via (205) is formed at a position corresponding to the conductive structure of the wafer-level CIS chip. The first conductive structure via (205) penetrates the first non-conductive layer (15) and the CIS chip (10). A first conductive structure (16) is formed at the first conductive structure via (205).

[0013] Furthermore, a second non-conductive layer (102) is disposed on the silicon-based carrier sheet (101), a through hole (310) is formed on the silicon-based carrier sheet (101) with the second non-conductive layer (102), and a second conductive structure (103) is formed on the through hole (310).

[0014] Furthermore, the wafer-level CIS chip composed of the first conductive structure (16) and the silicon-based carrier sheet (101) composed of the second conductive structure (103) are bonded together using Hybrid Bonding technology. The two wafers are bonded together to form a non-conductive layer (104) and a third conductive structure (105). A groove structure (303) is provided on the wafer-level structure after the above bonding.

[0015] Furthermore, the groove structure is provided with a second type of chip (107) that has been thinned and cut using an adhesive film (106). The second type of chip (107) is provided with a second type of chip conductive structure (108). A gap structure (304) is formed between the second type of chip (107) and the groove structure 303. A first insulating layer (109) is provided on the wafer-level structure of the second type of chip conductive structure (108) and a second conductive via structure (306) is formed. A first metal redistribution layer (110) is formed on the wafer-level structure of the second conductive via structure (306).

[0016] Furthermore, a second insulating layer (111) and a third conductive via structure (308) are disposed on the wafer-level structure of the first metal redistribution layer (110).

[0017] Furthermore, a second metal redistribution layer (112) is formed on the wafer-level structure of the third conductive via structure (308); solder balls (113) are implanted on the wafer-level structure of the second metal redistribution layer (112); and the wafer with the implanted solder balls (113) is cut to obtain a single die.

[0018] The main advantages of this utility model are as follows: (1) Hybrid Bonding technology is used for bonding, which can achieve higher density contact connection (more than one million contacts can be made in a 1×1cm chip) and smaller contact spacing connection (the spacing can be miniaturized to less than 1 micrometer). (2) The CIS chip is integrated with other types of chips to realize the preparation of high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system integrated electronic products. (3) The integrated combined chip is packaged using FOWLP technology to complete the entire packaging process, thereby improving packaging efficiency and reducing packaging costs. Attached Figure Description

[0019] Figure 1 The following is a flowchart of the hybrid bonding process: (a) Unbonded surface of the test piece, (b) Dielectric material bonding steps, (c) Copper junction bonding process at increased temperature, and (d) Stress distribution inside the junction at high temperature.

[0020] Figure 2 This is a schematic diagram of the structure of a wafer-level image sensor (CIS) chip.

[0021] Figure 3 for Figure 2 The diagram shows a structure in which a high-transmittance adhesive film layer and a glass layer are sequentially formed on the upper surface of a wafer-level CIS chip.

[0022] Figure 4 To Figure 3 A schematic diagram of the structure in which the back side of a wafer-level CIS chip is thinned to form a non-conductive layer in the Hybrid Bonding technology.

[0023] Figure 5 In order to be in Figure 4 The diagram shows a structure in which conductive vias are formed at positions corresponding to the conductive structures of a wafer-level CIS chip.

[0024] Figure 6 In order to be in Figure 5 A conductive structure is formed at the conductive via structure shown.

[0025] Figure 7 This involves forming a non-conductive layer on a silicon-based substrate using the Hybrid Bonding technique.

[0026] Figure 8 In order to be in Figure 7 A through-hole structure is formed on the silicon-based carrier wafer with a non-conductive layer, as shown.

[0027] Figure 9 For example Figure 8 A conductive structure is formed on the structure shown.

[0028] Figure 10 This is a schematic diagram of bonding the wafer-level CIS chip obtained in step (5) to the silicon-based carrier obtained in step (8) using Hybrid Bonding technology.

[0029] Figure 11 In order to be in Figure 10 A groove structure is formed on the wafer-level structure shown.

[0030] Figure 12 To place the thinned and cut second-type chip onto a film such as... Figure 11 A schematic diagram of the groove structure shown.

[0031] Figure 13 For example Figure 12 The first insulating layer is formed on the wafer-level structure shown, and a conductive via structure is formed thereon.

[0032] Figure 14 For example Figure 13 The first metal redistribution layer is formed on the wafer-level structure shown.

[0033] Figure 15 For example Figure 14 A second insulating layer and a conductive via structure are formed on the wafer-level structure shown.

[0034] Figure 16 For example Figure 15 The second metal redistribution layer on the wafer-level structure shown.

[0035] Figure 17 For example Figure 16 The diagram shows a schematic of the ball-mounting process completed on the wafer-level structure.

[0036] Figure 18 This diagram illustrates how CIS chips are combined with other types of chips using Hybrid Bonding technology and packaged using FOWLP technology. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0038] (1) For example Figure 2 The wafer-level image sensor (CIS) chip surface shown is cleaned. 10 represents the chip, 11 represents the photosensitive area of ​​the CIS chip, and 12 represents the conductive structure of the CIS chip (i.e., Al Pad). 201 represents the upper surface of the CIS chip, and 202 represents the lower surface of the CIS chip.

[0039] (2) In Figure 2The wafer-level CIS chip shown is sequentially formed with an adhesive film layer and a glass layer, both possessing high light transmittance, resulting in the following: Figure 3 The structure is shown. 13 is an adhesive film layer with high light transmittance, 14 is a glass layer with high light transmittance, and 203 is the surface of the glass layer.

[0040] (3) Figure 3 The back side of the wafer-level CIS chip shown is thinned and a non-conductive layer, as described in the Hybrid Bonding technique, is formed to obtain... Figure 4 The structure is shown. 15 is the first non-conductive layer, which in this embodiment is made of SiO2. 204 is the upper surface of the first non-conductive layer 15.

[0041] (4) In Figure 4 Conductive vias are formed at positions corresponding to the conductive structures of the wafer-level CIS chip in the structure shown, resulting in... Figure 5 The structure shown has a conductive via penetrating the first non-conductive layer 15 and the CIS chip 10. 205 is the first conductive via.

[0042] (5) In Figure 5 A conductive structure is formed at the conductive via structure shown, resulting in the following: Figure 6 The structure shown is shown. 16 is the first conductive structure.

[0043] (6) In such Figure 7 A non-conductive layer, as shown in the Hybrid Bonding technique, is formed on the silicon-based substrate to obtain the following: Figure 7 The structure is shown. 101 is a silicon-based carrier sheet, and 102 is a second non-conductive layer; in this embodiment, this layer is made of SiO2. 301 is the lower surface of the silicon-based carrier sheet, and 302 is the upper surface of the non-conductive layer.

[0044] (7) In Figure 7 A via structure is formed on the silicon substrate carrier with a non-conductive layer, as shown, to obtain... Figure 8 The structure shown is shown. 310 is a through hole.

[0045] (8) In such Figure 8 A conductive structure is formed on the structure shown, resulting in the following: Figure 9 The structure shown is shown. 103 is the second conductive structure.

[0046] (9) The wafer-level CIS chip obtained in step (5) is bonded to the silicon-based carrier obtained in step (8) using Hybrid Bonding technology to obtain the following: Figure 10 The structure is shown. 104 is a non-conductive layer formed by bonding two wafers, and 105 is a third conductive structure formed by bonding two wafers.

[0047] (10) In Figure 10 A groove structure is formed on the wafer-level structure shown, resulting in... Figure 11 The structure shown is shown. 303 is a groove structure.

[0048] (11) Place the thinned and cut second-type chip on a film such as... Figure 11 Within the groove structure shown, the following is obtained: Figure 12 The structure is shown. 106 is the adhesive film, 107 is the second type of chip, 108 is the conductive structure of the second type of chip (i.e., AlPad), and 304 is the gap structure newly formed after the second type of chip is placed in the groove structure 303.

[0049] (12) In such Figure 12 The first insulating layer is formed on the wafer-level structure shown, and a conductive via structure is formed thereon, resulting in the following: Figure 13 The structure shown is as follows. 109 is the first insulating layer, 305 is the upper surface of the first insulating layer, and 306 is the second conductive via structure formed on the first insulating layer.

[0050] (13) In such Figure 13 The first metal redistribution layer is formed on the wafer-level structure shown, resulting in the following: Figure 14 The structure shown is shown. 110 is the first metal redistribution layer.

[0051] (14) In such Figure 14 A second insulating layer and a conductive via structure are formed on the wafer-level structure shown, resulting in the following: Figure 15 The structure shown is as follows. 111 is the second insulating layer, 307 is the upper surface of the second insulating layer, and 308 is the third conductive via structure formed on the second insulating layer.

[0052] (15) In such Figure 15 The second metal redistribution layer (i.e., pads) on the wafer-level structure shown results in the following: Figure 16 The structure shown is as follows. 112 is the second metal redistribution layer.

[0053] (16) In such Figure 16 The ball-mounting process is completed on the wafer-level structure shown, resulting in the following: Figure 17 The structure shown is shown. 113 is a solder ball structure.

[0054] (17) will be as follows Figure 17 The wafer shown is cut to obtain the following: Figure 18 The diagram shows an integrated chip structure that combines a CIS chip with other types of chips and completes the packaging using FOWLP technology.

[0055] like Figure 18As shown in the structure, this embodiment fabricates a system-integrated chip structure that combines a CIS chip with other types of chips using Hybrid Bonding technology and completes packaging using FOWLP technology, ultimately resulting in a high-performance, low-power, miniaturized, heterogeneous process integrated, and low-cost system-integrated chip structure. The specific layers in this structure are as follows: 10-CIS chip, 11-CIS photosensitive area, 12-CIS conductive structure, 13-high-transparency adhesive film layer, 14-high-transparency glass layer, 101-silicon substrate, 104-non-bonded layer, 105-third conductive structure, 106-adhesive film, 107-second type of chip, 108-second type of chip conductive structure, 109-first insulating layer, 110-first metal redistribution layer, 111-second insulating layer, 112-second metal redistribution layer (pad), 113-conductive structure (solder ball).

[0056] It is worth noting that in the description of this utility model, "multiple" means two or more, unless otherwise explicitly specified. In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can also refer to a mechanical connection. The circuits described in this utility model are all commonly used circuits in the art, and other related components are all commonly used existing components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0057] It will be apparent to those skilled in the art that this utility model patent is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this utility model patent. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this utility model patent is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be encompassed within this utility model patent. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A wafer-level system-on-a-chip (SoC) structure fabricated using Hybrid Bonding and FOWLP technologies, characterized in that, It includes a wafer-level CIS chip, a silicon-based carrier wafer, and a wafer-level CID chip; the wafer-level CIS chip has an adhesive film layer and a glass layer on its front side; Thinning is performed on the back side of the wafer-level CIS chip to form an unbonded layer; conductive via structures are formed on the back side of the wafer-level CIS chip; conductive structures are formed on the back side of the wafer-level CIS chip. A non-bonded layer is formed on a silicon-based carrier wafer; a conductive via structure is formed on the silicon-based carrier wafer; a conductive structure is formed on the silicon-based carrier wafer; a wafer-level CID chip and the silicon-based carrier wafer are bonded together; the back side of the silicon-based carrier wafer is thinned after bonding to form a groove structure; a second type of chip is attached within the groove structure of the bonded wafer; a first insulating layer is formed on the bonded wafer; a first metal redistribution layer is formed on the bonded wafer; a second insulating layer is formed on the bonded wafer; a second metal redistribution layer is formed on the bonded wafer; balls are implanted on the second metal redistribution layer of the bonded wafer; and a single die is obtained by dicing.

2. The wafer-level system-on-a-chip structure according to claim 1, characterized in that: The wafer-level CIS chip includes a CIS chip (10), a photosensitive area disposed on the upper surface of the CIS chip (10), and a CIS chip conductive structure (12).

3. The wafer-level system-on-a-chip structure according to claim 2, characterized in that: A high-transmittance adhesive film layer (13) and a high-transmittance glass layer (14) are sequentially disposed on the upper surface of the wafer-level CIS chip.

4. The wafer-level system-on-a-chip structure according to claim 3, characterized in that: Thinning is performed on the back side of the wafer-level CIS chip, and a first non-conductive layer (15) is provided; a first conductive structure via (205) is provided at the position corresponding to the conductive structure of the wafer-level CIS chip on this structure, the first conductive structure via (205) penetrates the first non-conductive layer (15) and the CIS chip (10), and a first conductive structure (16) is provided at the first conductive structure via (205).

5. The wafer-level system-on-a-chip structure according to claim 1, characterized in that: A second non-conductive layer (102) is disposed on the silicon-based carrier sheet (101), a through hole (310) is formed on the silicon-based carrier sheet (101) with the second non-conductive layer (102), and a second conductive structure (103) is formed on the through hole (310).

6. The wafer-level system-on-a-chip structure according to claim 2 or 5, characterized in that: The wafer-level CIS chip composed of the first conductive structure (16) and the silicon-based carrier wafer (101) composed of the second conductive structure (103) are bonded together using Hybrid Bonding technology. The two wafers are bonded together to form a non-conductive layer (104) and a third conductive structure (105). A groove structure (303) is provided on the wafer-level structure after the above bonding.

7. The wafer-level system-on-a-chip structure according to claim 6, characterized in that: The groove structure contains a second type of chip (107) that has been thinned and cut using an adhesive film (106). The second type of chip (107) has a second type of chip conductive structure (108). A gap structure (304) is formed between the second type of chip (107) and the groove structure (303). A first insulating layer (109) is provided on the wafer-level structure of the second type of chip conductive structure (108), and a second conductive via structure (306) is formed. A first metal redistribution layer (110) is formed on the wafer-level structure of the second conductive via structure (306).

8. The wafer-level system-on-a-chip structure according to claim 7, characterized in that: A second insulating layer (111) and a third conductive via structure (308) are disposed on the wafer-level structure of the first metal redistribution layer (110).

9. The wafer-level system-on-a-chip structure according to claim 8, characterized in that: A second metal redistribution layer (112) is formed on the wafer-level structure of the third conductive via structure (308); solder balls (113) are implanted on the wafer-level structure of the second metal redistribution layer (112); and the wafer with the implanted solder balls (113) is cut to obtain a single die.

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