Package structure

Abstract

The utility model provides a packaging structure. The packaging structure comprises a first semiconductor tube core, a second semiconductor tube core, an insulation packaging body and a redistribution layer. An insulating encapsulation laterally surrounds the first semiconductor die and the second semiconductor die, where the insulating encapsulation includes a first portion sandwiched between the first semiconductor die and the second semiconductor die, the first portion having a first recess adjacent an edge of the first semiconductor die, and a second recess adjacent an edge of the second semiconductor die. A redistribution layer is disposed over and electrically connected to the first semiconductor die and the second semiconductor die.

Description

Technical Field

[0001] This utility model relates to a packaging structure and a method for manufacturing the packaging structure. Background Technology

[0002] Semiconductor components and integrated circuits used in various electronic applications (such as mobile phones and other electronic devices) are typically manufactured on a single semiconductor wafer. The wafer die can be processed and packaged at the wafer level along with other semiconductor components or dies, and various technologies for wafer-level packaging have been developed. Utility Model Content

[0003] An embodiment of this utility model provides a packaging structure including a first semiconductor die, a second semiconductor die, an insulating encapsulator, and a redistribution layer. The insulating encapsulator laterally surrounds the first semiconductor die and the second semiconductor die, wherein the insulating encapsulator includes a first portion sandwiched between the first semiconductor die and the second semiconductor die, the first portion having a first recess adjacent to the edge of the first semiconductor die and a second recess adjacent to the edge of the second semiconductor die. The redistribution layer is disposed on the first semiconductor die and the second semiconductor die and is electrically connected to the first semiconductor die and the second semiconductor die.

[0004] This invention provides a packaging structure including two semiconductor dies, an insulating encapsulator, a thermal interface material, and a bridging structure. A first portion of the insulating encapsulator is disposed between the two semiconductor chips, wherein a first surface of the first portion is flat, and a second surface opposite to the first surface of the first portion has a protrusion. A second portion of the insulating encapsulator surrounds the first portion and the two semiconductor chips, wherein a third surface and a fourth surface opposite to the third surface of the second portion are flat. The thermal interface material is disposed on the back surfaces of the two semiconductor dies. The bridging structure overlaps with the two semiconductor dies and electrically connects the two semiconductor dies to each other. Attached Figure Description

[0005] The best understanding of all aspects of this disclosure will be achieved by referring to the accompanying drawings and reading the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of explanation, the critical dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figures 1A to 13 These are schematic top and cross-sectional views of various stages in a method for manufacturing a packaging structure according to some exemplary embodiments of the present disclosure.

[0007] Figures 14A to 14E This is an enlarged cross-sectional view of the first portion of the insulating encapsulation in the packaging structure according to various embodiments of the present disclosure.

[0008] Figure 15 This is a schematic cross-sectional view of a packaging structure according to some other embodiments of this disclosure.

[0009] Figures 16 to 18 These are schematic cross-sectional views of various stages of a method for manufacturing a packaging structure according to some other exemplary embodiments disclosed herein.

[0010] Figure 19 This is a schematic cross-sectional view of a stacked package (PoP) structure according to some embodiments of the present disclosure.

[0011] Figure 20 This is a schematic cross-sectional view of a stacked package (PoP) structure according to some other embodiments of this disclosure.

[0012] Explanation of reference numerals in the attached figures

[0013] 101: Semiconductor wafers

[0014] 102: Semiconductor die

[0015] 102A: First Semiconductor die

[0016] 102A-1, 102B-1: Semiconductor substrate

[0017] 102A-2, 102B-2, 222C, 608C, 750: Conductive pads

[0018] 102A-3, 102B-3: Passivation layer

[0019] 102A-4, 102B-4: Conductive pillars

[0020] 102A-5, 102B-5: Protective layer

[0021] 102A-SD, 102B-SD: Side Surface

[0022] 102B: Second Semiconductor Die

[0023] 104: Core bonding film

[0024] 204, 220: Insulating materials

[0025] 204', 220', 606', 760: Insulating Encapsulation

[0026] 204A1, 606A1: Part 1

[0027] 204A1-S1, 606A1-S1: First surface

[0028] 204A1-S2, 606A1-S2: Second Surface

[0029] 204A2, 606A2: Part Two

[0030] 204A2-S1, 606A2-S1: Third Surface

[0031] 204A2-S2, 606A2-S2: Fourth Surface

[0032] 204-TS, 212-TS, 214-TS, 220-TS: Top surface

[0033] 206, 304B, 306B, 222A, 608A: Dielectric layer

[0034] 208: First conductive component

[0035] 208A, 210A: Conductive main body

[0036] 208B, 210B: Seed layer portion

[0037] 210: Second conductive component

[0038] 212: Through hole

[0039] 214: Bridging Structure

[0040] 214A, 710: Substrate

[0041] 214B: Connection Structure

[0042] 214C: Substrate Through Hole

[0043] 214D: Core Bridge

[0044] 216, 308: Conductive connectors

[0045] 218: Bottom Filling Structure

[0046] 222B, 608B: Conductive components

[0047] 224, 610, 622: Conductive terminals

[0048] 300: Circuit substrate

[0049] 302: Base Core

[0050] 304: First redistribution structure

[0051] 304A, 306A: Metallization layer

[0052] 306: Second redistribution structure

[0053] 402: Passive Components

[0054] 404: Bottom filler

[0055] 406: Thermal interface material

[0056] 406PT1: First protrusion

[0057] 406PT2: Second protrusion

[0058] 501: Adhesive material

[0059] 502: Cover Structure

[0060] 602: Carrier substrate

[0061] 604: Insulator Through Hole

[0062] 608, RDL1, RDL2: Redistribution Layer

[0063] 700: Second Package

[0064] 720: Semiconductor chip

[0065] 730: Joint line

[0066] 740: solder pad

[0067] 770: Bottom filler glue

[0068] AX1, AX2: Air gaps

[0069] D1, D2: Depth

[0070] PK1, PK2, PK3: Packaging Structure

[0071] PoP1, PoP2: Stacked packaging structure

[0072] PT1: Protrusion

[0073] RC1: First recessed part

[0074] RC2: Second recess

[0075] RC3: Third recess

[0076] RC4: Fourth Depression

[0077] W1, W2: Width

[0078] X1: First distance Detailed Implementation

[0079] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a second feature on or over a first feature may include embodiments in which the second feature and the first feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the second feature and the first feature, such that the second feature and the first feature may not be in direct contact. Furthermore, component symbols and / or letters may be reused in various instances in this disclosure. Such reuse is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0080] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “on,” “over,” “overlying,” “above,” and “upper” may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0081] Other features and processes may also be included. For example, test structures may be included to illustrate verification testing of three-dimensional (3D) packaged or 3D integrated circuit (3DIC) devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which enable testing of the 3D package or 3DIC, the use of probes and / or probe cards, and similar operations. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods, including intermediate verification of known good dies, to improve yield and reduce costs.

[0082] Figures 1A to 13 These are schematic top and cross-sectional views of various stages in a method for manufacturing a packaging structure according to some exemplary embodiments of this disclosure. Reference Figure 1A A semiconductor wafer 101 is provided. The semiconductor wafer 101 includes a plurality of semiconductor dies 102. (Reference) Figure 1BIn some embodiments, a die bonding film 104 is formed on the semiconductor wafer 101, located on the back side of each semiconductor die 102. The die bonding film 104 is made of a thermoplastic or thermosetting polymer resin having conductive or non-conductive fillers. The die bonding film 104 can be used as an adhesive to attach the semiconductor die 102 to a carrier substrate in subsequent steps.

[0083] refer to Figure 2 In some embodiments, the semiconductor wafer 101, together with the die bonding film 104, is sliced ​​to separate the individual semiconductor dies 102 (including 102A and 102B). For example, in an exemplary embodiment, a first semiconductor die 102A and a second semiconductor die 102B having at least a die bonding film 104 attached to their back sides are obtained. In some embodiments, each of the first semiconductor die 102A and the second semiconductor die 102B includes a semiconductor substrate (102A-1 / 102B-1), a plurality of conductive pads (102A-2 / 102B-2), a passivation layer (102A-3 / 102B-3), a plurality of conductive pillars (102A-4 / 102B-4), and a protective layer (102A-5 / 102B-5).

[0084] like Figure 2 As shown, multiple conductive pads (102A-2 / 102B-2) are disposed on a semiconductor substrate (102A-1 / 102B-1). A passivation layer (102A-3 / 102B-3) is formed over the semiconductor substrate (102A-1 / 102B-1) and has openings that partially expose the conductive pads (102A-2 / 102B-2) on the semiconductor substrate (102A-1 / 102B-1). The semiconductor substrate (102A-1 / 102B-1) may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and may also include active components (e.g., transistors, etc.) and selective passive components (e.g., resistors, capacitors, inductors, etc.) formed therein. The conductive pads (102A-2 / 102B-2) may be aluminum pads, copper pads, or other suitable metal pads. The passivation layer (102A-3 / 102B-3) can be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of any suitable dielectric material.

[0085] Furthermore, in some embodiments, a post-passivation layer (not shown) may be selectively formed over the passivation layer (102A-3 / 102B-3). The post-passivation layer covers the passivation layer (102A-3 / 102B-3) and has multiple contact openings. The conductive pads (102A-2 / 102B-2) are partially exposed by the contact openings of the post-passivation layer. The post-passivation layer may be a benzocyclobutene (BCB) layer, a polyimide layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers. In some embodiments, conductive pillars (102A-4 / 102B-4) are formed on the conductive pads (106B, 107B) via electroplating. The conductive pillars (102A-4 / 102B-4) may be made of a first material, for example, copper, etc. In some embodiments, a protective layer (102A-5 / 102B-5) is formed on a passivation layer (102A-3 / 102B-3) or a post-passivation layer, and covers the conductive pillars (102A-4 / 102B-4) to protect the conductive pillars (102A-4 / 102B-4).

[0086] In some embodiments, the first semiconductor die 102A may be a logic component, such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller, etc. The second semiconductor die 102B may be a memory component, such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. In some embodiments, the first semiconductor die 102A and the second semiconductor die 102B may be the same type of die, such as an SoC die. The first semiconductor die 102A and the second semiconductor die 102B may have different dimensions (e.g., different heights and / or surface areas), or they may have the same dimensions (e.g., the same height and / or surface area).

[0087] refer to Figure 3The first semiconductor die 102A and the second semiconductor die 102B are placed on the carrier substrate 202. In one embodiment, the carrier substrate 202 may be a glass carrier or any suitable carrier used in methods for manufacturing package structures for carrying semiconductor wafers or reconstructing wafers. In some embodiments, a release layer (not shown) may be formed on the carrier substrate 202, thereby allowing the first semiconductor die 102A and the second semiconductor die 102B to be placed on the release layer. In some embodiments, the release layer may be any material suitable for bonding and peeling the carrier substrate 202 to an overlying layer or any wafer disposed thereon. In some embodiments, the release layer may include a release layer (e.g., a light-to-heat conversion (LTHC) layer) or an adhesive layer (e.g., a UV-curable adhesive or a thermosetting adhesive).

[0088] In some embodiments, after placing the first semiconductor die 102A and the second semiconductor die 102B on the carrier substrate 202 (or on the separation layer), a portion of the die bonding film 104 may be squeezed to partially cover the side surfaces (102A-SD, 102B-SD) of the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, the first semiconductor die 102A is placed next to the second semiconductor die 102B on the carrier substrate 202 such that the first semiconductor die 102A and the second semiconductor die 102B are spaced apart by a first distance X1, wherein the first distance X1 is in the range of 100 μm to 200 μm.

[0089] In some embodiments, after the first semiconductor die 102A and the second semiconductor die 102B are placed on the carrier substrate 202, an insulating material 204 is formed on the carrier substrate 202 to cover the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, the insulating material 204 is formed, for example, by a compression molding process, to fill the gap between the first and second semiconductor dies (102A / 102B) and encapsulate the first and second semiconductor dies (102A / 102B). In this stage, the conductive pillars (102A-4 / 102B-4) and the protective layers (102A-5 / 102B-5) of the first and second semiconductor dies (102A / 102B) are encapsulated by the insulating material 204 and are well protected by the insulating material 204. In other words, the conductive pillars (102A-4 / 102B-4) and protective layer (102A-5 / 102B-5) of the semiconductor die (102A / 102B) are not exposed and are well protected by the insulating material 204.

[0090] In some embodiments, the insulating material 204 includes, for example, a polymer (such as epoxy resin, phenolic resin, silicone resin, or other suitable resin), a dielectric material having low dielectric constant (Dk) and low loss tangent (Df), or other suitable materials. In some embodiments, the insulating material 204 may also include inorganic fillers or inorganic compounds (e.g., silica, clay, etc.) that may be added thereto to optimize the coefficient of thermal expansion (CTE) of the insulating material 204. However, this disclosure is not limited thereto.

[0091] refer to Figure 4 In subsequent steps, the insulating material 204 is partially removed to expose the conductive pillars (102A-4 / 102B-4) of the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, the insulating material 204 and the protective layer (102A-5 / 102B-5) are ground or polished through a planarization step. For example, the planarization step is performed through a mechanical grinding process and / or a chemical mechanical polishing (CMP) process until the top surface of the conductive pillars (102A-4 / 102B-4) is exposed. In some embodiments, the insulating material 204 is polished to form an insulating encapsulation 204'. In some embodiments, after the planarization step, the top surfaces of the conductive pillars (102A-4 / 102B-4), the top surfaces (102A-TS / 102B-TS) of the first semiconductor die 102A and the second semiconductor die 102B, and the top surface 204-TS of the insulating encapsulation 204' are coplanar and flush with each other. In some embodiments, a cleaning step may be selectively performed after a mechanical polishing or chemical mechanical polishing (CMP) step. For example, a cleaning step is performed to clean and remove residues generated in the planarization step. However, this disclosure is not limited thereto, and the planarization step may be performed by any other suitable method.

[0092] In an exemplary embodiment, the insulating encapsulation 204' has a first portion 204A1 and a second portion 204A2. The first portion 204A1 is a part of the insulating encapsulation 204' sandwiched between the first semiconductor die 102A and the second semiconductor die 102B, while the second portion 204A2 is a part of the insulating encapsulation 204' that laterally surrounds the first portion 204A1 and laterally surrounds the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, since a die bonding film 104 is present on the sidewalls of the first semiconductor die 102A and the second semiconductor die 102B, the first portion 204A1 of the insulating encapsulation 204' includes a protrusion PT1. For example, the first portion 204A1 of the insulating encapsulation 204' has a first surface 204A1-S1 and a second surface 204A1-S2 opposite to the first surface 204A1-S1. The first surface 204A1-S1 of the first portion 204A1 is a flat surface, while the second surface 204A1-S2 of the first portion 204A1 includes a protrusion PT1. In some embodiments, the maximum width of the first portion 204A1 of the insulating encapsulation 204', measured from the side surface of the first semiconductor die 102A to the side surface of the second semiconductor die 102B, is in the range of 100 μm to 200 μm. In some embodiments, the second portion 204A2 surrounding the first portion 204A1 has a third surface 204A2-S1 and a fourth surface 204A2-S2 opposite to the third surface 204A2-S1, wherein the third surface 204A2-S1 and the fourth surface 204A2-S2 are flat surfaces. In some embodiments, the fourth surface 204A2-S2 of the second portion 204A2 is substantially flush with the second surface 204A1-S2 of the first portion 204A1 including the protrusion PT1.

[0093] refer to Figure 5In subsequent steps, a redistribution layer RDL1 can be formed on the insulating encapsulation 204' and over the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, forming the redistribution layer RDL1 includes forming a dielectric layer 206 disposed on the insulating encapsulation 204' and forming a first conductive component 208 and a second conductive component 210 on the dielectric layer 206. In some embodiments, the dielectric layer 206 can be formed from a photosensitive material that can be patterned using a photomask, such as PBO, polyimide, BCB-type polymers, cyclic olefin copolymers, acrylic copolymers, etc., which can be formed by spin coating, lamination, chemical vapor deposition (CVD), etc. Other acceptable dielectric materials formed by any acceptable process can also be used. In some embodiments, the dielectric layer 206 can be patterned to form openings exposing conductive pillars (102A-4 / 102B-4) of the first semiconductor die 102A and the second semiconductor die 102B.

[0094] In some embodiments, a first conductive member 208 and a second conductive member 210 are formed on a dielectric layer 206 and fill the openings in the dielectric layer 206. For example, the first conductive member 208 and the second conductive member 210 are conductive pillars (102A-4 / 102B-4) electrically connected to a first semiconductor die 102A and a second semiconductor die 102B. In some embodiments, forming the first conductive member 208 and the second conductive member 210 includes forming seed layer portions 208B and 210B and forming conductive body portions 208A and 210A. For example, a seed layer (not shown) is conformally formed over the dielectric layer 206 and within the openings of the dielectric layer 206. Subsequently, a conductive material may be formed over the seed layer, wherein the seed layer is patterned to form the seed layer portions 208B and 210B, and the conductive material is patterned to form the conductive body portions 208A and 210A. In some embodiments, the seed layer portion 208B is sandwiched between the conductive pillar (102A-4 / 102B-4) and the conductive body portion 208A, while the seed layer portion 210B is sandwiched between the conductive pillar (102A-4 / 102B-4) and the conductive body portion 210A. In some embodiments, the seed layer portions 208B and 210B are formed by electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), or combinations thereof. In one embodiment, the seed layer portions 208B and 210B are formed by sequentially depositing or sputtering a titanium layer and a copper layer. In some embodiments, the conductive body portions 208A and 210A are formed by plating methods such as electroless plating or electroplating, and can be formed of materials such as copper, titanium, tungsten, aluminum, etc.

[0095] refer to Figure 6 In subsequent steps, a plurality of through-holes 212 may be formed on the second conductive component 210. For example, the through-holes 212 are disposed on and electrically connected to the conductive body portion 210A of the second conductive component 210. In some embodiments, forming the through-holes 212 includes forming a mask pattern (not shown) with an opening, then forming a metal material (not shown) to fill the opening by electroplating or deposition, and removing the mask pattern to form the through-holes 212. In some embodiments, the through-holes 212 are made of a metal material such as copper or a copper alloy.

[0096] refer to Figure 7After forming the via 212, a bridging structure 214 is disposed on the first conductive component 208 to electrically connect it to the conductive body portion 208A of the first conductive component 208. The bridging structure 214 may be a local silicon interconnect (LSI), a large scale integration package (LSI), an interposer dies, etc. In some embodiments, the bridging structure 214 partially overlaps with the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, the bridging structure 214 includes a substrate 214A, a connection structure 214B, a substrate via 214C, and a die bridge 214D. The substrate 214A may be a semiconductor substrate, a dielectric layer, etc. The substrate via 214C extends through the substrate 214A and is exposed on the back side of the bridging structure 214. The die bridge 214D may be a metallization layer formed in the substrate 214A and electrically connects the first semiconductor die 102A to the second semiconductor die 102B. In this way, the bridging structure 214 can be used to directly connect semiconductor dies (102A / 102B) and allow communication between semiconductor dies (102A / 102B). The connection structure 214B is disposed on the substrate 214A and electrically connected to the substrate via 214C and the die bridge 214D.

[0097] In some embodiments, a conductive connector 216 is disposed between the first conductive component 208 and the connection structure 214B of the bridging structure 214. In some embodiments, a reflow process is performed to electrically connect the conductive connector 216 to the first conductive component 208 and the connection structure 214B. In some embodiments, the bridging structure 214 is electrically connected to the first semiconductor die 102A and the second semiconductor die 102B through the conductive connector 216 and the first conductive component 208.

[0098] In an exemplary embodiment, the conductive connector 216 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. The conductive connector 216 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connector 216 is initially formed by evaporation, electroplating, printing, solder transfer, ball placement, or other methods to form a solder layer. After the solder layer is structurally formed, a reflow process can be performed to shape the material into the desired bump shape and to engage the conductive connector 216 with the first conductive component 208 and the connection structure 214B.

[0099] After the bridging structure 214 is placed on the first conductive component 208, an underfill structure 218 can be formed to fill the gap between the bridging structure 214 and the redistribution layer RDL1. For example, the underfill structure 218 covers and surrounds the conductive body portion 208A of the connecting structure 214B, the conductive connector 216, and the first conductive component 208. The underfill structure 218 can reduce stress and protect the connection from reflow of the conductive connector 216. The underfill structure 218 can be formed from molding compounds, epoxy resins, etc. The underfill structure 218 can be formed after attaching the bridging structure 214 via a capillary flow process, or it can be formed before attaching the bridging structure 214 via a suitable deposition method. The underfill structure 218 can be applied in liquid or semi-liquid form and subsequently cured.

[0100] refer to Figure 9 After performing a reflow soldering process to bond the conductive connector 216 to the connection structure 214B and the first conductive component 208, an insulating material 220 is formed over the dielectric layer 206 and the insulating encapsulator 204', and said insulating material 220 is formed to encapsulate the bridging structure 214 and the via 212. In some embodiments, the insulating material 220 is formed, for example, by a compression molding process, and fills the gap between the bridging structure 214 and the adjacent via 212. During this stage, the bridging structure 214 and the via 212 are encapsulated by the insulating material 204' and are well protected.

[0101] In some embodiments, insulating material 220 comprises a polymer (e.g., epoxy resin, phenolic resin, silicone resin, or other suitable resin), a dielectric material having a low dielectric constant (Dk) and a low loss tangent (Df), or other suitable material. In alternative embodiments, insulating material 220 may comprise an acceptable insulating encapsulating material. In some embodiments, insulating material 220 may also comprise inorganic fillers or inorganic compounds (e.g., silica, clay, etc.) that may be added thereto to optimize the coefficient of thermal expansion (CTE) of insulating material 220. In some embodiments, insulating material 220 may be the same as or different from insulating material 204. This disclosure is not limited thereto.

[0102] refer to Figure 9 In subsequent steps, a thinning step is performed to form the insulating encapsulation 220'. For example, the thickness of the insulating material 220 is reduced until the top surface 212-TS of the through-hole 212 and the top surface 214-TS of the substrate through-hole 214C are exposed. In some embodiments, the insulating material 220 is ground or polished by a mechanical grinding process and / or a chemical mechanical polishing (CMP) process to form the insulating encapsulation 220'. In some embodiments, the through-hole 212 may be partially polished such that the top surface 212-TS of the through-hole 212 is flush with the top surface 214-TS of the substrate through-hole 214C. In some embodiments, the top surface 220-TS of the insulating encapsulation 220', the top surface 212-TS of the through-hole 212, and the top surface 214-TS of the substrate through-hole 214C are coplanar and flush with each other.

[0103] refer to Figure 10 Following the thinning step, a redistribution layer RDL2 is formed on the insulating encapsulation 220' above the bridging structure 214 and the via 212. In some embodiments, the redistribution layer RDL2 may include a plurality of dielectric layers 222A and a plurality of conductive components 222B stacked alternately. Although only two conductive components 222B and three dielectric layers 222A are shown herein, the scope of this disclosure is not limited to the scope of the embodiments. In other embodiments, the number of conductive components 222B and dielectric layers 222A may be adjusted based on product requirements. In some embodiments, the conductive components 222B are electrically connected to the first semiconductor die 102A and the second semiconductor die 102B through the via 212. In some embodiments, the conductive components 222B are electrically connected to the substrate via 214C of the bridging structure 214.

[0104] In some embodiments, the dielectric layer 222A may be made of polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), or borosilicate glass (BSG), and may be patterned using photolithography and / or etching processes. In some embodiments, the dielectric layer 222A is formed using appropriate fabrication techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. This disclosure is not limited thereto.

[0105] In some embodiments, the conductive component 222B may be made of a conductive material formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof, and may be patterned using photolithography and etching processes. In some embodiments, the conductive component 222B may be a patterned copper layer or other suitable patterned metal layer. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing trace amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0106] After forming the redistribution layer RDL2, a plurality of conductive pads 222C can be provided on the exposed top surface of the topmost layer of the conductive component 222B for electrical connection to conductive terminals (e.g., conductive balls). In some embodiments, the conductive pads 222C are, for example, under-ball metallurgy (UBM) patterns for ball mounting. Figure 10 As shown, conductive pads 222C are formed on and electrically connected to the redistribution layer RDL2. In some embodiments, the material of the conductive pads 222C may include copper, nickel, titanium, tungsten, or alloys thereof, and may be formed, for example, by an electroplating process. This disclosure does not limit the number of conductive pads 222C, and they can be selected based on the design layout. In some alternative embodiments, the conductive pads 222C may be omitted. In other words, the conductive terminals 224 formed in subsequent steps can be directly disposed on the redistribution layer RDL2.

[0107] like Figure 10As shown, after forming the conductive pads 222C, a plurality of conductive terminals 224 are disposed on the conductive pads 222C and above the redistribution layer RDL2. In some embodiments, the conductive terminals 224 may be disposed on the conductive pads 222C via a ball-mounting process or a reflow process. In some embodiments, the conductive terminals 224 are, for example, solder balls, ball grid array (BGA) balls, or controlled collapse chip connection (C4) bumps. In some embodiments, the conductive terminals 224 are connected to the redistribution layer RDL2 through the conductive pads 222C. In some embodiments, some conductive terminals 224 may be electrically connected to the semiconductor die (102A / 102B) through the redistribution layer RDL2. In this disclosure, the number of conductive terminals 224 is not limited thereto, and may be specified and selected according to the number of conductive pads 222C.

[0108] Please refer to Figure 11A and Figure 11B After forming the redistribution layer RDL2 and placing the conductive terminals 224 on it, it is then... Figure 10 The structure shown is flipped and attached to a strip supported by a frame (not shown). In some embodiments, the carrier substrate 202 is peeled off to separate the first semiconductor die 102A and the second semiconductor die 102B from the carrier substrate 202. In some embodiments, the separation process includes projecting light, such as laser or ultraviolet light, onto the release layer, thereby easily removing the carrier substrate 202. In some embodiments, the die bonding film 104 attached to the back of the first semiconductor die 102A and the second semiconductor die 102B is also removed. Figure 11A And such as Figure 11A Top view of the structure Figure 11B As shown, when the die bonding film 104 is removed, the first portion 204A1 of the insulating encapsulation 204' sandwiched between the first semiconductor die 102A and the second semiconductor die 102B has a first recess RC1 adjacent to the edge of the first semiconductor die 102A and a second recess RC2 adjacent to the edge of the second semiconductor die 102B. For example, the protrusion PT1 is located between the first recess RC1 and the second recess RC2.

[0109] In an exemplary embodiment, the presence of the first recess RC1 and the second recess RC2 located at the edges of the first semiconductor die 102A and the second semiconductor die 102B improves the die-to-die bending strength of the first portion 204A1 of the insulating encapsulation 204'. This solves the molding crack problem of the insulating encapsulation 204' surrounding the first semiconductor die 102A and the second semiconductor die 102B.

[0110] refer to Figure 12In subsequent steps, conductive terminal 224 is used to... Figure 11A The structure shown is attached to a circuit substrate 300. The circuit substrate 300 can be an intermediary, a printed circuit board (PCB), etc. In the illustrated embodiment, the circuit substrate 300 includes a substrate core 302, a first redistribution structure 304, and a second redistribution structure 306 located on two opposite sides of the substrate core 302. The substrate core 302 can be formed of a semiconductor material, such as silicon, germanium, diamond, etc. Alternatively, compound materials such as rhodium silicon, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, germanium silicon carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations thereof can be used. Additionally, the substrate core 302 can be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon-germanium, SOI, silicon-on-insulator (SiGe-on-insulator; SGOI), or combinations thereof. In an alternative embodiment, the substrate core 302 is based on an insulating core material, such as a fiberglass reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternative materials for the core material include bismaleimide-triazine (BT) resin, or other PCB materials or films. Building films such as Ajinomoto Build-up Film (ABF) or other laminates can be used for the substrate core 302.

[0111] In some embodiments, the substrate core 302 may include active and / or passive components (not shown separately). A variety of devices, such as transistors, capacitors, resistors, combinations thereof, etc., can be used to produce the structural and functional designs of the device stack. These devices can be formed using any suitable method.

[0112] In some embodiments, the first redistribution structure 304 and the second redistribution structure 306 disposed on the substrate core 302 include a plurality of metallization layers 304A, 306A and a plurality of dielectric layers 304B, 306B surrounding the metallization layers 304A, 306A. The metallization layers 304A, 306A may be formed of a conductive material (e.g., copper), while the dielectric layers 304B, 306B may be formed of a low-k dielectric material or any suitable dielectric material. In some embodiments, the metallization layer 304A of the first redistribution structure 304 is electrically connected to the metallization layer 306A of the second redistribution structure 306 through a via structure embedded in the substrate core 302. In some embodiments, a conductive connector 308 is soldered back to the metallization layer 304A of the first redistribution structure 304, and a conductive terminal 224 is electrically connected to the metallization layer 306A of the second redistribution structure 306.

[0113] Furthermore, an underfill 404 may be formed between the redistribution layer RDL2 and the second redistribution structure 306 to laterally surround the conductive connector 308 and reduce stress and protect the connection resulting from reflow of the conductive connector 308. In some embodiments, the underfill 404 is formed by a capillary flow process after attaching the top package (including the first and second semiconductor dies 102A, 102B, bridging structure 214, and redistribution layer RDL2) or by a suitable deposition method before attaching the top package. In some embodiments, the underfill 404 may partially cover the sidewalls of the redistribution layer RDL2.

[0114] In some embodiments, a passive component 402 (e.g., a surface mount device (SMD)) may be mounted onto the circuit substrate 300. For example, the passive component 402 may be disposed on and electrically connected to the second redistribution structure 306. In some embodiments, the passive component 402 is coupled to the same surface of the second redistribution structure 306 as the conductive terminal 224. In some embodiments, the passive component 402 is spaced apart from the conductive terminal 224 and the underfill 404.

[0115] refer to Figure 13After the passive component 402 is installed, a thermal interface material 406 is applied to the back surfaces of the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, the thermal interface material 406 may fill the first recess RC1 and the second recess RC1, but this disclosure is not limited thereto. In alternative embodiments, the thermal interface material 406 is not filled into the first recess RC1 and the second recess RC1. In some embodiments, after the thermal interface material 406 is applied, the cover structure 502 is attached to the circuit substrate 300 using an adhesive material 501. For example, the cover structure 502 is pressed onto the thermal interface material 406, such that the thermal interface material 406 is sandwiched between the cover structure 502 and the back surfaces of the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, the cover structure 502 is configured to surround the first semiconductor die 102A and the second semiconductor die 102B, the bridging structure 214, and the redistribution layer RDL2. This completes the package structure PK1 according to some exemplary embodiments of this disclosure.

[0116] exist Figure 13 In the package structure PK1 shown, the insulating encapsulation 204' has a first recess RC1 and a second recess RC2 located at the edges of the first semiconductor die 102A and the second semiconductor die 102B. In this way, the molding crack problem of the insulating encapsulation 204' surrounding the first semiconductor die 102A and the second semiconductor die 102B can be solved.

[0117] The following will combine Figures 14A to 14E To describe in more detail Figure 13 The arrangement details of the first recess RC1 and the second recess RC1 of the thermal interface material 406 relative to the first portion 204A1 of the insulating encapsulation 204' are shown.

[0118] Figure 14A and Figure 14E This is an enlarged cross-sectional view of the first portion 204A1 of the insulating encapsulator 204' in the packaging structure according to various embodiments of this disclosure. Figure 14AAs shown, in some embodiments, the first portion 204A1 of the insulating encapsulation 204' is shown as including a first recess RC1 and a second recess RC2. A protrusion PT1 is located between the first recess RC1 and the second recess RC2. In some embodiments, the first recess RC1 has a depth D1 and a width W1, while the second recess RC2 has a depth D2 and a width W2. In some embodiments, the depth D1 of the first recess RC1 and the depth D2 of the second recess RC2 are in the range of 1 μm to 10 μm. In some embodiments, the depth D1 of the first recess RC1 and the depth D2 of the second recess RC2 are in the range of 5 μm to 10 μm. In an exemplary embodiment, the depth D1 and width W1 of the first recess RC1 are substantially equal to the depth D2 and width W2 of the second recess RC2. In some embodiments, the height of the protrusion PT1 of the first portion 204A1 is substantially equal to the depth D1 of the first recess RC1 or the depth D2 of the second recess RC2. In other words, the height of the protrusion PT1 can also be in the range of 1μm to 10μm.

[0119] like Figure 14A As further shown, after the thermal interface material 406 is disposed on the back surfaces of the first semiconductor die 102A and the second semiconductor die 102B, the thermal interface material 406 does not fill the first recess RC1 and the second recess RC2. In other words, the air gaps AX1 and AX2 exist between the protrusion PT1 of the first portion 204A1 of the insulating encapsulation 204' and the edges of the first and second semiconductor dies 102A and 102B.

[0120] like Figure 14B As further shown, in another embodiment, the thermal interface material 406 partially fills the first recess RC1 and the second recess RC2 of the insulating encapsulation 204'. In other words, the thermal interface material 406 includes a first protrusion 406PT1 and a second protrusion 406PT2 that partially cover the side surfaces of the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, the protrusion height of the first protrusion 406PT1 may be different from the protrusion height of the second protrusion 406PT2. Furthermore, since the thermal interface material 406 does not completely fill the first recess RC1 and the second recess RC2, air gaps AX1 and AX2 still exist between the protrusion PT1 of the first portion 204A1 of the insulating encapsulation 204' and the edges of the first and second semiconductor dies 102A and 102B.

[0121] like Figure 14CAs further shown, in another embodiment, the thermal interface material 406 completely fills the first recess RC1 and the second recess RC2 of the insulating encapsulation 204'. In other words, the first protrusion 406PT1 and the second protrusion 406PT2 fill the first recess RC1 and the second recess RC2 of the insulating encapsulation 204' and contact the side surface of the protrusion PT1. Figure 14D As further shown, in some other embodiments, the thermal interface material 406 is not filled into the first recess RC1 and the second recess RC2 of the insulating encapsulation. However, the depth D1 and width W1 of the first recess RC1 may differ from the depth D2 and width W2 of the second recess RC2. For example, the depth D2 and width W2 of the second recess RC2 may be greater than the depth D1 and width W1 of the first recess RC1.

[0122] like Figure 14E As shown, in some other embodiments, the depth D1 and width W1 of the first recess RC1 may differ from the depth D2 and width W2 of the second recess RC2. Furthermore, a thermal interface material 406 fills both the first recess RC1 and the second recess RC2. For example, the first protrusion 406PT1 completely fills the first recess RC1, while the second protrusion 406PT2 partially fills the second recess RC2. In such an embodiment, because the thermal interface material 406 does not completely fill the second recess RC2, an air gap AX2 still exists between the protrusion PT1 of the first portion 204A1 of the insulating encapsulation 204' and the edge of the second semiconductor die 102B.

[0123] In the above embodiments, it should be understood that the depth and width of the first recess RC1 and the second recess RC2 can be adjusted according to design requirements to simultaneously meet a depth range of 1μm to 10μm. Furthermore, the thermal interface material 406 may or may not be filled into the first recess RC1 and the second recess RC2. In some embodiments, when air gaps AX1 and AX2 exist in the package structure, residual chip bonding film material (adhesive material) may exist in the air gaps AX1 and AX2. It is worth noting that, as... Figures 14A to 14E All different embodiments of the thermal interface material 406 relative to the first recess RC1 and the second recess RC1 of the insulating encapsulation body 204' shown above can be applied to the above. Figure 13 The packaging structure PK1 shown is applicable to any packaging structure (or stacked packaging structure) described below.

[0124] Figure 15 This is a schematic cross-sectional view of a packaging structure according to some other embodiments of this disclosure. Figure 15 The package structure PK2 shown is... Figure 13The encapsulation structure PK1 shown is similar. Therefore, the same component symbols will be used to represent the same or similar parts, and will not be described in detail again here. The difference in the embodiments is that, Figure 15 In the package structure PK2 shown, the second portion 204A2 of the insulating encapsulator 204' further includes a third recess RC3 and a fourth recess RC4. For example, the third recess RC3 and the fourth recess RC4 can be formed by removing the die bonding film 104 in a manner similar to the first recess RC1 and the second recess RC2. In some embodiments, the third recess RC3 is located at the edge of the first semiconductor die 102A and opposite to the first recess RC1. Furthermore, the fourth recess RC4 is located at the edge of the second semiconductor die 102B and opposite to the second recess RC2.

[0125] exist Figure 15 In the package structure PK2 shown, the presence of the first recess RC1 and the second recess RC2 located at the edges of the first semiconductor die 102A and the second semiconductor die 102B improves the die-to-die bending strength of the first portion 204A1 of the insulating encapsulation 204'. This solves the molding crack problem of the insulating encapsulation 204' surrounding the first semiconductor die 102A and the second semiconductor die 102B.

[0126] Figures 16 to 18 These are schematic cross-sectional views of various stages of a method for manufacturing a packaging structure according to some other exemplary embodiments disclosed herein. Figure 16 As shown, it is as follows Figure 2A first semiconductor die 102A and a second semiconductor die 102B, with a die bonding film 104 on their back surfaces, are placed on a carrier substrate 602. The carrier substrate 602 may be a glass carrier or any suitable carrier used in methods for manufacturing package structures to support semiconductor wafers or reconstruct wafers. The first semiconductor die 102A and the second semiconductor die 102B are spaced apart by a first distance X1, wherein the first distance X1 is in the range of 100 μm to 200 μm. In some embodiments, a plurality of insulating vias 604 are provided on the carrier substrate 602 to surround the first semiconductor die 102A and the second semiconductor die 102. In some embodiments, the insulating vias 604 are integrated fan-out (“InFO”) vias. In one embodiment, the formation of the insulating via 604 includes forming a mask pattern (not shown) with openings, then forming a metal material (not shown) to fill the openings by electroplating or deposition, and removing the mask pattern to form the insulating via 604 on the carrier substrate 602. In some embodiments, the material of the mask pattern may include positive or negative photoresist. In one embodiment, the material of the insulating via 604 may include a metallic material, such as copper or a copper alloy. However, this disclosure is not limited thereto.

[0127] After placing the first semiconductor die 102A, the second semiconductor die 102B, and the insulating via 604 on the carrier substrate 602, the insulating encapsulation 606', the redistribution layer 608 (including the dielectric layer 608A and the conductive component 608B), the conductive pad 608C, and the conductive terminal 610 can be formed in the same manner as... Figures 1A to 13 The insulating encapsulation 220', redistribution layer RDL2, conductive pads 222C, and conductive terminals 224 of the described package structure PK1 are formed in a similar manner. Therefore, the details of the insulating encapsulation 606', redistribution layer 608, conductive pads 608C, and conductive terminals 610 will not be described in detail here.

[0128] refer to Figure 17 ,Will Figure 16The structure shown is flipped upside down, and the carrier substrate 602 is peeled off to separate the first semiconductor die 102A and the second semiconductor die 102B from the carrier substrate 602. For example, the peeling process includes projecting light, such as laser or ultraviolet light, onto a peeling layer on the carrier substrate 202, allowing easy removal of the carrier substrate 202. In some embodiments, the die bonding film 104 attached to the back surfaces of the first semiconductor die 102A and the second semiconductor die 102B is also removed. When the die bonding film 104 is removed, a first portion 606A1 of the insulating encapsulation 606' sandwiched between the first semiconductor die 102A and the second semiconductor die 102B has a first recess RC1 adjacent to the edge of the first semiconductor die 102A and a second recess RC2 adjacent to the edge of the second semiconductor die 102B. For example, a protrusion PT1 is located between the first recess RC1 and the second recess RC2.

[0129] In some embodiments, a first portion 606A1 of the insulating encapsulation 606' has a first surface 606A1-S1 and a second surface 606A1-S2 opposite to the first surface 606A1-S1. The first surface 606A1-S1 of the first portion 606A1 is a flat surface, while the second surface 606A1-S2 of the first portion 606A1 includes a protrusion PT1. Furthermore, a second portion 606A2 surrounding the first portion 606A1 has a third surface 606A2-S1 and a fourth surface 606A2-S2 opposite to the third surface 606A2-S1, wherein the third surface 606A2-S1 and the fourth surface 606A2-S2 are flat surfaces. In some embodiments, the fourth surface 606A2-S2 of the second portion 606A2 is substantially flush with the second surface 606A1-S2 of the first portion 204A1 including the protrusion PT1, and substantially flush with the top surface of the insulator via 604.

[0130] refer to Figure 18 In subsequent steps, a dielectric layer 620 is disposed on the back surfaces of the first semiconductor die 102A and the second semiconductor die 102B. In some embodiments, the dielectric layer 620 has an opening exposing an insulator via 604. In some embodiments, a conductive terminal 622 is also disposed in the opening to be electrically connected to the insulator via 604. This achieves a package structure PK3 with double-sided terminals. Figure 18 In the package structure PK3 shown, the dielectric layer 620 is not filled into the first recess RC1 and the second recess RC2. In other words, an air gap can exist between the protrusion PT1 of the first portion 606A1 of the insulating encapsulation 606' and the edges of the first semiconductor die 102A and the second semiconductor die 102B (similar to...). Figure 14A(The arrangement shown). In the package structure PK3, due to the presence of the first recess RC1 and the second recess RC2 located at the edges of the first semiconductor die 102A and the second semiconductor die 102B, the die-to-die bending strength of the first portion 606A1 of the insulating encapsulation 606' can be improved. In this way, the molding crack problem of the insulating encapsulation 606' surrounding the first semiconductor die 102A and the second semiconductor die 102B can be solved.

[0131] Figure 19 This is a schematic cross-sectional view of a package-on-package (PoP) structure according to some embodiments of this disclosure. Reference Figure 19 In manufacturing Figure 18 Following the shown package structure PK3, a second package 700 can be stacked on top of package structure PK3 (the first package) to form a stacked package (PoP) structure. For example... Figure 19 As shown, the second package 700 is disposed on the package structure PK3 and electrically connected to the conductive terminal 622 of the package structure PK3.

[0132] In some embodiments, the second package 700 has a substrate 710 and a plurality of semiconductor chips 720 mounted on one surface (e.g., the top surface) of the substrate 710 and stacked on top of each other. In some embodiments, bonding wires 730 are used to provide electrical connections between the semiconductor chips 720 and pads 740 (e.g., bonding pads). In some embodiments, an insulating encapsulation 760 is formed to seal the semiconductor chips 720 and bonding wires 730 to protect these components. In some embodiments, insulator vias (not shown) may be used to provide electrical connections between pads 740 and conductive pads 750 (e.g., bonding pads) located on another surface (e.g., the bottom surface) of the substrate 710. In embodiments, conductive pads 750 are electrically connected to the semiconductor chips 720 through these insulator vias (not shown). In some embodiments, the conductive pads 750 of the package structure 700 are electrically connected to conductive terminals 622 of the package structure PK3. In some embodiments, an underfill adhesive 770 is also provided to fill the space between the package structure PK3 and the second package 700 to surround and protect the conductive terminals 622. After stacking the second package 700 on the package structure PK3 (the first package) and providing electrical connection between the two, the stacked package structure POP1 can be manufactured.

[0133] exist Figure 19In the stacked package structure POP1 shown, the presence of the first recess RC1 and the second recess RC2 located at the edges of the first semiconductor die 102A and the second semiconductor die 102B improves the die-to-die bending strength of the first portion 204A1 of the insulating encapsulation 204'. This solves the molding crack problem of the insulating encapsulation 606' surrounding the first semiconductor die 102A and the second semiconductor die 102B.

[0134] Figure 20 This is a schematic cross-sectional view of a stacked package (PoP) structure according to some other embodiments of this disclosure. Figure 20 The stacked packaging structure PoP2 shown is... Figure 19 The stacked package structure shown is similar to PoP1. Therefore, the same component symbols will be used to represent the same or similar parts, and will not be described in detail again here. The difference between the embodiments is that, Figure 20 In the stacked package structure PoP2 shown, the second portion 606A2 of the insulating encapsulator 606' further includes a third recessed portion RC3 and a fourth recessed portion RC4. For example, the third recessed portion RC3 and the fourth recessed portion RC4 can be formed by removing the die bonding film 104 in a manner similar to the first recessed portion RC1 and the second recessed portion RC2. In some embodiments, the third recessed portion RC3 is located at the edge of the first semiconductor die 102A and is disposed opposite to the first recessed portion RC1. Furthermore, the fourth recessed portion RC4 is located at the edge of the second semiconductor die 102B and is disposed opposite to the second recessed portion RC2.

[0135] exist Figure 20 In the stacked package structure PoP2 shown, the presence of the first recess RC1 and the second recess RC2 located at the edges of the first semiconductor die 102A and the second semiconductor die 102B improves the die-to-die bending strength of the first portion 204A1 of the insulating encapsulation 204'. This solves the molding crack problem of the insulating encapsulation 204' surrounding the first semiconductor die 102A and the second semiconductor die 102B.

[0136] In the above embodiments, the packaging structure includes an insulating encapsulation having a first recess and a second recess located at the edges of the first semiconductor die and the second semiconductor die. This improves the die-to-die bending strength of the first portion of the insulating encapsulation compared to an insulating encapsulation with a flat surface formed between two adjacent dies. Furthermore, it solves the molding cracking problem of the insulating encapsulation encapsulating the first and second semiconductor dies.

[0137] According to some embodiments disclosed herein, the package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulator, and a redistribution layer. The insulating encapsulator laterally surrounds the first and second semiconductor dies, wherein the insulating encapsulator includes a first portion sandwiched between the first and second semiconductor dies, the first portion having a first recess adjacent to an edge of the first semiconductor die and a second recess adjacent to an edge of the second semiconductor die. The redistribution layer is disposed on the first and second semiconductor dies and electrically connected to the first and second semiconductor dies.

[0138] In some embodiments, the package structure further includes a bridging structure and a second insulating encapsulation. The bridging structure is disposed on the first semiconductor die and the second semiconductor die, and electrically connected to the first semiconductor die, the second semiconductor die, and the redistribution layer. The second insulating encapsulation laterally surrounds the bridging structure. In some embodiments, the package structure further includes a first conductive component, a second conductive component, and a via. The first conductive component is disposed on the first semiconductor die and the second semiconductor die, and electrically connects the first semiconductor die and the second semiconductor die to the bridging structure. The second conductive component is disposed on the first semiconductor die and the second semiconductor die. The via is disposed on the second conductive component and electrically connects the second conductive component to the redistribution layer. In some embodiments, the first semiconductor die and the second semiconductor die are spaced apart by a first distance, and the first distance is in the range of 100 μm to 200 μm. In some embodiments, the depth of the first recess and the depth of the second recess are in the range of 1 μm to 10 μm. In some embodiments, the depth of the first recess is different from the depth of the second recess. In some embodiments, a first portion of the insulating encapsulation further includes a protrusion located between the first recess and the second recess. In some embodiments, the packaging structure further includes a thermal interface material disposed on the back sides of the first semiconductor die and the second semiconductor die, wherein the thermal interface material fills the first recess and the second recess. In some embodiments, the thermal interface material partially fills the first recess and completely fills the second recess.

[0139] According to some other embodiments disclosed herein, the package structure includes two semiconductor dies, an insulating encapsulator, a thermal interface material, and a bridging structure. A first portion of the insulating encapsulator is disposed between the two semiconductor chips, wherein a first surface of the first portion is a flat surface, and a second surface opposite to the first surface of the first portion has a protrusion. A second portion of the insulating encapsulator surrounds the first portion and the two semiconductor chips, wherein a third surface and a fourth surface opposite to the third surface of the second portion are flat surfaces. The thermal interface material is disposed on the back surfaces of the two semiconductor dies. The bridging structure overlaps with portions of the two semiconductor dies and electrically connects the two semiconductor dies to each other.

[0140] In some embodiments, a thermal interface material partially covers the side surfaces of the two semiconductor dies and contacts the protrusion of the first portion. In some embodiments, the package structure further includes an air gap between the protrusion of the first portion of the insulating encapsulation and the edges of the two semiconductor dies. In some embodiments, the height of the protrusion of the first portion is in the range of 1 μm to 10 μm. In some embodiments, the package structure further includes a redistribution layer, a circuit substrate, and a cap structure. The redistribution layer is disposed on the bridging structure and electrically connected to the bridging structure and the two semiconductor dies. The circuit substrate is disposed above the redistribution layer and electrically connected to the redistribution layer. The cap structure is disposed on the circuit substrate, wherein the cap structure covers the two semiconductor dies and the bridging structure and contacts the thermal interface material. In some embodiments, the maximum width of the first portion of the insulating encapsulation is 100 μm to 200 μm.

[0141] According to another embodiment of this disclosure, a method for manufacturing a package structure is described. The method includes the following steps: Providing a semiconductor wafer. Providing a die bonding film over the semiconductor wafer. Slicing the semiconductor chip together with the die bonding film to form a first semiconductor die and a second semiconductor die, the first and second semiconductor dies having die bonding films attached to their back surfaces. Placing the first and second semiconductor dies on a carrier. Forming an insulating encapsulation laterally surrounding the first and second semiconductor dies and the die bonding film. Forming a redistribution layer disposed on and electrically connected to the first and second semiconductor dies. Peeling off the carrier and removing the die bonding film attached to the back surfaces of the first and second semiconductor dies. After removing the die bonding film, a first portion of the insulating encapsulation sandwiched between the first and second semiconductor dies forms a first recess adjacent to the edge of the first semiconductor die and a second recess adjacent to the edge of the second semiconductor die.

[0142] In some embodiments, the method further includes: forming a bridging structure on a first semiconductor die and a second semiconductor die, and electrically connecting the bridging structure to the first semiconductor die and the second semiconductor die; and forming a redistribution layer on the bridging structure, and electrically connecting the redistribution layer to the bridging structure. In some embodiments, the depth of the first recess and the second recess is in the range of 1 μm to 10 μm. In some embodiments, after removing the die bonding film, a first portion of the insulating encapsulation has a protrusion located between the first recess and the second recess. In some embodiments, the method further includes forming a thermal interface material on the back side of the first semiconductor die and the second semiconductor die, wherein the thermal interface material is filled into the first recess and the second recess.

[0143] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A packaging structure, comprising: First semiconductor die and second semiconductor die; An insulating encapsulation laterally surrounds the first semiconductor die and the second semiconductor die, wherein the insulating encapsulation includes a first portion sandwiched between the first semiconductor die and the second semiconductor die, the first portion having a first recess adjacent to the edge of the first semiconductor die and a second recess adjacent to the edge of the second semiconductor die; as well as A redistribution layer is disposed on the first semiconductor die and the second semiconductor die and is electrically connected to the first semiconductor die and the second semiconductor die.

2. The packaging structure according to claim 1, further comprising: A bridging structure is disposed on the first semiconductor die and the second semiconductor die, and is electrically connected to the first semiconductor die, the second semiconductor die and the redistribution layer; as well as A second insulating encapsulation is laterally wrapped around the bridging structure.

3. The packaging structure according to claim 2, further comprising: A first conductive component is disposed on the first semiconductor die and the second semiconductor die, and electrically connects the first semiconductor die and the second semiconductor die to the bridging structure; A second conductive component is disposed on the first semiconductor die and the second semiconductor die; as well as A through-hole is provided on the second conductive component and electrically connects the second conductive component to the redistribution layer.

4. The packaging structure according to claim 1, wherein the first semiconductor die and the second semiconductor die are spaced apart by a first distance, and the first distance is in the range of 100 μm to 200 μm.

5. The packaging structure according to claim 1, wherein, The depths of the first recess and the second recess are in the range of 1 μm to 10 μm.

6. A packaging structure, comprising: Two semiconductor dies; A first portion of an insulating encapsulation is disposed between the two semiconductor dies, wherein a first surface of the first portion is a flat surface, and a second surface opposite to the first surface of the first portion has a protrusion; The second portion of the insulating encapsulation surrounds the first portion and the two semiconductor dies, wherein the third surface of the second portion and the fourth surface opposite to the third surface are flat surfaces; A thermal interface material is disposed on the back side of the two semiconductor dies; as well as A bridging structure overlaps with the two semiconductor dies and electrically connects the two semiconductor dies to each other.

7. The packaging structure of claim 6, wherein the thermal interface material partially covers the side surfaces of the two semiconductor dies, and the thermal interface material contacts the protrusion of the first portion.

8. The packaging structure according to claim 6 further includes an air gap located between the protrusion of the first portion of the insulating encapsulation and the edges of the two semiconductor dies.

9. The packaging structure according to claim 6, wherein the height of the protrusion in the first portion is in the range of 1 μm to 10 μm.

10. The packaging structure according to claim 6, further comprising: A redistribution layer is disposed on the bridging structure and electrically connected to the bridging structure and the two semiconductor dies; A circuit substrate is disposed above the redistribution layer and electrically connected to the redistribution layer; as well as A cover structure is disposed on the circuit substrate, wherein the cover structure covers the two semiconductor dies and the bridging structure, and is in contact with the thermal interface material.

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