Semiconductor device and semiconductor apparatus

Abstract

A semiconductor device and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor device, an integrated cooling structure, a second semiconductor device and a plurality of substrate via holes. The first semiconductor device includes a first interconnect structure. An integrated cooling structure is bonded to the first interconnect structure, wherein the integrated cooling structure is configured for a working fluid to enter and exit the integrated cooling structure. The second semiconductor device includes a second interconnect structure, and the second semiconductor device is bonded to the integrated cooling structure relative to the first interconnect structure. A plurality of substrate vias extend through the integrated cooling structure, wherein the substrate vias electrically couple the first semiconductor device to the second semiconductor device.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor devices and semiconductor equipment. Background Technology

[0002] In wafer-to-wafer bonding technology, various methods have been developed to bond two packaged components (e.g., wafers) together. Available bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, and similar methods. In fusion bonding, the oxide surface of one wafer is bonded to the oxide surface or silicon surface of another wafer. In eutectic bonding, two eutectic materials are placed together and subjected to high pressure and high temperature. Therefore, the eutectic materials are molten. When the molten eutectic material solidifies, the wafers are bonded together. In direct metal-to-metal bonding, two metal spacers are pressed against each other at elevated temperatures, and the mutual diffusion of the metal spacers leads to bonding. In hybrid bonding, the metal spacers of two wafers are bonded to each other via direct metal-to-metal bonding, and the oxide surface of one wafer is bonded to the oxide surface or silicon surface of the other wafer. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor device and semiconductor equipment to solve at least one of the above-mentioned problems.

[0004] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor device, an integrated cooling structure, a second semiconductor device, and a plurality of substrate vias. The first semiconductor device includes a first interconnect structure. The integrated cooling structure is coupled to the first interconnect structure, wherein the integrated cooling structure is configured to allow working fluid to enter and exit the integrated cooling structure. The second semiconductor device includes a second interconnect structure, and the second semiconductor device is coupled to the integrated cooling structure relative to the first interconnect structure. The plurality of substrate vias extend through the integrated cooling structure, wherein the substrate vias electrically couple the first semiconductor device to the second semiconductor device.

[0005] According to one embodiment of the present invention, the integrated cooling structure includes a water inlet port and a water outlet port, and both the water inlet port and the water outlet port are connected to a cavity within the integrated cooling structure.

[0006] According to one embodiment of the present invention, it further includes: an external pump; a water inlet pipe, a first side of which is attached to the external pump and a second side of which is attached to the water inlet port, wherein the water inlet pipe contains the working fluid; and a water outlet pipe, a first side of which is attached to the water outlet port and a second side of which is attached to the external pump, wherein the water outlet pipe contains the working fluid.

[0007] According to one embodiment of the present invention, the integrated cooling structure includes: a cavity configured to allow the working fluid to flow through the cavity; and a plurality of micropillars extending from a first side of the cavity to a second side of the cavity, wherein the plurality of micropillars are configured to obstruct the flow of the working fluid through the cavity.

[0008] According to one embodiment of the present invention, a first subset of the plurality of micropillars does not have the plurality of substrate vias, and a second subset of the plurality of micropillars each surrounds one of the plurality of substrate vias.

[0009] According to one embodiment of the present invention, the plurality of micropillars have a teardrop-shaped cross-section in a top view.

[0010] According to one embodiment of the present invention, the distance between each of the plurality of micropillars in the cavity is different.

[0011] According to one embodiment of the present invention, the plurality of micropillars within the cavity have a first diameter, wherein the first diameter is between 100 micrometers and 800 micrometers.

[0012] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor package, a pump system, and a liquid coolant. The first semiconductor package includes a first semiconductor device, a second semiconductor device, and an integrated micro-cooling structure. The integrated micro-cooling structure is disposed between the first semiconductor device and the second semiconductor device. The pump system is attached to the first semiconductor package and includes a pump, a first conduit, and a second conduit. A first side of the first conduit is attached to the pump, and a second side of the first conduit is attached to the integrated micro-cooling structure. A first side of the second conduit is attached to the integrated micro-cooling structure, and a second side of the second conduit is attached to the pump. The liquid coolant is contained within cavities within the pump system and the integrated micro-cooling structure. Attached Figure Description

[0013] The embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of this utility model.

[0014] Figure 1 According to some embodiments, a first bonding layer is formed on a first semiconductor device.

[0015] Figure 2 According to some embodiments, the bonding of a first cooling layer structure to a first semiconductor device is shown.

[0016] Figure 3 According to some embodiments, the formation of a first perforation within a first cooling layer structure is shown.

[0017] Figure 4A According to some embodiments, the formation of cavities and micropillars within the first cooling layer structure is shown.

[0018] Figure 4B According to some embodiments, a cross-sectional view of the cavity and micropillars within the first cooling layer structure is shown.

[0019] Figure 5 According to some embodiments, the joining of the second cooling layer structure and the first cooling layer structure is shown.

[0020] Figure 6 According to some embodiments, the formation of an opening through the second cooling layer structure into a cavity within the first cooling layer structure is shown.

[0021] Figure 7 According to some embodiments, the bonding of a second semiconductor device with a second cooling layer structure is shown.

[0022] Figure 8A According to some embodiments, it is shown that coolant is introduced into the cavity.

[0023] Figure 8B According to some embodiments, a cross-sectional view of a cavity is shown, in which coolant in the cavity surrounds perforations within the micropillar.

[0024] Figures 9 to 10 According to some embodiments, the formation of a semiconductor package is shown, wherein the semiconductor package has a through-hole formed after a first cooling layer structure is bonded to a second cooling layer structure.

[0025] The attached figures are labeled as follows:

[0026] 100: First semiconductor device

[0027] 101: Metallized Pattern

[0028] 103: Perforation

[0029] 105: First substrate

[0030] 107: Interconnection Structure

[0031] 109: First dielectric layer

[0032] 111: First conductive connector

[0033] 120: First bonding layer

[0034] 200: First cooling structure layer

[0035] 201: First cooling structure substrate

[0036] 203: Second dielectric layer

[0037] 205: Second conductive connector

[0038] 220: Second bonding layer

[0039] 301: First substrate via

[0040] 303: Third dielectric layer

[0041] 305: Third conductive connector

[0042] 320: Third bonding layer

[0043] 400: Cavity

[0044] 401: Microcolumn

[0045] 450: Removal process

[0046] 500: Second cooling structure layer

[0047] 501: Second cooling structure substrate

[0048] 503: Fourth dielectric layer

[0049] 505: Fourth conductive connector

[0050] 507: Second substrate via

[0051] 520: Fourth bonding layer

[0052] 550: IMC Structure

[0053] 603: Fifth dielectric layer

[0054] 605: Fifth conductive connector

[0055] 620: Fifth bonding layer

[0056] 650: Second removal process

[0057] 651: Water inlet port

[0058] 653: Water outlet port

[0059] 700: Second Semiconductor Device

[0060] 701: Metallized Pattern

[0061] 703: Perforation

[0062] 705: Second substrate

[0063] 707: Second interconnect structure

[0064] 709: Sixth dielectric layer

[0065] 711: Sixth conductive connector

[0066] 720: Sixth bonding layer

[0067] 750: First semiconductor package 800: Coolant system

[0068] 801: Working fluid

[0069] 803: External Pump

[0070] 805:Water inlet pipe

[0071] 807: Water outlet pipe

[0072] 850: Flow Profile

[0073] 901: First Hole

[0074] 1001: Third substrate via

[0075] D1: Depth

[0076] D2: Second Depth

[0077] First diameter

[0078] P1: First pitch Detailed Implementation

[0079] The following utility model provides different embodiments or examples for implementing different components of the provided object. Specific examples of each component and its configuration are described below to simplify the description of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, if the description mentions that a first component is formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that they are not in direct contact. Furthermore, this utility model may repeat element symbols and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0080] This document may use spatial relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” etc., to describe the relationship between one or more elements or components in the accompanying drawings and to one or more other elements or components. Spatial relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatial relative descriptions used herein may also be interpreted according to the orientation after the turn.

[0081] Embodiments of this invention advantageously provide an integrated micro-cooling (IMC) structure within a package such as a system-on-integrated-chip (SoIC) package or a 3D integrated-chip (3DIC) package to provide improved cooling. Furthermore, the IMC structure can utilize a turbulent flow of the working fluid (e.g., a coolant) to allow for increased temperature absorption and a faster rate of thermal conduction, thereby more effectively removing heat from the package.

[0082] Figure 1A first semiconductor device 100 with a metallization pattern 101 and a through-hole 103 is shown. In some embodiments, the first semiconductor device 100 may be a high bandwidth memory (HBM) module, xPU, logic die, CPU, GPU, SoC die, MEMS die, logic device, complementary metal oxide semiconductor (CMOS) device, micro-electro-mechanical system (MEMS) device, integrated passive device (IPD), driver, or memory device element, such as, but not limited to, memory cells including, static random access memory (SRAM), dynamic random access memory (DRAM), magneto-resistive random access memory (MRAM), and the like. The first semiconductor device 100 may include other types of devices, combinations thereof, or the like. Any suitable device with any suitable function may be used, and it is entirely intended that all such devices be included between embodiments. Although Figure 1 Only one layer of metallization pattern 101 and one layer of via 103 are shown, but it should be understood that the first semiconductor device 100 may include more than one layer of metallization pattern 101 and more than one layer of via 103.

[0083] In one embodiment, the first semiconductor device 100 includes a first substrate 105, which may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a silicon-carbon substrate, a III-V compound semiconductor substrate, or the like. A device region (not shown separately) is formed on or within the first substrate 105. The device region may include active or passive devices, such as transistors, resistors, capacitors, diodes, and the like. In some embodiments, the device region may include a package die (not shown separately).

[0084] In some embodiments, interconnect structure 107 can be used to electrically connect various active and passive devices. Interconnect structure 107 may include insulating layers (not shown separately) and conductive components (e.g., metallization pattern 101 and vias 103) formed in alternating layers on the first substrate 105 using any suitable method, wherein the insulating layers are such as inter-layer dielectrics (ILDs) and / or inter-metal dielectric layers (IMDs). Interconnect structure 107 can connect various active and / or passive devices in the device region of the first substrate 105 to form functional circuitry. The insulating layers may include low-k dielectric materials having, for example, a dielectric constant (k value) below about 4.0 or even 2.8.

[0085] In some embodiments, the interconnect structure 107 includes one or more layers of conductive routing (e.g., metallization pattern 101 and / or vias 103) formed on the first substrate 105. The conductive routing may be formed from one or more conductive layers of a dielectric (e.g., a low-k dielectric material) material having interconnect conductor layers. For example, the conductive routing may include one to three layers of conductors. In other embodiments, the conductive routing may include conductors of different numbers of layers. Vias may extend through the dielectric to provide vertical connections between conductor layers. The conductive routing may be formed by any suitable process, such as deposition, damascene, dual damascene, etc.

[0086] In some embodiments, a damascene process is used to form conductive routes, wherein photolithography is used to pattern and etch corresponding dielectric layers to form trenches corresponding to desired patterns of metallization layers and / or vias. Optional diffusion barrier layers and / or optional adhesive layers may be deposited, and the trenches may be filled with conductive materials. Suitable materials for barrier layers include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives, and suitable materials for conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In one embodiment, the metallization layer may be formed by depositing a seed layer of copper or a copper alloy and filling the trenches by electroplating. Chemical mechanical planarization (CMP) processes or similar methods may be used to remove excess conductive material from the surface of the corresponding dielectric layer and planarize the surface for subsequent processes.

[0087] In some embodiments, damascene or dual-damascene processes can be used to form conductive routes with a smaller pitch (e.g., "fine-pitch routing"), which can increase the density of conductive routes and also allow for improved conduction and connection reliability within the interconnect structure 107. Fine-pitch routing can have a smaller surface roughness than other types of routing, and therefore can reduce the resistance experienced by high-speed signals and also reduce signal loss (e.g., insertion loss) during high-speed operation.

[0088] Figure 1 A first bonding layer 120 formed on the interconnect structure 107 is further illustrated. In one embodiment, a first dielectric layer 109 is formed on the interconnect structure 107. Acceptable dielectric materials for the first dielectric layer 109 may include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. The first dielectric layer 109 may be formed by spin coating, lamination, chemical vapor deposition (CVD), or similar methods. The first dielectric layer 109 is then patterned using, for example, photolithography and etching processes, or any suitable patterning process may be used. Openings (not shown separately) are patterned to expose conductive portions of the interconnect structure 107. In one embodiment, a conductive material is formed in the openings and over the first dielectric layer 109. As an example of forming a conductive material, a seed layer (not shown separately) may be formed over the first dielectric layer 109 and in the openings extending through the first dielectric layer 109. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD). A conductive material may then be formed on the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc.

[0089] In one embodiment, the first conductive connector 111 is formed from the conductive material in the opening. In another embodiment, the first conductive connector 111 is formed by removing excess conductive material from the surface of the first dielectric layer 109 using a planarization process such as chemical-mechanical polishing (CMP), wherein the remaining conductive material in the opening of the first dielectric layer 109 forms the first conductive connector 111. The first conductive connector 111 provides electrical contacts for external connections to the interconnect structure 107, allowing an integrated circuit device to be electrically coupled to the aforementioned interconnect structure 107. In one embodiment, the first dielectric layer 109 and the first conductive connector 111 form a first bonding layer 120 for bonding subsequent structures.

[0090] Figure 2 The bonding between the first cooling structure layer 200 and the first semiconductor device 100 is illustrated. In one embodiment, the first cooling structure layer 200 may include a first cooling structure substrate 201. In one embodiment, the first cooling structure substrate 201 may be formed of a silicon material. The silicon material may include silicon (e.g., bulk silicon), silicon carbide, silicon oxide, silicon nitride, etc., or combinations thereof, such as silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and the like.

[0091] In one embodiment, a second bonding layer 220 may be formed on the first cooling structure substrate 201. In one embodiment, the second bonding layer 220 may include a second dielectric layer 203 and a second conductive connector 205. The second bonding layer 220, including the second dielectric layer 203 and the second conductive connector 205, may be formed using similar methods and materials as those used to form the first bonding layer 120, wherein the methods include forming the first dielectric layer 109 and forming the first conductive connector 111. However, any suitable process and materials may be used to form the second bonding layer 220.

[0092] In one embodiment, a first cooling structure substrate 201 and a second bonding layer 220 formed on the first cooling structure substrate 201 are flip-up, and the second bonding layer 220 can be positioned to contact the first bonding layer 120. The second bonding layer 220 can be bonded to the first bonding layer 120 by dielectric-to-dielectric and metal-to-metal bonding processes performed between the second bonding layer 220 and the first bonding layer 120. In some embodiments, dielectric-to-dielectric bonding forms a direct bond (e.g., fusion bonding, such as oxide-to-oxide bonding) between the first dielectric layer 109 and the second dielectric layer 203. Alternatively, metal-to-metal bonding processes can directly bond the first conductive connector 111 of the first bonding layer 120 and the second conductive connector 205 of the second bonding layer 220 via direct metal-to-metal bonding. The dielectric-to-dielectric bonding process may begin by applying a surface treatment to either or both of the first dielectric layer 109 and the second dielectric layer 203 to facilitate dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding) between the first dielectric layer 109 and the second dielectric layer 203. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. Following the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water or a similar method) applicable to either or both of the first dielectric layer 109 and the second dielectric layer 203. Next, a dielectric-to-dielectric and metal-to-metal bonding process may proceed to align the second conductive connector 205 of the second bonding layer 220 with the first conductive connector 111 of the first bonding layer 120. The dielectric-to-dielectric and metal-to-metal bonding process then includes a pre-bonding step during which the second bonding layer 220 is brought into contact with the first bonding layer 120. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). Annealing is performed in the dielectric-to-dielectric and metal-to-metal bonding processes, such as at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the first conductive connector 111 (e.g., copper) and the second conductive connector 205 (e.g., copper) diffuse into each other, thereby forming a direct metal-to-metal bond, thereby bonding the first cooling structure layer 200 to the first semiconductor device 100.

[0093] Figure 3The formation of a first substrate via (TSV) 301 through a first cooling structure substrate 201 is illustrated. In one embodiment, the first TSV 301 can be formed by initially forming a TSV opening (not shown separately) in the first cooling structure substrate 201. The TSV opening can be formed by applying and developing a suitable photoresist (not shown) and etching the exposed portion of the first cooling structure substrate 201 to a desired depth. Once the TSV opening is formed within the first cooling structure substrate 201, it can be lined with a liner. The liner can be, for example, an oxide formed from tetraethylorthosilicate (TEOS) or silicon nitride, but any suitable dielectric material can also be used alternatively. A plasma-enhanced chemical vapor deposition (PECVD) process can be used to form the liner, but other suitable processes such as physical vapor deposition or thermal processes can also be used alternatively.

[0094] Once the liner has been formed along the sidewalls and bottom of the TSV opening, a barrier layer (not shown separately) can be formed, and the remainder of the TSV opening can be filled with a conductive material. The conductive material may include copper, but other suitable materials may also be used, such as aluminum, alloys, doped polysilicon, combinations thereof, or the like. The conductive material can be formed by electroplating copper onto a seed layer (not shown separately), filling, and overfilling the TSV opening. Once the TSV opening is filled, excess liner, barrier layer, seed layer, and conductive material outside the TSV opening can be removed using a planarization process such as chemical mechanical polishing (CMP) to form the first TSV 301, but any suitable removal process may be used.

[0095] Figure 3The formation of a third bonding layer 320 is also illustrated. The third bonding layer 320 may be formed on the first cooling structure substrate 201, and may include a third dielectric layer 303 and a third conductive connector 305. In one embodiment, the third dielectric layer 303 and the third conductive connector 305 may be formed using a similar manner and from similar materials as the first dielectric layer 109 or the second dielectric layer 203 and the first conductive connector 111 or the second conductive connector 205. In this embodiment, the third conductive connector 305 is formed in an opening on the first TSV 301 for physical and electrical coupling to the first TSV 301. In an alternative embodiment, the third bonding layer 320 is formed by forming the third dielectric layer 303 on the first cooling structure substrate 201 prior to forming the first TSV 301. In this embodiment, an opening is formed through both the third dielectric layer 303 and the first cooling structure substrate 201, and then the first TSV 301 is formed in a manner similar to that described above, but the first TSV 301 extends through the third dielectric layer 303.

[0096] Figure 4A and Figure 4B The formation of a cavity 400 in the first cooling structure layer 200 is illustrated. In one embodiment, the cavity 400 in the first cooling structure layer 200 is formed by forming micropillars 401 within the first cooling structure layer 200 from the remaining material of the first cooling structure substrate 201. In one embodiment, the cavity 400 can be formed by a removal process 450, which removes material from the first cooling structure substrate 201 and from the third dielectric layer 303. The step of removing material from the first cooling structure substrate 201 and the third dielectric layer 303 forms the cavity 400 within the first cooling structure layer 200, wherein the remaining portion of the material of the first cooling structure substrate 201 protrudes into the cavity 400 to form the micropillars 401.

[0097] In one embodiment, the removal process 450 may be an etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar methods, or combinations thereof. The etching process may be anisotropic. In one embodiment, the pattern of the micropillars 401 may be formed during the removal process 450 by any suitable method. For example, one or more photolithography processes may be used to mask areas of the first cooling structure substrate 201 that are not removed during the removal process 450 to form the micropillars 401. In another embodiment, the cavity 400 and the micropillars 401 may be formed by the removal process 450, wherein the removal process 450 is a mechanical removal process, such as a drilling process. However, any suitable process may be used in the removal process 450 to form the cavity 400 and the micropillars 401.

[0098] In one embodiment, removal process 450 forms micropillars 401, which serve to provide multiple functions within cavity 400. A first subset of micropillars 401 includes a first TSV 301, and a second subset of micropillars 401 does not include the first TSV 301. In one embodiment, micropillars 401 may provide structural support for a first cooling structure layer 200 within cavity 400. In one embodiment, micropillars 401 provide obstruction to the flow of subsequently inserted working fluid 801 (e.g., liquid coolant), allowing the working fluid 801 to have turbulence. In one embodiment, micropillars 401 provide structural support for the first TSV 301 and physical isolation of the working fluid 801 as it passes through cavity 400 in first cooling structure layer 200.

[0099] In one embodiment, the cavity 400 extends to a depth D1 in the first cooling structure layer 200. In some embodiments, the depth D1 may be between 100 micrometers and 500 micrometers. In this embodiment, turbulence of the subsequently inserted working fluid 801 (discussed in more detail below with reference to FIG8) can be achieved using a standard power pump (discussed in more detail below with reference to FIG8), wherein the first depth D1 is 100 micrometers or greater. If the first depth D1 is greater than 500 micrometers, the first semiconductor device 100 and the subsequently attached device (e.g., Figure 7 The distance between the second semiconductor device 700 shown may be too large, and the signal degradation between the first semiconductor device 100 and the second semiconductor device 700 may be insufficient. In other embodiments, the depth D1 may be between 50 micrometers and 500 micrometers. In this embodiment, turbulence of the subsequently inserted working fluid 801 can be achieved using a high-power pump (discussed in more detail below with reference to FIG8), where the second depth D2 is 50 micrometers or greater. If the second depth D2 is greater than 500 micrometers, the distance between the first semiconductor device 100 and the subsequently attached device (e.g., Figure 7 The distance between the second semiconductor device 700 shown may be too large, and the signal attenuation between the first semiconductor device 100 and the second semiconductor device 700 may be insufficient.

[0100] Figure 4B It shows Figure 4AThe diagram shows a cross-sectional view of the first cooling structure layer 200 at the cavity 400. In one embodiment, the micropillars 401 can be arranged in an organized array (e.g., each of the micropillars has a consistent pitch) of a first subset of the micropillars 401 surrounding the first TSV 301 and a second subset of the micropillars 401 excluding the first TSV 301. In an alternative embodiment, the micropillars 401 may be arranged in a non-organized and possibly non-uniform distribution. For example, the pitch between each of the micropillars 401 may vary. Furthermore, in one embodiment, the micropillars 401 are shown formed with a circular cross-section; however, this is merely illustrative and the micropillars 401 can be formed with any suitable cross-section shape, such as square, rectangular, teardrop shape, similar shapes, or combinations thereof.

[0101] Micropillar 401 can be formed into a first diameter The first diameter The cross-sectional area can be between 100 micrometers and 800 micrometers. Alternatively, in one embodiment, the micropillar 401 can be formed with a cross-sectional area between 7,850 square micrometers and 502,000 square micrometers. If the cross-sectional area is below this range, the micropillar 401 may not be large enough to provide structural support for the first cooling structure layer 200 within the cavity 400 and impede the flow of the working fluid 801, or to provide structural support and physical isolation for the first TSV 301 when the working fluid 801 passes through the cavity 400 in the first cooling structure layer 200. If the cross-sectional area is above this range, the micropillar 401 may excessively occupy space within the cavity 400, resulting in excessive impediment to the flow of the working fluid 801 within the cavity 400, which may lead to unintended pressure being applied to the external pump 803 (discussed in more detail below with reference to FIG8). In one embodiment, the micropillar 401 has a first pitch P1, wherein the first pitch P1 can be between 200 micrometers and 600 micrometers. If the pitch between the micropillars 401 is less than the first pitch P1, the flow of the working fluid 801 may be excessively restricted. If the pitch between the micropillars 401 is greater than the first pitch P1, the micropillars may not contribute to the turbulence of the working fluid 801 through the cavity 400 or provide sufficient structural support for the first cooling structure layer 200.

[0102] Figure 5The bonding between the second cooling structure layer 500 and the first cooling structure layer 200 is illustrated. In one embodiment, the second cooling structure layer 500 may include a second cooling structure substrate 501. In one embodiment, the second cooling structure substrate 501 may be formed of a silicon material. The silicon material may include silicon (e.g., bulk silicon), silicon carbide, silicon oxide, silicon nitride, the likes thereof, or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, or the likes thereof.

[0103] In one embodiment, a fourth bonding layer 520 may be formed on the second cooling structure substrate 501. In one embodiment, the fourth bonding layer 520 may include a fourth dielectric layer 503 and a fourth conductive connector 505. The fourth bonding layer 520, including the fourth dielectric layer 503 and the fourth conductive connector 505, may be formed using similar methods and materials as those used to form the third bonding layer 320, wherein the methods include forming the third dielectric layer 303 and forming the third conductive connector 305. However, any suitable process and materials may be used to form the fourth bonding layer 520.

[0104] In one embodiment, the second cooling structure substrate 501 and the fourth bonding layer 520 formed on the second cooling structure substrate 501 are flippable, and the fourth bonding layer 520 can be positioned to contact the third bonding layer 320. The fourth bonding layer 520 can be bonded to the third bonding layer 320 by dielectric-to-dielectric and metal-to-metal bonding processes performed between the fourth bonding layer 520 and the third bonding layer 320. In some embodiments, the dielectric-to-dielectric bonding process forms a direct bond (e.g., fusion bonding, such as oxide-to-oxide bonding) between the third dielectric layer 303 and the fourth dielectric layer 503. Alternatively, the metal-to-metal bonding process can directly bond the third conductive connector 305 of the third bonding layer 320 to the fourth conductive connector 505 of the fourth bonding layer 520 via direct metal-to-metal bonding. In an alternative embodiment, the metal-to-metal bonding process can directly bond the four conductive connectors to the first TSV 301, and the third conductive connector 305 can be omitted. The dielectric-to-dielectric bonding process may begin by applying a surface treatment to either or both of the third dielectric layer 303 and the fourth dielectric layer 503 to facilitate dielectric-to-dielectric bonding (such as oxide-to-oxide bonding) between the third dielectric layer 303 and the fourth dielectric layer 503. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. Following the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water or a similar method) that can be applied to either or both of the third dielectric layer 303 and the fourth dielectric layer 503. Next, the dielectric-to-dielectric and metal-to-metal bonding process may continue to align the fourth conductive connector 505 of the fourth bonding layer 520 with the third conductive connector 305 of the third bonding layer 320 or with the first TSV 301. The dielectric-to-dielectric and metal-to-metal bonding process then includes a pre-bonding step during which the third bonding layer 320 is brought into contact with the fourth bonding layer 520. Pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). Annealing is then performed on dielectric-to-dielectric and metal-to-metal bonding processes, such as at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the fourth conductive connector 505 (e.g., copper) diffuses with the third conductive connector 305 (e.g., copper) or the first TSV 301, thereby forming a direct metal-to-metal bond, thereby bonding the first cooling structure layer 200 to the second cooling structure layer 500.

[0105] Figure 5The formation of a second TSV 507 through the second cooling structure substrate 501 is also illustrated. In one embodiment, the second TSV 507 can be formed by initially forming a TSV opening (not shown separately) in the second cooling structure substrate 501. The TSV opening can be formed by applying and developing a suitable photoresist (not shown) and removing the exposed portion of the second cooling structure substrate 501 to a desired depth. Once the TSV opening is formed within the second cooling structure substrate 501, it can be lined with a substrate. The substrate can be, for example, an oxide formed from tetraethoxysilane (TEOS) or silicon nitride, but any suitable dielectric material can also be used alternatively. A plasma-assisted chemical vapor deposition (PECVD) process can be used to form the substrate, but other suitable processes such as physical vapor deposition or thermal processes can also be used alternatively.

[0106] Once the liner is formed along the sidewalls and bottom of the TSV opening, a barrier layer (not shown separately) can be formed, and the remainder of the TSV opening can be filled with a conductive material. The conductive material may include copper, but other suitable materials may also be used, such as aluminum, alloys, doped polysilicon, combinations thereof, or the like. The conductive material can be formed by electroplating copper onto a seed layer (not shown separately), filling and overfilling the TSV opening. Once the TSV opening has been filled, excess liner, barrier layer, seed layer, and conductive material outside the TSV opening can be removed by a planarization process such as chemical mechanical polishing (CMP) to form a second TSV 507, but any suitable removal process may be used.

[0107] In one embodiment, after the first cooling structure layer 200 is bonded to the second cooling structure layer 500, the resulting structure including the first cooling structure layer 200, the cavity 400, the micropillars 401, and the second cooling structure layer 500 may be referred to as an integrated micro-cooler (IMC) structure 550. The IMC structure 550 allows working fluid 801 to be introduced into the cavity 400, so that the working fluid 801 can flow between the first semiconductor device 100 and the second semiconductor device 700 to dissipate and remove heat generated from the first semiconductor device 100 and the second semiconductor device 700.

[0108] Figure 6A fifth bonding layer 620 is shown formed over a second cooling structure layer 500. In one embodiment, a fifth dielectric layer 603 is formed over a second cooling structure substrate 501. Acceptable dielectric materials for the fifth dielectric layer 603 may include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon carbonoxynitride, silicon carbonitride, silicon carbonitride, or the like. The fifth dielectric layer 603 may be formed by spin coating, lamination, chemical vapor deposition (CVD), or similar methods. The fifth dielectric layer 603 may then be patterned using, for example, photolithography and etching processes, or any suitable patterning process may be used. The patterning process forms openings (not shown separately). In one embodiment, a conductive material is formed in the openings and over the fifth dielectric layer 603. As an example of forming a conductive material, a seed layer (not shown separately) may be formed over the fifth dielectric layer 603 and in the openings extending through the fifth dielectric layer 603. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using methods such as PVD or similar methods. A conductive material may then be formed on the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like.

[0109] In one embodiment, the fifth conductive connector 605 is formed from the conductive material in the opening. In another embodiment, the fifth conductive connector 605 is formed by removing excess conductive material from the surface of the fifth dielectric layer 603 through a planarization process such as chemical mechanical polishing (CMP), wherein the remaining conductive material in the opening of the fifth dielectric layer 603 forms the fifth conductive connector 605. In one embodiment, the fifth dielectric layer 603 and the fifth conductive connector 605 form a fifth bonding layer 620. Furthermore, in one embodiment, the fifth conductive connector 605 is physically coupled and electrically coupled to the second TSV 507.

[0110] Figure 6A second removal process 650 is also illustrated. In one embodiment, the second removal process 650 may occur after the formation of the fifth bonding layer 620. The second removal process 650 removes material from the second cooling structure substrate 501 and from the fourth dielectric layer 503 to form an inlet port 651 and an outlet port 653, wherein the inlet port 651 and the outlet port 653 provide channels to the cavity 400. In one embodiment, the inlet port 651 and the outlet port 653 are located on opposite sides of the second cooling structure layer 500. The inlet port 651 is shown on the left side of the second cooling structure layer 500, and the outlet port 653 is shown on the right side of the second cooling structure layer 500; this is merely illustrative, and the inlet port 651 and the outlet port 653 may be in any suitable orientation. The second removal process 650 may be an etching process similar to the process described above with respect to removal process 450, or it may be a mechanical process similar to the process described above with respect to removal process 450.

[0111] Figure 7 A second semiconductor device 700 with a metallization pattern 701 and a through-hole 703 is illustrated. In some embodiments, the second semiconductor device 700 may be a high-bandwidth memory (HBM) module, xPU, logic die, CPU, GPU, SoC chip, MEMS die, logic device, complementary metal-oxide-semiconductor (CMOS) device, microelectromechanical system (MEMS) device, integrated passive device (IPD), driver, or memory device, such as a memory cell, including but not limited to static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, magnetoresistive random access memory (MRAM) cells, or the like. The second semiconductor device 700 may include other types of devices, combinations thereof, or the like. Any suitable device with any suitable function may be used, and it is entirely intended that all such devices be included between embodiments.

[0112] In one embodiment, the second semiconductor device 700 includes a second substrate 705, which may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a silicon-carbon substrate, a III-V compound semiconductor substrate, or the like. A device region (not shown separately) is formed on or within the second substrate 705. The device region may include active or passive devices, such as transistors, resistors, capacitors, diodes, and the like. In some embodiments, the device region may include a package die (not shown separately).

[0113] In some embodiments, the second interconnect structure 707 can be used to redistribute connections between various active and passive devices. The second interconnect structure 707 may include insulating layers (not shown separately) formed in alternating layers on the second substrate 705 using any suitable method, and conductive components (e.g., metallization pattern 701 and vias 703), wherein the insulating layers include interlayer dielectrics (ILDs) and / or intermetallic dielectrics (IMDs). The second interconnect structure 707 can connect various active and / or passive devices in the device region of the second substrate 705 to form functional circuitry. The insulating layers may include low-k dielectric materials having, for example, k values ​​below about 4.0 or even 2.8.

[0114] In some embodiments, the second interconnect structure 707 includes one or more conductive routes (e.g., metallization pattern 701 and / or vias 703) formed on the second substrate 705. The conductive routes may be formed from one or more conductive layers of a dielectric (e.g., a low-k dielectric material) material having interconnect conductor layers. For example, the conductive routes may include one to three layers of conductors. In other embodiments, the conductive routes may include conductors of different numbers of layers. The vias may extend through the dielectric to provide vertical connections between conductor layers. The conductive routes may be formed by any suitable process, such as deposition, damascene, dual damascene, etc.

[0115] In some embodiments, a damascene process is used to form conductive routes, wherein a photolithography technique is used to pattern and etch corresponding dielectric layers to form trenches corresponding to desired patterns of metallization layers and / or vias. Optional diffusion barrier layers and / or optional adhesive layers may be deposited, and the trenches may be filled with a conductive material. Suitable materials for the barrier layers include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives, and suitable materials for the conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In one embodiment, the metallization layer may be formed by depositing a seed layer of copper or a copper alloy and filling the trenches by electroplating. Chemical mechanical planarization processes or similar methods may be used to remove excess conductive material from the surface of the corresponding dielectric layer and planarize the surface for subsequent processes.

[0116] In some embodiments, damascene or dual damascene processes can be used to form conductive routes with a smaller pitch (e.g., "detailed pitch routes"), which can increase the density of conductive routes and also allow for improved conduction and connection reliability within the second interconnect structure 707. Detailed pitch routes can have a smaller surface roughness than other types of routes, and therefore can reduce the resistance experienced by high-speed signals and also reduce signal loss (e.g., insertion loss) during high-speed operation.

[0117] Figure 7A sixth bonding layer 720 formed on the second interconnect structure 707 is also shown. In one embodiment, the sixth bonding layer 720 may include a sixth dielectric layer 709 and a sixth conductive connector 711. The sixth bonding layer 720, including the sixth dielectric layer 709 and the sixth conductive connector 711, may be formed using similar methods and materials as those used to form the first bonding layer 120, wherein the methods include forming the first dielectric layer 109 and forming the first conductive connector 111. However, any suitable process and materials may be used to form the sixth dielectric layer 709.

[0118] In one embodiment, the second semiconductor device 700 and the sixth bonding layer 720 are flipped so that the sixth bonding layer 720 faces the fifth bonding layer 620. The sixth bonding layer 720 can be bonded to the fifth bonding layer 620 by performing a dielectric-to-dielectric bonding process and a metal-to-metal bonding process between the sixth bonding layer 720 and the fifth bonding layer 620. In some embodiments, the dielectric-to-dielectric bonding process forms a direct bond (e.g., fusion bonding, such as oxide-to-oxide bonding) between the sixth dielectric layer 709 and the fifth dielectric layer 603. Alternatively, the metal-to-metal bonding process can directly bond the sixth conductive connection 711 of the sixth bonding layer 720 to the fifth conductive connection 605 of the fifth bonding layer 620 via direct metal-to-metal bonding. The dielectric-to-dielectric bonding process may begin by performing a surface treatment on either or both of the sixth dielectric layer 709 and the fifth dielectric layer 603 to facilitate dielectric-to-dielectric bonding (such as oxide-to-oxide bonding) between the sixth dielectric layer 709 and the fifth dielectric layer 603. The surface treatment may include plasma treatment. Plasma treatment can be performed in a vacuum environment. Following plasma treatment, surface treatment may further include a cleaning process (e.g., rinsing with deionized water) applicable to either or both of the sixth dielectric layer 709 and the fifth dielectric layer 603. Next, dielectric-to-dielectric and metal-to-metal bonding processes can be performed to align the sixth conductive connector 711 of the sixth bonding layer 720 with the fifth conductive connector 605 of the fifth bonding layer 620. The metal-to-metal bonding process includes a pre-bonding step during which the sixth bonding layer 720 is brought into contact with the fifth bonding layer 620. Pre-bonding can be performed at room temperature (e.g., between approximately 21°C and approximately 25°C). The annealing process in the dielectric-to-dielectric and metal-to-metal bonding processes is continued, such as at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the sixth conductive connector 711 (e.g., copper) and the fifth conductive connector 605 (e.g., copper) diffuse into each other, thereby forming a direct metal-to-metal bond, thereby bonding the second cooling structure layer 500 to the second semiconductor device 700.

[0119] In one embodiment, after the second semiconductor device 700 is bonded to the second cooling structure layer 500, the resulting structure including the first semiconductor device 100, the IMC structure 550, and the second semiconductor device 700 may be referred to as a first semiconductor package 750. In one embodiment, the first semiconductor package 750 may be a system-on-a-chip (SoIC) package. A SoIC package having the IMC structure 550 disposed between the first semiconductor device 100 and the second semiconductor device 700 allows for improved heat dissipation of the first semiconductor package 750.

[0120] Figure 8A The diagram illustrates the introduction of a coolant system 800 into a first semiconductor package 750. In one embodiment, the first coolant system includes an inlet pipe 805, an outlet pipe 807, an external pump 803, and a working fluid 801. In one embodiment, the inlet pipe 805 is fixed to an inlet port 651, the outlet pipe 807 is fixed to an outlet port 653, and the external pump 803 pumps the working fluid 801 through the inlet pipe 805 and the inlet port 651 into a cavity 400, and through the cavity 400 and the outlet port 653 into the outlet pipe 807. In one embodiment, the external pump 803 may have multiple inlet pipes 805 connected to multiple semiconductor packages and multiple outlet pipes 807 returning from these semiconductor packages, wherein a flow splitter is used to divert the working fluid 801 pumped in by the external pump 803 to the multiple semiconductor packages.

[0121] In one embodiment, the working fluid 801 may be a coolant, such as water, an aqueous ethylene glycol solution, etc. The working fluid 801 enters at a first temperature through the inlet port 651, flows through the cavity 400, and exits at a second temperature through the outlet port 653. In embodiments where the working fluid 801 is water, the first temperature may be between 0°C and 40°C. In embodiments where the working fluid 801 is an aqueous ethylene glycol solution, the first temperature may be between -49°C and 40°C. In both embodiments, the second temperature of the working fluid 801 exiting through the outlet port 653 is higher than the first temperature of the working fluid 801 entering through the inlet port 651. The first semiconductor package 750 may have an operating temperature resulting from heat generated by the first semiconductor device 100 and heat generated by the second semiconductor device 700. In one embodiment, the working fluid 801 is pumped into the cavity 400 by an external pump 803, and the working fluid 801 is at a first temperature, wherein the first temperature is lower than the operating temperature of the first semiconductor package 750. As the working fluid 801 passes through the cavity 400, it absorbs (transfers) heat from the first semiconductor package 750 due to the temperature difference between the operating temperature of the first semiconductor package 750 and the lower temperature of the working fluid 801. In one embodiment, as the working fluid 801 leaves the cavity 400, the heat absorbed by the working fluid 801 from the first semiconductor package 750 causes the temperature of the working fluid 801 to rise from a first temperature to a second temperature. As the working fluid 801 passes through the cavity 400, the heat transferred from the first semiconductor package 750 to the working fluid 801 lowers the operating temperature of the first semiconductor package 750. In one embodiment, the working fluid 801 at the second temperature after leaving the cavity 400 can then dissipate heat to the environment outside the first semiconductor package 750. By lowering the operating temperature of the first semiconductor package 750, the first semiconductor package 750 can have improved performance, efficiency, and reliability.

[0122] Figure 8B It shows Figure 8AThe diagram shows a cross-sectional view of the IMC structure 550 at the point where it cuts through the cavity 400. In one embodiment, when the cavity 400 has a depth D1 of at least 100 micrometers, the external pump 803 may be a standard pump with an operating power greater than 0 watts to 10 watts to provide sufficient power to allow the working fluid 801 to pass through the cavity 400 surrounding the micropillar 401 with a suitable flow profile (e.g., the flow profile of the working fluid 801 through the cavity is a turbulent flow profile). In one embodiment, when the cavity 400 has a depth D1 of at least 50 micrometers, where the aforementioned depth may be less than 100 micrometers, the external pump 803 may be a high-pressure pump with an operating power greater than 0 watts to 20 watts to provide sufficient power to allow the working fluid 801 to pass through the cavity 400 surrounding the micropillar 401 with a suitable flow profile (e.g., the flow profile of the working fluid 801 through the cavity is a turbulent flow profile).

[0123] The heat absorption capacity of the working fluid 801 is influenced by several factors. One factor is the flow profile 850 of the working fluid 801. The flow profile 850 of the working fluid 801 is partly characterized by inertial forces and viscous forces within it. The flow profile 850 of the working fluid 801 is characterized by the ratio of inertial forces to viscous forces within the fluid, a ratio known as the Reynolds number. The Reynolds number indicates the transition from laminar to turbulent flow. In turbulent flow, the flow profile 850 is dominated by inertial forces rather than viscous forces. The thermal conductivity of the working fluid 801 in turbulent flow is greater than that in laminar flow. In one embodiment, the number and pitch of the micropillars 401 within the cavity 400, the shape of the micropillars 401 obstructing the flow profile 850 of the working fluid, the flow velocity of the working fluid 801 flowing through the cavity 400 generated by the external pump 803, and the cavity depth D1 all contribute to driving the flow profile 850 of the working fluid 801 into a turbulent flow profile, thereby increasing the thermal conductivity of the working fluid 801. By increasing the thermal conductivity of the working fluid 801, heat can be absorbed from the first semiconductor package 750 at a faster rate when the working fluid 801 passes through the cavity 400, thereby reducing the operating temperature of the first semiconductor package 750 and improving the effectiveness of the IMC structure 550. In one embodiment, the IMC structure 550 is configured to generate turbulence (e.g., a Reynolds number of 4,000 or greater) in the flow profile 850 of the working fluid 801 when the working fluid 801 passes through the cavity 400.

[0124] Figure 9 An embodiment is shown in which the second cooling structure layer 500 is bonded to the first cooling structure layer 200 before any substrate vias are formed in any structure. In this embodiment, it is formed in a similar manner and with a similar process as discussed above. Figures 1 to 5 The structure described herein, except that a first TSV 301 is not formed through the first cooling structure layer 200 and a second TSV 507 is not formed through the second cooling structure layer 500. In this embodiment, after the second cooling structure layer 500 is bonded to the first cooling structure layer 200 to form the IMC structure 550, a first hole 901 is formed through both the first cooling structure layer 200 and the second cooling structure layer 500. In one embodiment, the first hole 901 is formed in a manner similar to that discussed above for forming the opening for the first TSV 301. In another embodiment, the first hole 901 is formed by a mechanical process such as drilling. In this embodiment, the third bonding layer 320 and the fourth bonding layer 520 may utilize metal dummy pads to form a metal-to-metal bond as described above.

[0125] Figure 10 A first semiconductor package 750 is shown in one embodiment, wherein a first TSV 301 and a second TSV 507 are formed in... Figure 9 The third TSV 1001 in the first hole 901 discussed above is replaced. In one embodiment, the third TSV 1001 is formed in a similar manner and with similar materials as discussed above with respect to the first TSV 301.

[0126] In some embodiments, the structures of the IMC structure 550, the first semiconductor device 100, and the second semiconductor device 700 can be formed separately and then bonded together by wafer-to-wafer bonding, chip-to-wafer bonding, or chip-to-chip bonding.

[0127] By forming an IMC structure 550 between two semiconductor devices (e.g., a first semiconductor device 100 and a second semiconductor element 700), advantageous effects are achieved by allowing rapid heat dissipation from the first semiconductor package 750. The first semiconductor package 750 is a SoIC package or a 3DIC package, which are high-performance computing packages with power outputs ranging from 1,000 watts to 5,000 watts. By positioning the IMC structure 550 in the middle of the first semiconductor package 750, relative to the heat dissipation structure on the outside of the first semiconductor package 750, heat generated by the first semiconductor device 100 can be dissipated from the first semiconductor package 750 without traversing the entire first semiconductor package 750. Furthermore, by utilizing the working fluid 801 within the coolant system 800, the high specific heat associated with the working fluid 801, and the ability to introduce the working fluid 801 at a temperature significantly lower than the operating temperature of the first semiconductor package 750, allows the working fluid 801 to remove a significant amount of heat, thereby improving the efficiency and reliability of the first semiconductor package 750. In addition, forming a cavity 400 around the micropillar 401 at a specific depth (e.g., a first depth D1) with a specific pump (e.g., a standard pump and a high-pressure pump) allows for turbulent flow of the working fluid 801 within the cavity 400. The importance of the turbulent flow of the working fluid 801 within the cavity 400 lies in the fact that the turbulent flow of the fluid has particles with increased lateral motion, which increases the thermal conductivity of the fluid. This allows the working fluid 801 to remove even more heat generated by the first semiconductor package 750 and allows for lower operating temperatures in higher power density packages.

[0128] According to some embodiments, a semiconductor device includes a first semiconductor device, an integrated cooling structure, a second semiconductor device, and a plurality of substrate vias. The first semiconductor device includes a first interconnect structure. The integrated cooling structure is coupled to the first interconnect structure, wherein the integrated cooling structure is configured to allow working fluid to enter and exit the integrated cooling structure. The second semiconductor device includes a second interconnect structure, and the second semiconductor device is coupled to the integrated cooling structure relative to the first interconnect structure. The plurality of substrate vias extend through the integrated cooling structure, wherein the substrate vias electrically couple the first semiconductor device to the second semiconductor device. In one embodiment, the integrated cooling structure includes an inlet port and an outlet port, both of which are connected to a cavity within the integrated cooling structure. In one embodiment, the semiconductor device further includes an external pump, an inlet pipe, and an outlet pipe. A first side of the inlet pipe is attached to the external pump, and a second side of the inlet pipe is attached to the inlet port, wherein the inlet pipe contains working fluid. A first side of the outlet pipe is attached to the outlet port, and a second side of the outlet pipe is attached to the external pump, wherein the outlet pipe contains working fluid. In one embodiment, the integrated cooling structure includes a cavity and a plurality of micropillars. The cavity is configured to allow working fluid to flow through it. The micropillars extend from a first side of the cavity to a second side of the cavity, wherein the micropillars are configured to obstruct the flow of working fluid through the cavity. In one embodiment, a first subset of the micropillars does not have substrate vias, and a second subset of the micropillars each surrounds one of the substrate vias. In one embodiment, the micropillars have a tear-drop cross section in a top view. In one embodiment, the working fluid includes a glycol solution or water.

[0129] According to some embodiments, a method of manufacturing a semiconductor device includes: attaching a first substrate to a first semiconductor device; etching a cavity in the first substrate; wherein the step of etching the cavity forms a plurality of micropillars within the cavity, and the micropillars are formed of a material of the first substrate; attaching a second substrate relative to the first semiconductor device to the first substrate, wherein the step of attaching the second substrate to the first substrate seals the cavity to form an integrated cooling structure configured to contain a liquid coolant; and attaching a second semiconductor device relative to the first semiconductor device to the integrated cooling structure. In one embodiment, the method of manufacturing a semiconductor device further includes: forming a water inlet port through the second substrate into the cavity, and the water inlet port being adjacent to a first side of the second semiconductor device; and forming a water outlet port through the second substrate into the cavity, and the water outlet port being adjacent to a second side of the second semiconductor device, and the second side being located on the side of the second semiconductor device opposite to the first side. In one embodiment, the method of manufacturing a semiconductor device further includes: attaching a water inlet pipe to the water inlet port; attaching a water outlet pipe to the water outlet port; and pumping liquid coolant into the cavity through the water inlet pipe, around the micropillars, and out through the water outlet pipe. In one embodiment, the liquid coolant has a first temperature at the inlet pipe and a second temperature at the outlet pipe, wherein the second temperature is greater than the first temperature. In one embodiment, during the process of pumping the liquid coolant into the cavity through the inlet pipe, around the micropillars, and out through the outlet pipe, the liquid coolant exhibits turbulent flow around the micropillars within the cavity. In one embodiment, a first subset of the micropillars is formed to include perforations extending through the micropillars, and a second subset of the micropillars is formed to not include perforations. In one embodiment, each of the micropillars within the cavity is spaced apart from each of the other micropillars by a different distance. In one embodiment, the liquid coolant comprises an ethylene glycol solution or water.

[0130] According to some embodiments, a semiconductor device includes a first semiconductor package, a pump system, and a liquid coolant. The first semiconductor package includes a first semiconductor device, a second semiconductor device, and an integrated micro-cooling structure. The integrated micro-cooling structure is disposed between the first semiconductor device and the second semiconductor device. The pump system is attached to the first semiconductor package and includes a pump, a first conduit, and a second conduit. A first side of the first conduit is attached to the pump, and a second side of the first conduit is attached to the integrated micro-cooling structure. A first side of the second conduit is attached to the integrated micro-cooling structure, and a second side of the second conduit is attached to the pump. The liquid coolant is contained within a cavity within the pump system and the integrated micro-cooling structure. In one embodiment, the pump has a pump power of 10 watts or less. In one embodiment, the pump system is configured to contain liquid coolant at a first temperature in the first conduit and liquid coolant at a second temperature in the second conduit, the second temperature being higher than the first temperature. In one embodiment, the pump system is configured to contain liquid coolant with a Reynolds number greater than 4,000 within the cavity. In one embodiment, the pump system is attached to a second semiconductor package.

[0131] The components of several embodiments are summarized above to facilitate a better understanding of the views expressed in the embodiments of this utility model by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this utility model to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this utility model, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this utility model.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor device, the first semiconductor device including a first interconnect structure; An integrated cooling structure is coupled to the first interconnect structure, wherein the integrated cooling structure is configured to allow a working fluid to enter and exit the integrated cooling structure; A second semiconductor device includes a second interconnect structure, the second semiconductor device being coupled to the integrated cooling structure relative to the first interconnect structure; as well as Multiple substrate vias extend through the integrated cooling structure, wherein the multiple substrate vias electrically couple the first semiconductor device to the second semiconductor device.

2. The semiconductor device as claimed in claim 1, characterized in that, The integrated cooling structure includes a water inlet port and a water outlet port, and both the water inlet port and the water outlet port are connected to a cavity within the integrated cooling structure.

3. The semiconductor device as claimed in claim 2, characterized in that, Also includes: An external pump; A water inlet pipe, a first side of which is attached to the external pump and a second side of which is attached to the water inlet port, wherein the water inlet pipe contains the working fluid; as well as A water outlet pipe, a first side of which is attached to the water outlet port and a second side of which is attached to the external pump, wherein the water outlet pipe contains the working fluid.

4. The semiconductor device as claimed in claim 1, characterized in that, The integrated cooling structure includes: A cavity, wherein the cavity is configured to allow the working fluid to flow through the cavity; and Multiple micropillars, wherein the multiple micropillars extend from a first side of the cavity to a second side of the cavity, wherein the multiple micropillars are configured to impede the flow of the working fluid through the cavity.

5. The semiconductor device as claimed in claim 4, characterized in that, A first subset of the plurality of micropillars does not have the plurality of substrate vias, and a second subset of the plurality of micropillars each surrounds one of the plurality of substrate vias.

6. The semiconductor device as claimed in claim 4, characterized in that, The micropillars have a teardrop-shaped profile in a top view.

7. The semiconductor device as claimed in claim 4, characterized in that, The distance between each of the multiple micropillars within the cavity is different.

8. The semiconductor device as claimed in any one of claims 4 to 7, characterized in that, The plurality of micropillars within the cavity have a first diameter, wherein the first diameter is between 100 micrometers and 800 micrometers.

9. A semiconductor device, characterized in that, include: A first semiconductor package, comprising: A first semiconductor device; A second semiconductor device; and An integrated micro-cooling structure is disposed between the first semiconductor device and the second semiconductor device; A pump system, attached to the first semiconductor package, the pump system comprising: One pump; A first conduit, wherein a first side of the first conduit is attached to the pump, and a second side of the first conduit is attached to the integrated micro-cooling structure; and A second conduit, wherein a first side of the second conduit is attached to the integrated micro-cooling structure, and a second side of the second conduit is attached to the pump; and A liquid coolant, wherein the liquid coolant is contained within the pump system and within a cavity of the integrated micro-cooling structure.

10. The semiconductor device as claimed in claim 9, characterized in that, The pump system is attached to a second semiconductor package.

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