Direct current bias circuit and device

Abstract

The utility model relates to a direct current bias circuit and device, and the circuit comprises a signal attenuation unit which is used for accessing an input signal, attenuating the input signal, and outputting an attenuation signal; the first impedance conversion unit is connected with the signal attenuation unit and is used for accessing the attenuation signal with high input impedance and outputting the attenuation signal with low output impedance; and the in-phase direct-current bias unit is connected with the first impedance conversion unit and is used for accessing a bias signal and performing direct-current bias on the attenuation signal output by the low-output impedance according to the bias signal so as to output a bias signal which is kept in the same phase as the input signal. According to the utility model, the input impedance and the signal isolation performance of a biased signal can be improved, the biased signal and an input signal are ensured to be kept in phase, and the precision and the adaptability of the biased signal are facilitated.

Description

Technical Field

[0001] This utility model relates to the field of electronic communication technology, and in particular to a DC bias circuit and device. Background Technology

[0002] DC bias is a common technique in electronic communication technology. However, existing DC bias circuits suffer from low input impedance, poor signal isolation performance, which affects the accuracy of the source signal. Furthermore, the source and target signals cannot be kept in phase, resulting in poor adaptability of the source signal and failing to meet the needs of various applications. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a DC bias circuit and device.

[0004] The technical solution adopted by this utility model to solve its technical problem is: to construct a DC bias circuit, including:

[0005] A signal attenuation unit is used to receive an input signal and attenuate the input signal before outputting an attenuated signal.

[0006] A first impedance transformation unit, connected to the signal attenuation unit, is used to receive the attenuated signal with a high input impedance and output the attenuated signal with a low output impedance; and

[0007] A DC bias unit, connected to the first impedance transformation unit, is used to receive a bias signal and DC bias the attenuated signal output with low output impedance according to the bias signal, so as to output a biased signal that is in phase with the input signal.

[0008] Preferably, the DC bias circuit further includes:

[0009] The second impedance transformation unit is connected to the in-phase DC bias unit and is used to input the bias signal with a high input impedance and input the bias signal to the in-phase DC bias unit with a low output impedance.

[0010] Preferably, the first impedance transformation unit includes a first operational amplifier U1; the non-inverting input terminal of the first operational amplifier U1 is connected to the signal attenuation unit, and the inverting input terminal and output terminal of the first operational amplifier U1 are connected to the non-inverting DC bias unit.

[0011] The second impedance transformation unit includes a fourth operational amplifier U4; the non-inverting input terminal of the fourth operational amplifier U4 is connected to the bias signal, and the inverting input terminal and output terminal of the fourth operational amplifier U4 are connected to the non-inverting DC bias unit.

[0012] Preferably, the first operational amplifier U1 and the fourth operational amplifier U4 are junction field-effect transistor type operational amplifiers.

[0013] Preferably, the signal attenuation unit includes a first resistor R1 and a second resistor R2;

[0014] The first end of the first resistor R1 is used to receive the input signal, and the second end of the first resistor R1 is connected to the first impedance transformation unit and grounded through the second resistor R2.

[0015] Preferably, the signal attenuation unit further includes a filter; the first terminal of the first resistor R1 is grounded via the filter.

[0016] Preferably, the in-phase DC bias unit includes:

[0017] An inverse proportional operation unit, connected to the first impedance transformation unit, is used to invert and amplify the attenuated signal output with low output impedance, and output the inverted signal.

[0018] A DC bias unit, connected to the inverse proportional operation unit and the second impedance transformation unit, is used to invert and DC bias the inverted signal based on the bias signal output with low output impedance, so as to output the biased signal.

[0019] Preferably, the inverse proportional operation unit includes a second operational amplifier U2, a third resistor R3, and a fourth resistor R4;

[0020] The non-inverting input of the second operational amplifier U2 is grounded. The inverting input of the second operational amplifier U2 is connected to the first impedance transformation unit through the third resistor R3 and to the output of the second operational amplifier U2 through the fourth resistor R4. The output of the second operational amplifier U2 is connected to the DC bias unit.

[0021] Preferably, the DC bias unit includes a third operational amplifier U3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8;

[0022] The inverting input of the third operational amplifier U3 is connected to the inverse proportional operational unit via the fifth resistor R5 and to the output of the third operational amplifier U3 via the sixth resistor R6. The non-inverting input of the third operational amplifier U3 is connected to the second impedance transformation unit via the seventh resistor R7 and to ground via the eighth resistor R8. The output of the third operational amplifier U3 outputs the biased signal.

[0023] This invention also provides a DC biasing device, including the DC biasing circuit described above.

[0024] The technical solution of this utility model first attenuates the input signal through a signal attenuation unit to obtain an attenuated signal. Then, the attenuated signal is input with a high input impedance and output with a low output impedance through a first impedance transformation unit. Finally, the in-phase DC bias unit performs DC bias on the attenuated signal output with a low output impedance according to the bias signal to obtain a biased signal that is in phase with the input signal. This improves the input impedance and signal isolation performance of the biased signal and ensures that the biased signal is in phase with the input signal, thereby improving the accuracy and adaptability of the biased signal. Attached Figure Description

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0026] Figure 1 This is a circuit diagram of a DC bias circuit in one embodiment of the present invention;

[0027] Figure 2 This is a waveform diagram of the input signal and the biased signal in one embodiment of the present invention. Detailed Implementation

[0028] To provide a clearer understanding of the technical features, objectives, and effects of this utility model, the specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0029] In the following description, it should be understood that the orientations or positional relationships indicated by terms such as "front," "rear," "up," "down," "left," "right," "longitudinal," "horizontal," "vertical," "horizontal," "top," "bottom," "inner," "outer," "head," and "tail" are based on the orientations or positional relationships shown in the accompanying drawings, and are constructed and operated in a specific orientation. They are only for the convenience of describing this technical solution and do not indicate that the device or component referred to must have a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0030] This invention provides a DC bias circuit that can DC bias the input signal (i.e., the source signal) to obtain a biased signal (i.e., the target signal) with a high signal-to-noise ratio and stability, thereby improving the stability and reliability of the electronic circuit.

[0031] Figure 1 This is a circuit diagram of a DC bias circuit in one embodiment of this utility model. Figure 1 As shown, the DC bias circuit may include a signal attenuation unit 1, a first impedance transformation unit 2, a non-inverting DC bias unit 3, and a second impedance transformation unit 4.

[0032] Signal attenuation unit 1 is used to receive input signals and attenuate them before outputting an attenuated signal. Since some input signals are AC signals, and the difference between the valley and peak values ​​(i.e., peak-to-peak values) of these AC signals is large, even exceeding the voltage range that the signal processing circuit can recognize, for example, for a signal processing circuit operating at a voltage below 5V, its recognition range is 0V to 5V. When the system recognizes an input signal with a peak-to-peak value greater than 5V, signal distortion will inevitably occur. Signal attenuation unit 1 can reduce the voltage amplitude of the input signal by a certain proportion to prevent the input signal's voltage range from exceeding the voltage range that the signal processing circuit can recognize.

[0033] In some embodiments, such as Figure 1 As shown, the signal attenuation unit 1 may include a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is used to receive the input signal, and the second end of the first resistor R1 serves as the attenuation signal output terminal connected to the first impedance transformation unit 2. The second end of the first resistor R1 is also grounded via the second resistor R2. In this embodiment, the first resistor R1 and the second resistor R2 form a voltage divider circuit, which can proportionally reduce the voltage amplitude of the input signal. The attenuation signal and the input signal have the following relationship: Vo1 = Vin * R2' / (R1' + R2'), where Vo1 represents the attenuation signal, Vin represents the input signal, R2' represents the resistance value of the second resistor R2, and R1' represents the resistance value of the first resistor R1.

[0034] Understandably, if the impedances of the first resistor R1 and the second resistor R2 are too small, the input signal will require a larger current to maintain a constant voltage. This means the source signal output circuit needs to output a larger current, placing higher demands on its driving capability. If this source signal output circuit also supplies the input signal to other signal processing circuits, insufficient driving capability may lead to a drop in the input signal voltage, causing signal distortion. Therefore, the impedances of the first resistor R1 and the second resistor R2 should not be too small. Conversely, if the impedances of the first resistor R1 and the second resistor R2 are too large, the input impedance becomes extremely sensitive to noise currents, making it easier for noise to be superimposed on the input signal, thus reducing the signal-to-noise ratio. Therefore, the impedances of the first resistor R1 and the second resistor R2 should also not be too large. Therefore, it is preferable to use resistors in the range of 1MΩ to 10MΩ for the first resistor R1 and the second resistor R2.

[0035] To further improve the signal-to-noise ratio of the input signal, in some embodiments, such as Figure 1 As shown, the signal attenuation unit 1 may further include a filter 11 for filtering out noise in the input signal. The first terminal of the first resistor R1 is grounded via the filter 11.

[0036] In some embodiments, such as Figure 1 As shown, filter 11 may include capacitor C1. The filtering effect of filter 11 is affected by the capacitance value of capacitor C1. Therefore, the capacitance value of capacitor C1 can be adjusted according to the actual situation.

[0037] Please see Figure 1 The first impedance transformation unit 2 is connected to the signal attenuation unit 1. The first impedance transformation unit 2 is used to receive the attenuated signal with a high input impedance and output the attenuated signal with a low output impedance. The function of the first impedance transformation unit 2 is to construct a signal isolation circuit between the signal attenuation unit 1 and the in-phase DC bias unit 3, so as to reduce the influence between the front and rear stage networks. Moreover, the front stage receives the attenuated signal with a higher impedance, which can avoid signal distortion caused by insufficient driving capability of the source signal output circuit. The rear stage outputs the attenuated signal with a lower impedance, which can improve the driving capability of the attenuated signal and prevent signal distortion caused by insufficient driving force of the rear stage network.

[0038] In some embodiments, such as Figure 1 As shown, the first impedance transformation unit 2 may include a first operational amplifier U1. The non-inverting input terminal of the first operational amplifier U1 is connected to the second terminal of the first resistor R1 in the signal attenuation unit 1. The inverting input terminal and the output terminal of the first operational amplifier U1 are connected to the non-inverting DC bias unit 3 to input an attenuated signal with low output impedance to the non-inverting DC bias unit 3. In this embodiment, the first operational amplifier U1 constitutes a voltage follower circuit, which can isolate the preceding and following circuits, increase the input impedance, and reduce the output impedance.

[0039] To improve the performance of the first impedance transformation unit 2, the first operational amplifier U1 is preferably a junction field-effect transistor (JFET) type operational amplifier, which has the advantage of high input impedance (input impedance can reach GΩ or more).

[0040] Please see Figure 1The in-phase DC bias unit 3 is connected to the first impedance transformation unit 2. The in-phase DC bias unit 3 is used to receive the bias signal and DC biases the attenuated signal with low output impedance according to the bias signal, so that the output signal remains in phase with the input signal. Although the signal attenuation unit 1 ensures that the peak-to-peak value of the attenuated signal is not greater than the span of the recognizable voltage range of the signal processing circuit, it cannot guarantee that the attenuated signal is included within the recognizable voltage range of the signal processing circuit. Taking an input signal of -4V to 2V as an example, after processing by the signal attenuation unit 1, the voltage range of the attenuated signal is -2V to 1V (the reduction ratio of the signal attenuation unit 1 is 0.5). However, the recognizable voltage range of the subsequent signal processing circuit is 0V to 5V, so the attenuated signal cannot be directly acquired. The function of the in-phase DC bias unit 3 is to DC bias the attenuated signal according to the bias signal, so that the DC-biased attenuated signal (i.e., the biased signal) can enter the recognizable voltage range of the subsequent signal processing circuit, and ensure that the input signal and the biased signal remain in phase.

[0041] In some embodiments, such as Figure 1 As shown, the in-phase DC bias unit 3 may include an inverse proportional operation unit 31 and a DC bias unit 32.

[0042] Please see Figure 1 The inverse proportional operation unit 31 is connected to the first impedance transformation unit 2. The inverse proportional operation unit 31 is used to invert and amplify the attenuated signal output from the low output impedance, and output the inverted signal. The function of the inverse proportional operation unit 31 is to reverse the phase of the attenuated signal and adjust the amplitude of the attenuated signal according to the designed gain parameters.

[0043] In some embodiments, such as Figure 1As shown, the inverse proportional operation unit 31 may include a second operational amplifier U2, a third resistor R3, and a fourth resistor R4. The non-inverting input of the second operational amplifier U2 is grounded, and the inverting input of the second operational amplifier U2 is connected to the output of the first operational amplifier U1 via the third resistor R3. The inverting input of the second operational amplifier U2 is also connected to the output of the second operational amplifier U2 via the fourth resistor R4. The output of the second operational amplifier U2 is connected to the DC bias unit 32. In this embodiment, the second operational amplifier U2, the third resistor R3, and the fourth resistor R4 form an inverting amplifier circuit capable of inverting and amplifying the attenuated signal. Its main function is to perform an inverting amplification of the attenuated signal in advance, so that the biased signal obtained after the second inverting amplification by the DC bias unit 32 remains in phase with the input signal. Furthermore, the amplification ratio of the inverse proportional operation unit 31 can be controlled by adjusting the resistance values ​​of the third resistor R3 and the fourth resistor R4. When the resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal, the attenuated signal and the inverted signal are out of phase, meaning that the inverse proportional operation unit 31 functions as an inverter. Of course, when it is necessary to amplify the attenuated signal proportionally, this can be achieved by adjusting the resistance values ​​of the third resistor R3 and the fourth resistor R4.

[0044] Please see Figure 1 The DC bias unit 32 is connected to the inverse proportional operation unit 31 and the second impedance transformation unit 4. The DC bias unit 32 is used to invert the inverted signal and DC bias it according to the bias signal output with low output impedance, so as to output the biased signal. The function of the DC bias unit 32 is to reverse the phase of the inverted signal so that the signal after reversal is in phase with the input signal. It also performs DC bias adjustment on the signal after reversal through the bias signal to ensure that the reference level or DC level of the biased signal is appropriate and to avoid the signal from exceeding the working range or causing distortion.

[0045] In some embodiments, such as Figure 1As shown, the DC bias unit 32 may include a third operational amplifier U3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The inverting input of the third operational amplifier U3 is connected to the output of the second operational amplifier U2 included in the inverse proportional operational unit 31 via the fifth resistor R5. The inverting input of the third operational amplifier U3 is also connected to the output of the third operational amplifier U3 via the sixth resistor R6. The non-inverting input of the third operational amplifier U3 is connected to the second impedance transformation unit 4 via the seventh resistor R7 or connected to the bias signal via the seventh resistor R7. The non-inverting input of the third operational amplifier U3 is also grounded via the eighth resistor R8. The output of the third operational amplifier U3 outputs the biased signal. In this embodiment, the third operational amplifier U3, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 form an inverting amplifier circuit capable of amplifying the inverted signal. The amplification ratio of the DC bias unit 32 can be controlled by adjusting the resistance values ​​of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8. When the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are all equal, the biased signal and the inverted signal have the following relationship: Vo = -Vo3 + Vshift, where Vo represents the biased signal, Vo3 represents the inverted signal, and Vshift represents the bias signal. Correspondingly, when the inverse proportional operation unit 31 is an inverter, the biased signal and the input signal have the following relationship: Vo = Vin * R2' / (R1' + R2') + Vshift. Figure 2 This is a schematic diagram of the waveforms of the input signal and the biased signal in one embodiment of this utility model. The waveform changes of the biased signal and the input signal can be referred to... Figure 2 Of course, when it is necessary to amplify the inverted signal proportionally, this can be achieved by adjusting the resistance values ​​of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8.

[0046] Please see Figure 1 The second impedance transformation unit 4 is connected to the in-phase DC bias unit 3. The second impedance transformation unit 4 is used to input the bias signal with a high input impedance and input the bias signal to the in-phase DC bias unit 3 with a low output impedance. It should be noted that the second impedance transformation unit 4 is an optional circuit, and its function is similar to that of the first impedance transformation unit 2, which will not be described in detail here.

[0047] Furthermore, such as Figure 1As shown, the second impedance transformation unit 4 may include a fourth operational amplifier U4. The non-inverting input of the fourth operational amplifier U4 is connected to a bias signal, and the inverting input and output of the fourth operational amplifier U4 are connected to the seventh resistor R7 included in the non-inverting DC bias unit 3. Correspondingly, to improve the performance of the second impedance transformation unit 4, the fourth operational amplifier U4 is preferably a junction field-effect transistor (JFET) type operational amplifier. The function of the second impedance transformation unit 4 is similar to that of the first impedance transformation unit 2, as described above, and will not be repeated here.

[0048] Understandably, the magnitude of the bias signal determines the actual voltage range of the biased signal. To ensure that the biased signal falls within the identifiable voltage range of the signal processing circuit, in some embodiments, the DC bias circuit may further include an adjustment unit capable of adjusting the magnitude of the bias signal. The input terminal of the adjustment unit is connected to the bias signal, and the output terminal of the adjustment unit is connected to the non-inverting input terminal of the fourth operational amplifier U4. Further, the adjustment unit may include a potentiometer, with the first terminal of the potentiometer connected to the bias signal, the second terminal of the potentiometer grounded, and the adjustable terminal of the potentiometer connected to the non-inverting input terminal of the fourth operational amplifier U4. Thus, the voltage magnitude of the bias signal can be adjusted by operating the potentiometer.

[0049] It should be noted that the function of the DC bias circuit is to ensure that the input signal falls within the recognizable voltage range of the signal processing circuit, so that the signal processing circuit can accurately identify the biased signal and perform corresponding operations based on the biased signal. In other words, the signal processing circuit refers to the hardware circuit that ultimately obtains the biased signal; however, the specific function of the signal processing circuit is not limited in this invention.

[0050] Understandably, this invention can improve the input impedance and signal isolation performance of the biased signal, and also ensure that the biased signal remains in phase with the input signal, which helps improve the accuracy and adaptability of the biased signal.

[0051] This utility model also provides a DC biasing device, including the DC biasing circuit provided in the embodiments of this utility model.

[0052] It is understood that the above embodiments only illustrate preferred embodiments of the present utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present utility model patent. It should be noted that for those skilled in the art, the above technical features can be freely combined, and several modifications and improvements can be made without departing from the concept of the present utility model, all of which fall within the protection scope of the present utility model. Therefore, all equivalent transformations and modifications made within the scope of the claims of the present utility model should fall within the coverage of the claims of the present utility model.

Claims

1. A DC bias circuit, characterized in that, include: A signal attenuation unit is used to receive an input signal and attenuate the input signal before outputting an attenuated signal. The first impedance transformation unit is connected to the signal attenuation unit and is used to receive the attenuated signal with a high input impedance and output the attenuated signal with a low output impedance. as well as A DC bias unit, connected to the first impedance transformation unit, is used to receive a bias signal and DC bias the attenuated signal output with low output impedance according to the bias signal, so as to output a biased signal that is in phase with the input signal.

2. The DC bias circuit according to claim 1, characterized in that, The DC bias circuit also includes: The second impedance transformation unit is connected to the in-phase DC bias unit and is used to input the bias signal with a high input impedance and input the bias signal to the in-phase DC bias unit with a low output impedance.

3. The DC bias circuit according to claim 2, characterized in that, The first impedance transformation unit includes a first operational amplifier U1; the non-inverting input terminal of the first operational amplifier U1 is connected to the signal attenuation unit, and the inverting input terminal and output terminal of the first operational amplifier U1 are connected to the non-inverting DC bias unit. The second impedance transformation unit includes a fourth operational amplifier U4; The non-inverting input of the fourth operational amplifier U4 is connected to the bias signal, and the inverting input and output of the fourth operational amplifier U4 are connected to the non-inverting DC bias unit.

4. The DC bias circuit according to claim 3, characterized in that, The first operational amplifier U1 and the fourth operational amplifier U4 are junction field-effect transistor type operational amplifiers.

5. The DC bias circuit according to claim 2, characterized in that, The signal attenuation unit includes a first resistor R1 and a second resistor R2; The first end of the first resistor R1 is used to receive the input signal, and the second end of the first resistor R1 is connected to the first impedance transformation unit and grounded through the second resistor R2.

6. The DC bias circuit according to claim 5, characterized in that, The signal attenuation unit further includes a filter; the first terminal of the first resistor R1 is grounded through the filter.

7. The DC bias circuit according to any one of claims 2 to 6, characterized in that, The in-phase DC bias unit includes: An inverse proportional operation unit, connected to the first impedance transformation unit, is used to invert and amplify the attenuated signal output with low output impedance, and output the inverted signal. A DC bias unit, connected to the inverse proportional operation unit and the second impedance transformation unit, is used to invert and DC bias the inverted signal based on the bias signal output with low output impedance, so as to output the biased signal.

8. The DC bias circuit according to claim 7, characterized in that, The inverse proportional operation unit includes a second operational amplifier U2, a third resistor R3, and a fourth resistor R4; The non-inverting input of the second operational amplifier U2 is grounded. The inverting input of the second operational amplifier U2 is connected to the first impedance transformation unit through the third resistor R3 and to the output of the second operational amplifier U2 through the fourth resistor R4. The output of the second operational amplifier U2 is connected to the DC bias unit.

9. The DC bias circuit according to claim 7, characterized in that, The DC bias unit includes a third operational amplifier U3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8; The inverting input of the third operational amplifier U3 is connected to the inverse proportional operational unit via the fifth resistor R5 and to the output of the third operational amplifier U3 via the sixth resistor R6. The non-inverting input of the third operational amplifier U3 is connected to the second impedance transformation unit via the seventh resistor R7 and to ground via the eighth resistor R8. The output of the third operational amplifier U3 outputs the biased signal.

10. A DC biasing device, characterized in that, Includes the DC bias circuit as described in any one of claims 1 to 9.

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