Semiconductor device

Abstract

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor technology, and specifically relates to a semiconductor device. Background Technology

[0002] In semiconductor devices, laterally diffused metal-oxide-semiconductor (LDMOS) devices possess advantages such as high breakdown voltage, high-frequency performance, and ease of integration, making them widely used in power integrated circuits. Breakdown voltage and characteristic on-resistance are key electrical parameters of LDMOS devices; improving the breakdown voltage and reducing the characteristic on-resistance are crucial for enhancing device performance. However, there is a trade-off between these two electrical parameters. For example, a short drift region injection window or low doping concentration can increase the device's breakdown voltage, but it also leads to an increase in characteristic on-resistance. Therefore, it is difficult to simultaneously achieve high breakdown voltage and low characteristic on-resistance in existing LDMOS devices. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor device that can reduce the characteristic on-resistance without changing the breakdown voltage, thereby improving the performance of the semiconductor device.

[0004] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:

[0005] This utility model provides a semiconductor device, comprising:

[0006] Substrate;

[0007] A well region is disposed within the substrate;

[0008] Two drift zones are spaced apart within the trap area, and shallow trench isolation structures are provided within the drift zones;

[0009] The body region is located within the trap region between the two drift regions;

[0010] A vertical gate is located within the body region and extends from the surface of the substrate into the well region;

[0011] Source doped regions are respectively disposed in the body regions on both sides of the vertical gate;

[0012] A drain-doped region is disposed within the drift region; and

[0013] A planar gate is disposed around the vertical gate and the source doped region, and covers a portion of the body region, a portion of the well region, and a portion of the shallow trench isolation structure.

[0014] In one embodiment of the present invention, the semiconductor device includes a gate oxide layer disposed on the substrate and between the substrate and the vertical gate.

[0015] In one embodiment of this utility model, the sum of the depth of the vertical gate and the thickness of the gate oxide layer is equal to the depth of the shallow trench isolation structure.

[0016] In one embodiment of the present invention, on the same side of the vertical gate, the source doping region includes a first type doping region and a second type doping region, and the first type doping region and the second type doping region on both sides of the vertical gate are symmetrically arranged.

[0017] In one embodiment of this utility model, the doping type in the first type of doped region is the opposite of the doping type in the second type of doped region.

[0018] In one embodiment of this invention, the depth of the drift region is less than or equal to the depth of the trap region.

[0019] In one embodiment of this utility model, the depth of the body region is less than or equal to the depth of the drift region.

[0020] In one embodiment of this utility model, the depth of the shallow trench isolation structure is less than the depth of the drift zone.

[0021] In one embodiment of the present invention, within the same drift region, the drain doped region is disposed in the drift region on the side of the shallow trench isolation structure away from the body region.

[0022] In one embodiment of this utility model, the doping type of the drain doped region is the same as that of the drift region, and the doping concentration of the drain doped region is greater than that of the drift region.

[0023] In summary, this utility model provides a semiconductor device. By improving the layout of the semiconductor device, the unexpected technical effect of this application is that it can significantly reduce the characteristic on-resistance of the semiconductor device without changing the breakdown voltage, thereby reducing power consumption and improving the performance of the LDMOS device. It can also increase the breakdown voltage of the semiconductor device, improving breakdown and leakage phenomena. Furthermore, it can simplify the manufacturing process of the semiconductor device and reduce production costs for enterprises. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a top view of a semiconductor device in one embodiment.

[0026] Figure 2 For along Figure 1 A cross-sectional view of a semiconductor device along the AA direction.

[0027] Label Explanation:

[0028] 100. Substrate; 101. Well region; 102. Drift region; 103. Shallow trench isolation structure; 104. Body region; 105. Vertical gate; 106. Source doped region; 1061. Type I doped region; 1062. Type II doped region; 107. Drain doped region; 108. Gate oxide layer; 109. Planar gate; 110. Interlayer dielectric layer; 111. Drain electrode; 112. Source electrode; 113. Planar gate electrode; 114. Vertical gate electrode; 115. Trench; 200. Planar channel; 201. Vertical channel. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0030] The present invention provides a semiconductor device that, through improvements in the layout of the semiconductor device, increases the conductive channels and exhibits excellent performance such as low characteristic on-resistance and high breakdown voltage. It can be widely used in various fields such as communications, transportation, energy, medicine, home appliances, and aerospace.

[0031] Please see Figures 1 to 2As shown, this invention provides a semiconductor device, including, for example, a substrate 100, a vertical gate electrode 114, a source electrode 112, and a planar gate electrode 113. The source electrodes 112 are respectively disposed on both sides of the vertical gate electrode 114, and the planar gate electrode 113 is disposed around the vertical gate electrode 114 and the source electrodes 112. The semiconductor device provided by this invention has multiple conductive channels, which can significantly reduce the characteristic on-resistance of the semiconductor device without changing the breakdown voltage, thereby improving the performance of the semiconductor device.

[0032] Please see Figure 2 As shown, in one embodiment of this invention, the substrate 100 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials, and also includes stacked structures composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, and germanium-on-insulator, etc. This invention does not limit the material of the substrate 100, and the substrate 100 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate. In this embodiment, the substrate 100 is, for example, a P-doped semiconductor substrate.

[0033] Please see Figure 2 As shown, in one embodiment of the present invention, the semiconductor device further includes a well region 101 disposed within the substrate 100. In this embodiment, the well region 101 is, for example, an N-type doped region. In other embodiments, the well region 101 may also be a P-type doped region.

[0034] Please see Figure 2 As shown, in one embodiment of the present invention, the semiconductor device further includes two drift regions 102, which are spaced apart within the well region 101. The doping type of the two drift regions 102 is, for example, the same as that of the well region 101. In this embodiment, the two drift regions 102 have, for example, the same size, and both drift regions 102 are, for example, N-type doped regions. The depth of the drift regions 102 is, for example, less than the depth of the well region 101, and the doping concentration of the drift regions 102 is, for example, greater than the doping concentration of the well region 101. In one embodiment of the present invention, the depth of the drift regions 102 may also be equal to the depth of the well region 101. In one embodiment of the present invention, the sizes of the two drift regions 102 may also be different. In other embodiments, the drift regions 102 may also be P-type doped regions. During the operation of the semiconductor device, the drift regions 102 can participate in current transmission. When the semiconductor device is turned off, the drift regions 102 carry most of the voltage, helping to maintain the reverse bias voltage of the semiconductor device.

[0035] Please see Figure 2 As shown, in one embodiment of this invention, the semiconductor device further includes a body region 104 disposed within a well region 101 between two drift regions 102. The doping type of the body region 104 is, for example, opposite to the doping type of the drift regions 102. In this embodiment, the body region 104 extends, for example, from the surface of the substrate 100 into the well region 101, and the depth of the body region 104 is, for example, less than the depth of the drift regions 102. The body region 104 is, for example, a P-type doped region. In other embodiments, the depth of the body region 104 may also be equal to the depth of the drift regions 102.

[0036] Please see Figure 2 As shown, in one embodiment of this invention, a shallow trench isolation structure 103 is provided within the drift region 102. In this embodiment, one shallow trench isolation structure 103 is provided in each of the two drift regions 102. The shallow trench isolation structure 103 extends, for example, from the surface of the substrate 100 into the drift region 102. In this embodiment, the depth of the shallow trench isolation structure 103 is, for example, less than the depth of the drift region 102, and the material of the shallow trench isolation structure 103 is, for example, an insulating material such as silicon oxide or fluorosilicone glass. By providing the shallow trench isolation structure 103, the effective surface distance between the body region 104 and the subsequently provided drain doped region 107 in the drift region 102 can be increased, thereby improving the breakdown voltage of the semiconductor device.

[0037] Please see Figure 2 As shown, in one embodiment of the present invention, the semiconductor device further includes a trench 115 located within the body region 104 and extending from the surface of the substrate 100 into the well region 101. In this embodiment, the depth of the trench 115 is, for example, equal to the depth of the shallow trench isolation structure 103, to simplify the semiconductor device fabrication process and reduce production costs for enterprises. In other embodiments of the present invention, the depth of the trench 115 may not be equal to the depth of the shallow trench isolation structure 103.

[0038] Please see Figure 2 As shown, in one embodiment of this invention, the semiconductor device further includes a gate oxide layer 108, which is disposed within the trench 115 and on the substrate 100. The gate oxide layer 108 is made of materials such as silicon oxide, and its thickness can be set according to actual needs. By providing the gate oxide layer 108, the breakdown voltage of the semiconductor device can be improved, and the breakdown and leakage phenomena of the semiconductor device can be mitigated.

[0039] Please see Figure 2As shown, in one embodiment of this utility model, the body region 104 includes a vertical gate 105, which fills a trench 115, and the surface of the vertical gate 105 is flush with the surface of the substrate 100. The material of the vertical gate 105 is, for example, polysilicon, which can be P-type or N-type, and the doping type of the vertical gate 105 is different from that of the substrate 100. Furthermore, this application does not limit the thickness of the vertical gate 105, which can be set according to actual needs.

[0040] Please see Figure 2 As shown, in one embodiment of this utility model, a source doped region 106 is further provided within the body region 104. The source doped regions 106 are, for example, respectively disposed on both sides of the vertical gate 105. In this embodiment, the source doped regions 106 include, for example, a first type doped region 1061 and a second type doped region 1062. The first type doped region 1061 is, for example, symmetrically disposed on both sides of the vertical gate 105, and the second type doped region 1062 is, for example, symmetrically disposed on both sides of the vertical gate 105. On the same side of the vertical gate 105, the second type doped region 1062 is, for example, disposed on the side of the first type doped region 1061 away from the vertical gate 105, and the first type doped region 1061 and the second type doped region 1062 are disposed adjacent to each other. Furthermore, the doping type in the first type doped region 1061 is, for example, opposite to, the doping type in the second type doped region 1062, and the doping type in the first type doped region 1061 is the same as the doping type in the body region 104. In this embodiment, the first type doped region 1061 is, for example, a P-type doped region, and the second type doped region 1062 is, for example, an N-type doped region. The doping concentration of the first type doped region 1061 is, for example, greater than the doping concentration in the body region 104, and the doping concentration of the second type doped region 1062 is, for example, greater than the doping concentration in the drift region 102 and the well region 101.

[0041] Please see Figure 2 As shown, in one embodiment of this invention, a drain doped region 107 is further provided within the drift region 102, and the drain doped regions 107 are respectively disposed within the two drift regions 102. Specifically, in the drift region 102, the drain doped region 107 is, for example, disposed on the side of the shallow trench isolation structure 103 away from the body region 104. The doping type of the drain doped region 107 is the same as the doping type of the drift region 102, and the doping concentration of the drain doped region 107 is, for example, greater than the doping concentration of the drift region 102 and the well region 101. In this embodiment, the drain doped region 107 is, for example, an N-type doped region. In other embodiments, the drain doped region 107 may also be a P-type doped region.

[0042] Please see Figures 1 to 2As shown, in one embodiment of this utility model, the semiconductor device further includes a planar gate 109. The planar gate 109 is disposed around the vertical gate 105 and the source doped region 106, and covers a portion of the body region 104 and a portion of the shallow trench isolation structure 103, as well as the well region 101 between the body region 104 and the shallow trench isolation structure 103. The material of the planar gate 109 is, for example, polysilicon, which can be P-type or N-type, and the doping type of the planar gate 109 is different from the doping type of the substrate 100. Furthermore, this application does not limit the thickness of the planar gate 109, which can be set according to actual needs.

[0043] Please see Figure 2 As shown, in one embodiment of this invention, the semiconductor device further includes an interlayer dielectric layer 110, which covers the gate oxide layer 108 and the planar gate 109. By etching a portion of the interlayer dielectric layer 110 and a portion of the gate oxide layer 108, a plurality of vias (not shown) are formed within the interlayer dielectric layer 110 and the gate oxide layer 108. These vias are disposed on a portion of the drain doped region 107, a portion of the vertical gate 105, and a portion of the source doped region 106. By etching the interlayer dielectric layer 110 on the planar gate 109, holes (not shown) are formed within the interlayer dielectric layer 110, and these holes are disposed on a portion of the planar gate 109. The material of the interlayer dielectric layer 110 is, for example, silicon oxide. By providing the interlayer dielectric layer 110, conductive plugs can be formed, and the semiconductor device can be protected during fabrication.

[0044] Please see Figure 2 As shown, in one embodiment of this utility model, the semiconductor device further includes conductive plugs disposed within vias and holes in the interlayer dielectric layer 110 to form electrodes. In this embodiment, the electrodes include a drain electrode 111, a source electrode 112, a planar gate electrode 113, and a vertical gate electrode 114. The drain electrode 111 is disposed on the drain doped region 107, the source electrode 112 is located between the first type doped region 1061 and the second type doped region 1062, the planar gate electrode 113 is disposed on the planar gate 109, and the vertical gate electrode 114 is disposed on the vertical gate 105. The planar gate electrode 113 and the vertical gate electrode 114 can be connected via a downstream metal interconnect. By forming a complete circuit with the drain electrode 111, the source electrode 112, the planar gate electrode 113, and the vertical gate electrode 114, the semiconductor device can operate normally.

[0045] Please see Figure 2As shown, in one embodiment of this invention, during the operation of the semiconductor device, when the voltage of the planar gate electrode 113 and the voltage of the vertical gate electrode 114 exceed a threshold voltage, the semiconductor device includes two conductive channels, namely a planar channel 200 and a vertical channel 201. In the planar channel 200, current flows out from the drain electrode 111, passes through the drift region 102, the well region 101, and the body region 104, and flows into the second type doped region 1062 within the source electrode 112. In the vertical channel 201, current flows out from the drain electrode 111, passes through the drift region 102 and enters the well region 101, enters the body region 104 along the sidewall of the vertical gate 105 within the well region 101, and flows into the first type doped region 1061 within the source electrode 112. During the semiconductor device shutdown process, when the voltages of the planar gate electrode 113 and the vertical gate electrode 114 are less than the threshold voltage, both conductive channels are closed, and a PN junction is formed between the drift region 102 and the body region 104. As the voltage of the drain electrode 111 increases, the reverse-biased PN junction expands towards the side where the drift region 102 is located, and the drift region 102 below the shallow trench isolation structure 103 bears most of the voltage of the drain electrode 111. Therefore, the semiconductor device provided by this invention, by increasing the conductive channels, can reduce the characteristic on-resistance of the semiconductor device without changing the breakdown voltage.

[0046] In summary, this utility model provides a semiconductor device. By setting a vertical gate between the source and the source, the unexpected technical effect of this application is that it can increase the conductive channels of the semiconductor device, enabling the semiconductor device to simultaneously possess planar and vertical channels. This significantly reduces the characteristic on-resistance of the semiconductor device without changing its breakdown voltage, thereby reducing power consumption and improving performance. By setting a shallow trench isolation structure and a gate oxide layer, the breakdown voltage of the semiconductor device can be increased, improving breakdown and leakage phenomena. By controlling the relative dimensions of the vertical gate, gate oxide layer, and shallow trench isolation structure, the manufacturing process of the semiconductor device can be simplified, reducing production costs for enterprises.

[0047] The embodiments of this utility model disclosed above are merely illustrative of the present utility model. The embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Obviously, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that, At least including: Substrate; A well region is disposed within the substrate; Two drift zones are spaced apart within the trap area, and shallow trench isolation structures are provided within the drift zones; The body region is located within the trap region between the two drift regions; A vertical gate is located within the body region and extends from the surface of the substrate into the well region; Source doped regions are respectively disposed in the body regions on both sides of the vertical gate; A drain-doped region is disposed within the drift region; as well as A planar gate is disposed around the vertical gate and the source doped region, and covers a portion of the body region, a portion of the well region, and a portion of the shallow trench isolation structure.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a gate oxide layer disposed on the substrate and between the substrate and the vertical gate.

3. The semiconductor device according to claim 2, characterized in that, The sum of the depth of the vertical gate and the thickness of the gate oxide layer is equal to the depth of the shallow trench isolation structure.

4. The semiconductor device according to claim 1, characterized in that, On the same side of the vertical gate, the source doped region includes a first type of doped region and a second type of doped region, and the first type of doped region and the second type of doped region on both sides of the vertical gate are symmetrically arranged.

5. The semiconductor device according to claim 4, characterized in that, The doping type in the first type of doped region is the opposite of the doping type in the second type of doped region.

6. The semiconductor device according to claim 1, characterized in that, The depth of the drift region is less than or equal to the depth of the trap region.

7. The semiconductor device according to claim 1, characterized in that, The depth of the body region is less than or equal to the depth of the drift region.

8. The semiconductor device according to claim 1, characterized in that, The depth of the shallow trench isolation structure is less than the depth of the drift zone.

9. The semiconductor device according to claim 1, characterized in that, Within the same drift region, the drain doped region is located in the drift region on the side of the shallow trench isolation structure away from the body region.

10. The semiconductor device according to claim 1, characterized in that, The doping type of the drain doped region is the same as that of the drift region, and the doping concentration of the drain doped region is greater than that of the drift region.

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