Integrated circuit structure

Abstract

The present disclosure describes an integrated circuit structure. The integrated circuit structure includes a first semiconductor structure having a first channel having a first channel width and a second semiconductor structure having a second channel having a second channel width different from the first channel width. The first channel and the second channel are in contact with each other.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit structure. Background Technology

[0002] As technology advances and the demand for hybrid devices and circuit structures grows, the increasing number of placement cells and the ability to provide differential arrays of placement cells necessitate designs that conform to smaller integrated circuit layouts, thus increasing the challenges for integrated circuit manufacturers. Utility Model Content

[0003] This disclosure provides an integrated circuit structure including a first semiconductor structure and a second semiconductor structure. The first semiconductor structure has a first channel with a first channel width. The second semiconductor structure has a second channel with a second channel width different from the first channel width, wherein the first channel and the second channel are in contact with each other.

[0004] Another aspect of this disclosure is to provide an integrated circuit structure including a first semiconductor device unit and a second semiconductor device unit. The first semiconductor device unit has a first gate with a first gate width. The second semiconductor device unit has a second gate with a second gate width different from the first gate width, wherein the first gate and the second gate are in contact with each other.

[0005] Another aspect of this disclosure is to provide an integrated circuit structure comprising a first semiconductor structure and a second semiconductor structure. The first semiconductor structure has a first channel extending along a first axis and a first gate electrode extending along a second axis. The first channel has a first channel width, and the first gate electrode has a first gate width. The second semiconductor structure has a second channel extending along the first axis and a second gate electrode extending along the second axis. The second channel has a second channel width. The second channel width is different from the first channel width. The first channel and the second channel are in contact with each other, and the second gate electrode has a second gate width different from the first gate width. Attached Figure Description

[0006] The following detailed description is the best way to understand the nature of this disclosure when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, many features are not drawn to scale. In fact, for clarity of description, the dimensions of each feature may be arbitrarily increased or decreased.

[0007] Figure 1 These are schematic diagrams illustrating circuit implementation layouts based on some embodiments of this disclosure;

[0008] Figure 2A This is a diagram illustrating another layout for implementing a circuit according to some embodiments of the present disclosure;

[0009] Figure 2B This is a cross-sectional view of a circuit implementation layout based on some embodiments of this disclosure;

[0010] Figure 3 This is a diagram illustrating another layout for circuit implementation based on some embodiments of this disclosure;

[0011] Figure 4 This is a flowchart of a layout method based on some embodiments of the present disclosure;

[0012] Figure 5 This is a diagram illustrating another layout for circuit implementation based on some embodiments of this disclosure;

[0013] Figure 6 These are illustrations of computer system examples that can implement various embodiments of this disclosure, based on some embodiments of this disclosure;

[0014] Figure 7 These are illustrations of an integrated circuit manufacturing system and associated integrated circuit manufacturing processes according to some embodiments of this disclosure.

[0015] [Symbol Explanation]

[0016] 100: Layout

[0017] 110: High-speed unit

[0018] 120: Passive Unit

[0019] 200: Circuit Implementation

[0020] 205: Slotted Port

[0021] 205d, 240d: Distance

[0022] 215: Spacing

[0023] 220: First Passive Unit

[0024] 220a, 220b, 220c, 220d: Gate structure

[0025] 225: Second gate pitch

[0026] 230: High-speed unit

[0027] 235: First gate pitch

[0028] 240: Second Passive Unit

[0029] 240a: Gate electrode

[0030] 250: High-speed unit

[0031] 250a: Gate structure

[0032] 260: Passive Unit

[0033] 270: Second High-Speed ​​Unit

[0034] 280, 280a, 280b: n-type channel

[0035] 285: Gate Structure of High-Efficiency Semiconductor Devices

[0036] 290, 290a, 290b: P-type channels

[0037] 295: Gate Structure of Passive Semiconductor Devices

[0038] 300: Circuit Implementation

[0039] 310: Dummy Filled Gate Structure

[0040] 315: Dummy gate width

[0041] 330: First semiconductor device unit

[0042] 360: Second Semiconductor Device Unit

[0043] 385: Gate structure of high-performance semiconductor devices

[0044] 395: Gate Structure of Passive Semiconductor Devices

[0045] 400: Method

[0046] 410, 420, 430, 440: Operations

[0047] 510, 520: First diffusion zone

[0048] 530, 540: Second diffusion zone

[0049] 550: First channel width

[0050] 560: Second channel width

[0051] 570: First gate structure

[0052] 575: Third width

[0053] 580: Second gate structure

[0054] 585: Fourth Width

[0055] 600: Computer System

[0056] 602: Input / Output Interface

[0057] 603: Input / Output Device

[0058] 604: Processor

[0059] 606: Communication infrastructure or bus

[0060] 608: Main Memory

[0061] 610: Secondary Memory

[0062] 612: Hard Disk Drive

[0063] 614: Removable Storage Drive

[0064] 618, 622: Removable storage units

[0065] 620: Interface

[0066] 624: Communication Interface

[0067] 626: Communication Path

[0068] 628: Remote device

[0069] 700: Integrated Circuit Manufacturing System

[0070] 720: Design Studio

[0071] 722: Integrated Circuit Design Layout Diagram

[0072] 730: Covered Room

[0073] 732: Data Preparation

[0074] 734: Mask Manufacturing

[0075] 745: Mask

[0076] 750: Manufacturer

[0077] 752: Wafer Manufacturing

[0078] 753: Semiconductor wafer

[0079] 760: Integrated Circuit Device

[0080] A, B, C, D, E, T, U, V, X, Y, Z: Orbits Detailed Implementation

[0081] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Furthermore, element symbols and / or letters are repeated in various embodiments of this disclosure. This repetition is for simplicity and clarity, unless otherwise stated, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0082] The terms used in this specification generally have their conventional meanings in the art and in the specific context. The use of examples in this specification, including instances of any terms discussed herein, is illustrative only and does not limit the scope or meaning of any exemplary terms or disclosure. Similarly, this disclosure is not limited to the specific embodiments described herein.

[0083] In addition, for ease of description, this document uses spatially relative terms (such as “below,” “under,” “lower,” “above,” “upper,” and the like) to describe the relationship between one element or feature shown in the figures and another. Besides the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatially relative descriptive terms used herein can be interpreted in the same way.

[0084] In some embodiments, the words “about” and “substantially” may mean a value of a given quantity that varies within 20% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of that value). These values ​​are merely examples and are not intended to be limiting. The words “about” and “substantially” may be interpreted by those skilled in the art, in accordance with the teachings herein, as referring to a percentage of that value.

[0085] As used herein, unless the context clearly indicates otherwise, "one" or "the" means both singular and plural forms.

[0086] The word "and / or" when used with a list of two or more items means that any one of the listed items can be used by itself or by any combination of one or more listed items. For example, "A and / or B" means one or both of A and B; in other words, A alone, B alone, or a combination of A and B. "A, B and / or C" means A alone, B alone, C alone, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C.

[0087] The following disclosure relates to optimizing placeholder cells in integrated circuit (IC) layout design. Electronic design automation (EDA) tools can be used to place placeholder cells and dummy fill structures in IC layout design. Placeholder cells can be associated with circuits or devices that implement specific functions in an IC, such as logic functions, analog functions, and other suitable functions. Dummy fill structures do not have specific functions and can be inserted using EDA tools to facilitate downstream processing, such as chemical mechanical polishing (CMP) processes. With technological advancements and the growing demand for hybrid device and circuit structures, the increasing number of placeholder cells and the ability to provide differential arrays of placeholder cells need to accommodate smaller IC layout designs, thus increasing challenges for IC manufacturers. Embodiments disclosed herein address this challenge by introducing differential arrays of placeholder cells with different configurations and / or functions to optimize circuit implementation. Furthermore, providing differential arrays of placeholder cells can minimize the insertion of dummy fill structures using EDA tools.

[0088] Figure 1 This is a schematic diagram of a layout 100 for circuit implementation according to some embodiments of the present disclosure. Layout 100 may include a high-speed unit 110 and a passive unit 120. In some embodiments of the present disclosure, shown... Figure 1 The columns and rows in the diagram represent individual tracks in the integrated circuit layout. As used herein, a track refers to a linear array of layout cells (e.g., layout cells along the x, y, or z axis). For example, according to some embodiments, rows A, B, C, D, and E, and columns Z, Y, X, V, U, and T each represent an individual track. Figure 1 As shown, each track may include at least two different cell types. In some embodiments disclosed herein, the cell type may be a high-speed cell 110 or a passive cell 120.

[0089] In some embodiments disclosed herein, Figure 1 This displays multiple layout units (e.g., high-speed unit 110 and passive unit 120) that are directly adjacent to each other. In some embodiments, Figure 1 The directly adjacent display layout units shown (e.g., high-speed unit 110 and passive unit 120) are adjacent to each other in the same orientation along the horizontal and vertical directions (e.g., the x and y directions, respectively). For example, the right side of the passive unit 120 occupying row A and column Z is adjacent to the left side of the high-speed unit 110 occupying row A and column Y, and the bottom side of the passive unit 120 occupying row A and column Z is adjacent to the top side of the passive unit 120 occupying row B and column Z.

[0090] According to some embodiments, layout 100 may include multiple semiconductor device units (e.g., high-speed unit 110 and passive unit 120). In some embodiments, each of the semiconductor device units may be a layout representation of a single transistor device, such as an n-type field-effect transistor (FET) device or a p-type field-effect transistor device. FET devices (e.g., n-type and p-type FET devices) may be planar metal-oxide-semiconductor (MOSFET) devices, finFET devices, gate-all-around (GAA) FET devices, any other suitable type of FET device, or any combination thereof. In some embodiments, each semiconductor device unit may be a layout representation of one or more transistor devices, such as logic devices (e.g., inverter logic devices, NAND logic devices, NOR logic devices, and XOR logic devices). Further details and embodiments of layout 100 and each semiconductor device unit are described below.

[0091] In some embodiments disclosed herein, depending on the circuitry and / or system, layout 100 may include any desired number of high-speed units 110 or passive units 120. Although some examples may depict interleaved high-speed units 110 and passive units 120, the high-speed units 110 and passive units 120 do not need to be arranged in an interleaved configuration. For example, a high-speed unit 110 may be adjacent to another high-speed unit 110, etc. Similarly, a passive unit 120 may be adjacent to another passive unit 120, etc.

[0092] In some embodiments disclosed herein, high-speed unit 110 may include a high-performance computing (HPC) product. For example, the HPC product may be a fin field-effect transistor, a gate-all-around transistor, a nanosheet, a two-dimensional material device, a back-end-of-line (BEOL) device, high-performance memory, an adder, a backplane, a graphics engine, a level shifter circuit, an inverter logic device, a NAND logic device, a three-dimensional NAND logic device, an n-type metal oxide semiconductor (NMOS) device, a p-type metal oxide semiconductor (PMOS) device, a NOR logic device, an XOR logic device, any other suitable analog / logic device, or a combination thereof. In some embodiments disclosed herein, high-speed unit 110 may be a unit that consumes more energy when compared to passive unit 120.

[0093] In some embodiments disclosed herein, the passive unit 120 may include a resistor, capacitor, diode (e.g., Zener diode, light-emitting diode, diode bridge circuit, rectifier circuit, or combination thereof), inductor, crystal, oscillator, relay, switch, connector, amplifier circuit, memory, filter, or any combination thereof.

[0094] Layout 100 may include one or more semiconductor device units that include analog functions, logic functions, or combinations thereof. For example, circuit implementations in layout 100 may include level shifter circuitry, amplifier circuitry, passive devices (e.g., resistors and capacitors), inverter logic devices, NAND logic devices, NOR logic devices, XOR logic devices, any other suitable analog / logic devices, or combinations thereof. In some embodiments, circuit implementations may be accomplished by connecting multiple semiconductor device units (e.g., via one or more interconnects). Further details and embodiments of connecting multiple semiconductor device units to perform specific analog and / or logic circuit functions are described below.

[0095] Figure 2A This is a diagram illustrating the layout of circuit implementation 200 according to some embodiments. In some embodiments, circuit implementation 200 can be used in... Figure 1 In the layout 100, and can be represented as, for example, multiple field-effect transistor devices, such as multiple n-type field-effect transistor devices and multiple p-type field-effect transistor devices sharing a common gate structure, for example... Figure 2AThe gate structure 220a is shown. In some embodiments disclosed herein, the gate structure includes a gate electrode and a gate dielectric. In some embodiments disclosed herein, the gate electrode may include a conductive filling feature. For example, the conductive filling feature may be any one of cobalt, titanium, titanium nitride (TiN), tungsten, copper, aluminum, gallium, zinc, ruthenium, molybdenum, indium tin oxide, or a metal compound. In some embodiments disclosed herein, the gate dielectric may be any one of hafnium oxide (HfO), hafnium dioxide (HfO2), silicon dioxide, tantalum oxide (TaO), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), silicon nitride (SiN), zirconium oxide (ZrO), zirconium dioxide (ZrO2), titanium oxide (TiO), or lanthanum (La).

[0096] In some embodiments of this disclosure, the gate dielectric may be electrically coupled to the input / output port of the slotted device. For example, slotted port 205 may be used for electrical and / or communication coupling of one system to another. Slotted port 205 may be electrically coupled to the silicon-germanium (SiGe) layer of the semiconductor device via a silicide layer. In some embodiments of this disclosure, slotted port 205 may be connected to the epitaxially grown silicon layer of the semiconductor device via a silicide layer. In some embodiments of this disclosure, depicted in Figure 1 The layout 100 can be an individual system. Therefore, the slot port 205 provides the ability to connect one system to another or more systems. In some embodiments, the slot port 205 and the gate electrode 240a are separated by a distance of up to about 100 nanometers (e.g., a distance 205d between the gate electrode 240a and the slot port 205, which is about 100 nanometers, about 90 nanometers, about 80 nanometers, about 70 nanometers, about 60 nanometers, or about 50 nanometers).

[0097] In some embodiments disclosed herein, the gate electrode may have substantially rectangular terminations. In some embodiments, the rectangular terminations may facilitate electrical coupling between the gate electrode and the slotted port. In some embodiments, the substantially rectangular terminations facilitate a connection from a first gate electrode to a second gate electrode, for example, electrically coupling a first cell to a second cell. In some embodiments, the substantially rectangular terminations are used to connect a high-performance semiconductor device gate structure to a passive semiconductor gate structure. Similarly, substantially rectangular terminations may be used to connect two passive semiconductor device gate structures, and / or substantially rectangular terminations may be used to connect two high-performance semiconductor device gate structures.

[0098] In some embodiments disclosed herein, the distance between the first gate electrode terminal and the second gate electrode terminal is less than or equal to 100 nanometers. For example, the first gate electrode terminal is separated from the second gate electrode terminal by a distance of approximately 100 nanometers, approximately 90 nanometers, approximately 80 nanometers, approximately 70 nanometers, approximately 60 nanometers, or approximately 50 nanometers, for a distance of 240d.

[0099] See Figure 2A The circuit implementation 200, including the high-speed unit 110 and the passive unit 120, can simultaneously occupy the track of the common device (e.g., Figure 1 (A to E or Z to T). For example Figure 2A As shown, track A of the device includes a first passive unit 220, a high-speed unit 230, and a second passive unit 240. Similarly, track B includes a high-speed unit 250, a passive unit 260, and a second high-speed unit 270. In some embodiments disclosed herein, track Z includes a first passive unit 220 and a high-speed unit 250, track Y includes a high-speed unit 230 and a passive unit 260, and track X includes a second passive unit 240 and a second high-speed unit 270.

[0100] n-type channel 280 and p-type channel 290 are also shown in Figure 2A In some embodiments disclosed herein, the channel may occupy a horizontal track (e.g., in...). Figure 1 The track AE is depicted in the image. In some embodiments, the channel may occupy a vertical track (e.g., in the image). Figure 1 The orbit depicted in the image is ZT.

[0101] In some embodiments disclosed herein, the widths of the n-type channel 280 and the p-type channel 290 may be based on the overall layout (e.g., in...). Figure 1 The layout 100 depicted is determined by diffusion design rules associated with technology nodes and / or semiconductor manufacturing processes. For example, the width may be determined based on design rules for device types intended to occupy specific cells (e.g., high-performance semiconductor devices occupy high-speed cells 110 or passive semiconductor devices occupy passive cells 120).

[0102] In some embodiments disclosed herein, the n-type channel 280 and the p-type channel 290 may have different channel widths to accommodate device types occupying a particular cell. For example, the first semiconductor structure may have a first channel width 550 (see...). Figure 5 The second semiconductor structure may have a second channel width 560. In some examples, the first channel width 550 may be greater than the second channel width 560. In some embodiments disclosed herein, the first semiconductor structure (e.g., a high-performance semiconductor device occupying high-speed cell 110) may have an n-type channel 280 and a p-type channel 290, the width of which is greater than the width of the n-type channel 280 and p-type channel 290 associated with the second semiconductor structure (e.g., a passive semiconductor device occupying passive cell 120).

[0103] like Figure 2A As shown, the first semiconductor structure (e.g., a high-speed cell) includes an n-type channel 280a and a p-type channel 290a, which extend along the x-axis and have a width greater than that of the n-type channel 280b and p-type channel 290b associated with the second semiconductor structure (e.g., a passive cell). Figure 2A In this embodiment, the channels extend along the x-axis, and the channel widths differ along the y-axis. In some embodiments disclosed herein, the wider n-type channel 280a and the wider p-type channel 290a can accommodate a larger amount of current consumed by the high-efficiency semiconductor device occupying the high-speed cell 110. Similarly, the wider n-type channel 280a and p-type channel 290a can be configured to provide a larger amount of current to the high-efficiency semiconductor device occupying the high-speed cell 110.

[0104] In some embodiments, the heights of the n-type channel 280 and p-type channel 290 along the z-axis can be based on the overall layout (e.g., in...). Figure 1 The layout 100 depicted is determined by diffusion design rules associated with technology nodes and / or semiconductor manufacturing processes. Figure 2A In this design, the channels extend along the x-axis, and their heights vary along the z-axis. For example, the z-axis height (or depth) can be determined based on design rules for the relative width and spacing of specific diffusion layers. The minimum height can be based on the width of the diffusion layer (e.g., the x-axis widths of n-type channels 280a and p-type channels 290a are associated with high-speed unit 110, and the x-axis widths of n-type channels 280b and p-type channels 290b are associated with passive unit 120).

[0105] In some embodiments disclosed herein, such as in Figure 2BAs illustrated, high-speed cell 230 includes an n-type channel 280a and a p-type channel 290a, the z-axis channel height of which is greater than that of the n-type channel 280b and p-type channel 290b associated with the first passive cell 220. In some embodiments disclosed herein, the larger channel height of the n-type channel 280a and the larger channel height of the p-type channel 290a can accommodate a larger amount of current consumed by the high-performance semiconductor device occupying high-speed cell 110. Similarly, the larger channel height of the n-type channel 280a and the larger channel height of the p-type channel 290a can be configured to provide a larger amount of current to the high-performance semiconductor device occupying high-speed cell 110.

[0106] exist Figure 2A The diagram also shows a high-performance semiconductor device gate structure 285 and a passive semiconductor device gate structure 295. In some embodiments disclosed herein, the gate structure may occupy a y-axis channel (e.g., in...). Figure 1 The orbital ZT depicted in the diagram. In some embodiments disclosed herein, the gate structure may occupy the x-axis channel (e.g., in...). Figure 1 The orbit depicted in the image is AE.

[0107] In some embodiments disclosed herein, the high-performance semiconductor device gate structure 285 and the passive semiconductor device gate structure 295 may have different gate widths to accommodate device types occupying specific cells. Figure 2A In this configuration, the gate structure extends along the y-axis and has different gate widths in the x-axis direction. For example, the high-performance semiconductor device gate structure 285 may have a first gate width, and the passive semiconductor device gate structure 295 may have a second gate width. In some embodiments, the first gate width may be greater than the second gate width. In some embodiments, the high-performance semiconductor device occupying the high-speed cell 110 may have a high-performance semiconductor device gate structure 285 with a wider width than the passive semiconductor device gate structure 295.

[0108] In some embodiments, the spacing 215 between the n-type channel 280 and the p-type channel 290 may be based on the overall layout (e.g., in...). Figure 1 The layout 100 depicted is determined by polysilicon design rules associated with technology nodes and / or semiconductor manufacturing processes. For example, the pitch 215 may be determined based on design rules for the relative width and spacing of specific polysilicon layers, such as sacrificial layers or dummy gate layers.

[0109] In some embodiments disclosed herein, the high-performance semiconductor device gate structure 285 and the passive semiconductor device gate structure 295 may have different gate pitches to accommodate device types occupying a particular cell. For example, a first semiconductor structure may have a first gate pitch 235, and a second semiconductor structure may have a second gate pitch 225. In some embodiments, the first gate pitch 235 may be larger than the second gate pitch 225. In some embodiments, the high-performance semiconductor device occupying the high-speed cell 110 may have a high-performance semiconductor device gate structure 285 having a larger pitch than the passive semiconductor device gate structure 295.

[0110] like Figure 2A As further shown, the high-performance semiconductor device gate structure 285 and the passive semiconductor device gate structure 295 in each unit can be interconnected. For example, the gate structure of the first unit can be electrically coupled to the gate structure of the second unit. In some embodiments disclosed herein, the high-performance semiconductor device gate structure 285 of the second high-speed unit 270 in track B can be electrically coupled to the passive semiconductor device gate structure 295 of the second passive unit 240 occupying track A.

[0111] exist Figure 2A In circuit implementation 200, each cell may have multiple gate structures. For example, the first passive cell 220 includes four separate gate structures 220a, 220b, 220c, and 220d. In some embodiments disclosed herein, any of the gate structures 220a, 220b, 220c, or 220d may be dummy gates. Any of the gate structures 220a, 220b, 220c, or 220d may also be electrically coupled to the gate structure of another cell, such as the gate structure 250a of the high-speed cell 250.

[0112] In some embodiments disclosed herein, one or more dummy fill structures are inserted into areas of layout 100 that are not occupied by high-performance semiconductor devices or passive semiconductor devices. The dummy fill structures have no particular function and can be inserted by electronic design automation (EDA) tools to facilitate layout planarization during semiconductor manufacturing processes, such as chemical mechanical polishing (CMP) processes. In some embodiments, the areas where EDA tools can insert dummy fill structures are limited to cell regions not occupying layout 100.

[0113] In some embodiments disclosed herein, the dummy fill structure may have different gate widths. For example, the dummy fill structure may have a gate width substantially equal to a first gate width (e.g., the gate width of gate structures 220a, 220b, 220c, or 220d of any high-speed semiconductor structure). In some embodiments, the dummy fill structure may have a gate width substantially equal to a second gate width (e.g., the second gate width corresponding to a passive semiconductor structure).

[0114] In some embodiments disclosed herein, Figure 3 The layout for circuit implementation 300 is shown. In some embodiments of this disclosure, the high-performance semiconductor device gate structure 385 and the passive semiconductor device gate structure 395 in each cell may be isolated from each other. For example, the gate structure of the first cell may be electrically decoupled from the gate structure of the second cell. In some embodiments of this disclosure, the high-performance semiconductor device gate structure 385 of the first semiconductor device cell 330 (e.g., a high-speed cell) in track A may be electrically decoupled from the passive semiconductor device gate structure 395 of the second semiconductor device cell 360 (e.g., a passive cell) occupying track B.

[0115] In some embodiments disclosed herein, units (e.g., high-speed unit 110 or passive unit 120) may be electrically coupled to a reference voltage. For example, according to some embodiments, at least one first semiconductor device gate is coupled to a reference voltage of about 0.5 volts to about 3 volts. The reference voltage may be about 0.5 volts, about 0.6 volts, 0.7 volts, about 0.8 volts, 0.9 volts, about 1 volt, 1.1 volts, about 1.2 volts, 1.3 volts, about 1.4 volts, 1.5 volts, about 1.6 volts, 1.7 volts, about 1.8 volts, 1.9 volts, about 2 volts, 2.1 volts, about 2.2 volts, 2.3 volts, about 2.4 volts, 2.5 volts, about 2.6 volts, 2.7 volts, about 2.8 volts, about 2.9 volts, or about 3 volts. In some embodiments, the reference voltage can be either the voltage drain (VDD) or the voltage source (VSS). Therefore, the high-performance semiconductor device gate structure 385 can be electrically coupled to either the drain voltage or the source voltage. In some embodiments disclosed herein, the dummy-fill gate 310 can be electrically coupled to the reference voltage. For example, the dummy-fill gate 310 can be coupled to either the drain voltage or the source voltage.

[0116] Some embodiments disclosed herein describe methods for providing hybrid units. Figure 4The diagram illustrates a flowchart of a layout creation method 400 according to some embodiments disclosed herein. For illustrative purposes, the operation of method 400 will be described with reference to [reference needed]. Figure 1 , 2A Methods 3 and 5 are described. The operations of method 400 may be performed in different orders or not at all depending on the specific application. Furthermore, it is understood that additional operations may be provided before, between, and after method 400, and other operations may only be briefly described here.

[0117] In operation 410, a first diffusion area is set in the selected layout area (e.g., drawn on...). Figure 1 (High-speed unit 110 or passive unit 120 in the middle). For example, the first diffusion region can be an n-type channel 280 or a p-type channel 290 occupying the high-speed unit, for example. Figure 2A The high-speed unit 230 is depicted in the image. In some embodiments, the second diffusion region may be an n-type channel 280 or a p-type channel 290 occupying the passive unit, for example... Figure 2A The second passive unit 240 is depicted in the text.

[0118] In operation 420, a second diffusion area is set in the selected layout area (e.g., drawn on...). Figure 1 (High-speed unit 110 or passive unit 120 in the middle). For example, the first diffusion region can be an n-type channel 280 or a p-type channel 290 occupying the high-speed unit, for example. Figure 2A The high-speed unit 230 is depicted in the image. In some embodiments, the second diffusion region may be an n-type channel 280 or a p-type channel 290 occupying the passive unit, for example... Figure 2A The second passive unit 240 is depicted in the text.

[0119] See now Figure 5 The first diffusion region 510 can be an n-type channel or a p-type channel with a first channel width 550. Similarly, the second diffusion region 530 can be an n-type channel or a p-type channel with a second channel width 560. Figure 5 In this embodiment, the first diffusion regions 510 and 520 and the second diffusion regions 530 and 540 extend along the x-axis, and the first channel width 550 and the second channel width 560 are different in the y-axis direction. In some embodiments disclosed herein, the first channel width 550 of the first diffusion regions 510 and 520 may be greater than the second channel width 560 of the second diffusion regions 530 and 540. In some embodiments disclosed herein, the first channel width 550 may be less than the second channel width 560.

[0120] Now arriving Figure 4In operation 420, method 400 may include depositing a second diffusion region 530 such that the first diffusion region 510 is connected to the second diffusion region 530. For example, the first diffusion region 510 may be electrically coupled to the second diffusion region 530. In some embodiments disclosed herein, the first diffusion region 510 may be a high-speed cell (e.g., in...). Figure 1 The high-speed unit 110 shown in the image has an n-type channel, and the second diffusion region 530 can be a passive unit (e.g., in...). Figure 1 The passive unit 120 shown in the image has an n-type channel. In some embodiments, the first diffusion region 510 may be a high-speed unit (e.g., in...). Figure 1 The high-speed unit 110 shown in the image has a p-type channel, and the second diffusion region 530 can be a passive unit (e.g., in...). Figure 1 The passive unit 120 shown in the figure has a p-type channel. The first diffusion region 510 can be a charge-carrying channel of a high-performance semiconductor device, and the second diffusion region 530 can be a charge-carrying channel of a passive semiconductor device.

[0121] In some embodiments disclosed herein, in operation 420, the second diffusion region 530 is deposited such that the second diffusion region 530 connected to the first diffusion region 510 can serve as a basis for creating circuit tracks (e.g., depicted in...). Figure 1 In this configuration, the x-axis leaves a track AE and / or the y-axis leaves a track ZT. For example, the connection of at least one first diffusion region 510 to a second diffusion region 530 can create extensions through multiple units adjacent to each other along specific tracks (e.g., set in...). Figure 1 At least one first n-type channel of the high-speed unit 110 and the passive unit 120 in the x-axis track.

[0122] In some embodiments of this disclosure, in operation 430, the method includes disposing a first gate structure 570 over a first diffusion region 510. The first gate structure 570 may have a third width 575. In some embodiments of this disclosure, such as Figure 1 For example, the first gate structure 570 and the third width 575 may be the gate structure and gate width of a high-performance semiconductor device occupying the high-speed cell 110. In some embodiments disclosed herein, in operation 440, the method also includes disposing a second gate structure 580 over the second diffusion region 530. The second gate structure 580 may have a fourth width 585. In some embodiments, such as in Figure 1 As depicted in the diagram, the second gate structure 580 and the fourth width 585 can be the gate structure and gate width of a passive semiconductor device occupying the passive cell 120.

[0123] Similarly, some layout cells may have a dummy-fill structure gate 310, which has, for example, Figure 3The dummy gate width 315 is shown. In some embodiments disclosed herein, the dummy gate width 315 may be in... Figure 5 The fifth width shown is distinct from the third width 575 and / or the fourth width 585. In some embodiments, the dummy gate width 315 may be substantially similar to the third width 575 and / or the fourth width 585.

[0124] In some embodiments disclosed herein, during operation 440, a passive semiconductor device gate structure 395 is deposited (as in...). Figure 3 As shown in the diagram, the passive semiconductor device gate structure 395 is connected to the high-performance semiconductor device gate structure 385. In some embodiments disclosed herein, the method may include decoupling the passive semiconductor device gate structure 395 from the high-performance semiconductor device gate structure 385. For example, a first gate structure of a first cell may be coupled to a first gate structure of a second cell, and a second gate structure of the first cell may be decoupled to a second gate structure of the second cell. For example, a high-performance semiconductor device occupying a high-speed cell (first semiconductor device cell 330) may have a high-performance semiconductor device gate structure 385 decoupled from the passive semiconductor device gate structure 395 of the passive cell (second semiconductor device cell 360). In circuit implementation, the decoupling of the gate structures may be performed as expected.

[0125] In some embodiments of this disclosure, at least one first gate structure or at least one second gate structure may be electrically coupled to a reference voltage. For example, at least one first gate structure may be electrically coupled to a drain voltage or a source voltage. Similarly, at least one second gate structure may be electrically coupled to a drain voltage or a source voltage. In some embodiments of this disclosure, the method may further include providing a dummy fill structure in the layout region. For example, the dummy fill structure may be disposed above the first diffusion region 510 and / or the second diffusion region 530.

[0126] Among other things, the advantages of the method 400 and embodiments described herein are optimization of power consumption and clock speed in integrated circuit layout design. This optimization is advantageous for at least two reasons. First, by manufacturing layout cells based on hybrid layout cells (e.g., mixing high-speed cells and passive cells on a single diffusion region track), the efficiency of the circuit is increased because the passive cells can utilize a larger amount of current supplied to the high-speed cells without negatively impacting the performance of the high-speed cells. As previously mentioned, dummy fill structures may not have electrical or electronic functions, but can help facilitate some downstream processes, such as chemical mechanical polishing.

[0127] Figure 6This is a schematic diagram of a computer system 600, which is exemplified according to some embodiments of the present invention, disclosing various embodiments. The computer system 600 can be any well-known computer capable of performing the functions and operations described herein. For example, the computer system 600 may indicate a placement cell type and connect placement cells within placement cells to provide circuit implementation in integrated circuit placement design use, such as electronic design automation tools, but is not limited thereto. The computer system 600 may be used, for example, to perform one or more operations in method 400, which describes an example method for semiconductor device cell placement.

[0128] Computer system 600 includes one or more processors (also referred to as central processing units), such as processor 604. Processor 604 is connected to communication infrastructure or bus 606. Computer system 600 also includes input / output devices 603, such as a monitor, keyboard, pointing device, etc., which communicate with the communication infrastructure or bus 606 via input / output interface 602. Electronic design automation tools can receive instructions through input / output devices 603 to perform the functions and operations described herein, such as... Figure 4 Method 400. The computer system 600 also includes a main memory (or primary memory) 608, such as random access memory (RAM). The main memory 608 may include one or more layers of cache memory. The main memory 608 has memory control logic (e.g., computer software) and / or data. In some embodiments, the control logic (e.g., computer software) and / or data may include the aforementioned related... Figure 4 Method 400 is one or more operations.

[0129] The computer system 600 may also include one or more secondary storage devices or secondary memory 610. Secondary memory 610 may include, for example, a hard disk drive 612 and / or a removable storage device or removable storage drive 614. The removable storage drive 614 may be a floppy disk drive, magnetic tape drive, optical disc drive, optical storage device, magnetic tape backup device, and / or any other storage device / drive.

[0130] The removable storage drive 614 can interact with the removable storage unit 618. The removable storage unit 618 includes a computer-usable or readable storage device on which computer software (control logic) and / or data is stored. The removable storage unit 618 can be a floppy disk, magnetic tape, optical disc, digital versatile optical disc (DVD), optical storage disc, and / or any other computer data storage device. The removable storage drive 614 reads from and / or writes to the removable storage unit 618 in a well-known manner.

[0131] According to some embodiments, secondary memory 610 may include other means, tools, or other methods for accessing computer system 600 to allow computer programs and / or other instructions and / or data. These means, tools, or other methods may include, for example, removable storage unit 622 and interface 620. Examples of removable storage unit 622 and interface 620 may include program cartridges and cartridge interfaces (e.g., program cartridges and cartridge interfaces found in audio-visual gaming devices), removable memory chips (e.g., erasable programmable read-only memory (EPROM) or programmable read-only memory (PROM)) and associated slots, memory cards and Universal Serial Bus (USB) ports, memory cards and associated memory card slots, and / or any other removable storage unit and associated interface. In some embodiments, secondary memory 610, removable storage unit 618, and / or removable storage unit 622 may include the aforementioned related methods. Figure 4 Method 400 is one or more operations.

[0132] Computer system 600 may further include a communication interface 624 or a network interface. Communication interface 624 enables computer system 600 to communicate and interact with any combination of remote devices, remote networks, remote entities, etc. (individually and collectively referred to as remote device 628). For example, communication interface 624 may allow computer system to communicate with remote device 628 over communication path 626, which may be wired and / or wireless and may include any local area network (LAN), wide area network (WAN), internet, etc. Control logic and / or data may be transmitted to and from computer system 600 via communication path 626.

[0133] The operations described in the preceding embodiments can be implemented in a wide variety of configurations and structures. Therefore, some or all of the operations described in the preceding embodiments, such as... Figure 4Method 400 can be implemented in hardware, software, or both. In some embodiments, a tangible manufactured instrument or object containing tangible computer-usable or readable multimedia with control logic (software) stored thereon is also intended herein to be a computer program product or program storage device. This includes, but is not limited to, computer system 600, primary memory 608, secondary memory 610, and removable storage units 618 and 622, and manufactured objects embodying combinations of the foregoing items. Such control logic, when executed by one or more data processing devices (computer system 600), causes these data processing devices to operate as described herein.

[0134] Figure 7 This is a diagram illustrating an integrated circuit manufacturing system 700 and associated integrated circuit manufacturing processes according to some embodiments. In some embodiments, the layout units described herein, such as... Figure 1 The layout 100 and high-speed unit 110 and / or passive unit 120 can be manufactured using integrated circuit manufacturing system 700.

[0135] The integrated circuit manufacturing system 700 includes a design room 720, a mask room 730, and an integrated circuit manufacturing plant / manufacturer (fab) 750—each of these interacts with the others in the design, development, and manufacturing cycle relating to the manufacture of an integrated circuit device 760. The design room 720, mask room 730, and manufacturer 750 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. Each of the design room 720, mask room 730, and manufacturer 750 interacts with the others and provides services to and / or receives services from the others. In some embodiments, two or more of the design room 720, mask room 730, and manufacturer 750 coexist in shared facilities and use shared resources.

[0136] Design studio 720 produces integrated circuit design layout 722. Integrated circuit design layout 722 includes various geometric patterns, such as those shown in... Figure 1The pattern in layout 100. The geometric pattern corresponds to the pattern of the metal, oxide, or semiconductor layers that constitute the various elements in the integrated circuit device 760 to be manufactured. The layers are bonded to form the features of the various integrated circuits. For example, a portion of the integrated circuit design layout 722 includes various integrated circuit features, such as active regions, gate electrodes, source and drain electrodes, and conductive segments or vias for interlayer interconnection, which will be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design room 720 performs appropriate design procedures to form the integrated circuit design layout 722. The design procedures include one or more logic designs, physical designs, and place and route designs. The integrated circuit design layout 722 may be presented in one or more data files having information on the geometric pattern. For example, the integrated circuit design layout 722 may be represented in GDSII file format or DFII file format.

[0137] Mask chamber 730 includes data preparation 732 and mask fabrication 734. Mask chamber 730 fabricates a mask 745 (or master mask) using an integrated circuit design layout 722 for fabricating integrated circuit devices 760 on various layers. Mask chamber 730 performs mask data preparation 732, where the integrated circuit design layout 722 is converted into a representative data file (RDF). The prepared mask data provides the representative data file to mask fabrication 734. Mask fabrication 734 includes a mask writer, such as mask 745 or semiconductor wafer 753, that converts the representative data file into a pattern on a substrate. The integrated circuit design layout 722 can be manipulated by mask data preparation 732 to conform to the specific characteristics of the mask writer and / or the needs of manufacturer 750. Figure 7 In this diagram, data preparation 732 and mask manufacturing 734 are shown as separate elements. In some embodiments, data preparation 732 and mask manufacturing 734 may be collectively referred to as "mask data preparation".

[0138] In some embodiments, data preparation 732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, or other process effects. The OPC adjustment integrated circuit design layout is shown in Figure 722. In some embodiments, data preparation 732 includes further resolution enhancement techniques (RETs), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masking, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) can be used, which treats optical proximity correction as an inverse imaging problem.

[0139] In some embodiments, data preparation 732 includes a mask rule checker (MRC) that uses a set of mask creation rules, including geometric and / or linearity constraints, to check whether the integrated circuit design layout 722 has undergone optical proximity correction to ensure sufficient edges to account for variability in the semiconductor manufacturing process. In some embodiments, the mask rule checker modifies the integrated circuit design layout 722 to compensate for constraints during mask manufacturing 734, and may revert some modifications performed by optical proximity correction to meet the mask creation rules.

[0140] In some embodiments, data preparation 732 includes lithography process checking (LPC), which simulates the processes implemented by manufacturer 750 to manufacture integrated circuit device 760. Lithography process checking simulates this process based on integrated circuit design layout 722 to create a simulated manufacturing apparatus, such as integrated circuit device 760. Process parameters in the lithography process checking simulation may include parameters associated with various processes in the integrated circuit manufacturing cycle, parameters associated with tools used to manufacture integrated circuits, and / or other aspects of the manufacturing process. Lithography process checking considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), and other suitable factors. In some embodiments, after the simulated manufacturing apparatus has been created by lithography process checking, and if the simulated apparatus does not meet design rules, optical proximity correction and / or mask rule checkers are repeated to further refine the integrated circuit design layout 722.

[0141] In some embodiments, data preparation 732 includes additional features, such as modifying the logic operation (LOP) of the integrated circuit design layout 722 according to manufacturing rules. Furthermore, the process of applying the integrated circuit design layout 722 during data preparation 732 may be performed in a different order than described above.

[0142] Following data preparation 732 and during mask fabrication 734, mask 745 is fabricated based on a modified integrated circuit design layout 722. In some embodiments, mask fabrication 734 includes performing one or more lithography exposures based on the integrated circuit design layout 722. In some embodiments, an electron beam (e-beam) or multiple electron beam mechanisms are used based on the modified integrated circuit design layout 722 to form a pattern on mask 745.

[0143] Mask 745 can be formed using various techniques. In some embodiments, mask 745 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, can be used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer. The radiation beam is blocked by the opaque areas and transmitted through the transparent areas. For example, a binary mask version of mask 745 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask.

[0144] In some embodiments, a phase-shift technique is used to form a mask 745. In the phase-shift mask (PSM) version of mask 745, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. For example, the phase-shift mask may be an attenuated phase-shift mask or an alternating phase-shift mask.

[0145] The mask produced by mask fabrication 734 is used in a variety of processes. For example, the mask can be used in ion implantation processes to form various doped regions in semiconductor wafer 753, in etching processes to form various etched regions in semiconductor wafer 753, and / or in other suitable processes.

[0146] Manufacturer 750 includes wafer fabrication 752. Manufacturer 750 may include one or more manufacturing facilities for manufacturing various integrated circuit products. In some embodiments, manufacturer 750 is a semiconductor wafer foundry. For example, there may be manufacturing facilities for front-end manufacturing of integrated circuit products (front-end-of-line (FEOL) manufacturing), a second manufacturing facility for providing back-end manufacturing for interconnection and packaging of integrated circuit products (back-end process manufacturing), and a third manufacturing facility for the wafer foundry to provide other services.

[0147] Manufacturer 750 uses a mask 745, manufactured by mask chamber 730, to fabricate integrated circuit device 760. In some embodiments, semiconductor wafer 753 is fabricated by manufacturer 750 using mask 745 to form integrated circuit device 760. In some embodiments, integrated circuit fabrication includes performing one or more lithography exposures based on integrated circuit design layout 722. Semiconductor wafer 753 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 753 further includes doped regions, dielectric features, multilayer interconnects, and other suitable features.

[0148] The disclosed embodiments relate to optimizing placement cells in integrated circuit layout design. With advancements in technology and the corresponding increase in demand for integrated circuits, there is a need to increase the number of placement cells to accommodate smaller integrated circuit layout designs, thus increasing the challenges of integrated circuit manufacturing. The embodiments disclosed herein address this challenge by employing placement cells with different configurations to optimize circuit implementation in integrated circuit layout design while minimizing the insertion of dummy fill structures using electronic design automation tools.

[0149] The embodiments disclosed herein describe a layout including a first semiconductor structure having a first channel and a second semiconductor structure having a second channel, the first channel having a first channel width and the second channel having a second channel width different from the first channel width. The first channel and the second channel are in contact with each other. In one or more of the foregoing and following embodiments, the first semiconductor structure includes a high-speed performance semiconductor device. In one or more of the foregoing and following embodiments, the second semiconductor structure includes a passive semiconductor device. In one or more of the foregoing and following embodiments, the layout further includes a dummy gate having a dummy gate width. In one or more of the foregoing and following embodiments, the dummy gate width is substantially similar to the first channel gate width of the first semiconductor structure or the second channel gate width of the second semiconductor structure. In one or more of the foregoing and following embodiments, the first gate of the first semiconductor structure is coupled to the second gate of the second semiconductor structure. In one or more of the foregoing and following embodiments, the first gate of the first semiconductor structure is decoupled to the second gate of the second semiconductor structure. In one or more of the foregoing and following embodiments, the gate of the second semiconductor structure is coupled to a reference voltage, wherein the reference voltage is a drain voltage or a source voltage. In one or more of the foregoing and following embodiments, the first semiconductor structure includes a first gate spacing between a first n-type channel and a first p-type channel, and the second semiconductor structure includes a second gate spacing between a second n-type channel and a second p-type channel. In one or more of the foregoing and following embodiments, the first channel height and the first channel width of the first channel are different from the second channel height and the second channel width of the second channel, respectively, and the first gate width and the first gate spacing of the first semiconductor structure are different from the second gate width and the second gate spacing of the second semiconductor structure, respectively.

[0150] The embodiments disclosed herein describe a first semiconductor structure having a first gate, a second semiconductor structure having a second gate, the first gate having a first gate width, and the second gate having a second gate width different from the first gate width. The first gate and the second gate are in contact with each other. In one or more of the foregoing and following embodiments, a dummy gate has a dummy gate width. In one or more of the foregoing and following embodiments, the first semiconductor structure has a first gate spacing between a first n-type channel and a first p-type channel, and the second semiconductor structure has a second gate spacing between a second n-type channel and a second p-type channel. In one or more of the foregoing and following embodiments, the first channel height, first channel width, first gate width, and first gate spacing of the first semiconductor structure are different from the second channel height, second channel width, second gate width, and second gate spacing of the second semiconductor structure, respectively. In one or more of the foregoing and following embodiments, the gate of the second semiconductor structure is coupled to a reference voltage, wherein the reference voltage is a drain voltage or a source voltage.

[0151] The embodiments disclosed herein describe a first semiconductor device unit having a first gate, a second semiconductor device unit having a second gate, the first gate having a first gate width, and the second gate having a second gate width different from the first gate width. The first gate and the second gate are in contact with each other. In one or more of the foregoing and following embodiments, a dummy gate has a dummy gate width. In one or more of the foregoing and following embodiments, the first semiconductor device unit has a first gate spacing between a first n-type channel and a first p-type channel, and the second semiconductor device unit has a second gate spacing between a second n-type channel and a second p-type channel. In one or more of the foregoing and following embodiments, the first channel height, first channel width, first gate width, and first gate spacing of the first semiconductor device unit are different from the second channel height, second channel width, second gate width, and second gate spacing of the second semiconductor device unit, respectively. In one or more of the foregoing and following embodiments, the gate of the second semiconductor device unit is coupled to a reference voltage, wherein the reference voltage is a drain voltage or a source voltage.

[0152] The embodiments disclosed herein describe a method including providing a first diffusion region in a layout region and providing a second diffusion region in the layout region. The first diffusion region may have a first diffusion region width, and the second diffusion region may have a second diffusion region width different from the first diffusion region width. The method further includes depositing the second diffusion region such that the second diffusion region is connected to the first diffusion region. In one or more of the foregoing and following embodiments, the method further includes providing a first gate structure above the first diffusion region, wherein the first gate structure has a third width; and providing a second gate structure above the second diffusion region adjacent to the first diffusion region, wherein the second gate structure has a fourth width different from the third width, wherein the second gate structure is connected to the first gate structure. In one or more of the foregoing and following embodiments, the method further includes coupling at least one of the first gate structure and the second gate structure to a reference voltage, wherein the reference voltage is a drain voltage or a source voltage. In one or more of the foregoing and following embodiments, the method further includes providing a dummy fill structure in the layout region. In one or more of the foregoing and following embodiments, the first gate structure and the second gate structure are decoupled.

[0153] The embodiments disclosed herein describe a first semiconductor structure including a first channel extending along a first axis and a first gate electrode extending along a second axis, wherein the first channel has a first channel width and the first gate electrode has a first gate width; a second semiconductor structure including a second channel extending along a first axis and a second gate electrode extending along a second axis, wherein the second channel has a second channel width that is different from the first channel width; the first channel and the second channel are in contact with each other; and the second gate electrode has a second gate width that is different from the first gate width.

[0154] It should be understood that the detailed description, and not the summary of the disclosure, is intended to explain the scope of the patent. The summary of the disclosure may describe one or more, but not all, possible embodiments of this disclosure conceived by the inventor, and therefore is not intended to limit the scope of the appended patent in any way.

[0155] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this application. Those skilled in the art should understand that they can readily use this application as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this application, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this application.

Claims

1. An integrated circuit structure, characterized in that, Include: A first semiconductor structure having a first channel having a first channel width; and A second semiconductor structure having a second channel having a width different from that of the first channel, wherein the first channel and the second channel are in contact with each other.

2. The integrated circuit structure as described in claim 1, characterized in that, It also includes a dummy gate having a dummy gate width.

3. The integrated circuit structure as described in claim 2, characterized in that, The dummy gate width is the same as the gate width of a first channel of the first semiconductor structure or the gate width of a second channel of the second semiconductor structure.

4. The integrated circuit structure as described in claim 1, 2, or 3, characterized in that, A first gate of the first semiconductor structure is coupled to a second gate of the second semiconductor structure.

5. The integrated circuit structure as described in claim 1, 2, or 3, characterized in that, A first gate of the first semiconductor structure is decoupled to a second gate of the second semiconductor structure.

6. The integrated circuit structure as described in claim 1, 2, or 3, characterized in that, The first semiconductor structure includes a first gate spacing between a first n-type channel and a first p-type channel, and the second semiconductor structure includes a second gate spacing between a second n-type channel and a second p-type channel.

7. An integrated circuit structure, characterized in that, Include: A first semiconductor device unit having a first gate having a first gate width; and A second semiconductor device unit has a second gate having a second gate width different from the width of the first gate, wherein the first gate and the second gate are in contact with each other.

8. The integrated circuit structure as described in claim 7, characterized in that, The first semiconductor device unit includes a first gate spacing between a first n-type channel and a first p-type channel, and the second semiconductor device unit includes a second gate spacing between a second n-type channel and a second p-type channel.

9. The integrated circuit structure as described in claim 8, characterized in that, The first channel height, first channel width, first gate width, and first gate spacing of the first semiconductor device unit are different from the second channel height, second channel width, second gate width, and second gate spacing of the second semiconductor device unit.

10. An integrated circuit structure, characterized in that, Include: A first semiconductor structure includes a first channel extending along a first axis and a first gate electrode extending along a second axis, wherein the first channel has a first channel width and the first gate electrode has a first gate width. as well as A second semiconductor structure includes a second channel extending along the first axis and a second gate electrode extending along the second axis, wherein the second channel has a second channel width different from the first channel width, the first channel and the second channel are in contact with each other, and the second gate electrode has a second gate width different from the first gate width.

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