Semiconductor device structure

Abstract

The utility model provides a semiconductor device structure. The structure includes a first plurality of source / drain regions disposed in a first direction, a second plurality of source / drain regions disposed in the first direction and spaced apart from the first plurality of source / drain regions, and a conductive feature disposed between the first plurality of source / drain regions. And a second plurality of source / drain regions, and a plurality of conductive contacts disposed over and in contact with the conductive feature. Each conductive contact of the plurality of conductive contacts is in contact with a source / drain region of the first plurality of source / drain regions and a source / drain region of the second plurality of source / drain regions.

Description

Technical Field

[0001] This utility model relates to a semiconductor device structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded generation after generation of ICs, each generation smaller and more complex than the last. Throughout IC development, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This shrinkage process typically benefits production efficiency and reduces associated costs. However, this size reduction also increases the complexity of integrated circuit fabrication and manufacturing.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Utility Model Content

[0004] This invention provides a semiconductor device structure. This structure includes a first plurality of source / drain regions disposed along a first direction, a second plurality of source / drain regions disposed along the first direction and spaced apart from the first plurality of source / drain regions, and a conductive feature disposed between the first plurality of source / drain regions. A plurality of conductive contacts are disposed above and in contact with the conductive features. Each of the plurality of conductive contacts is in contact with a source / drain region in the first plurality of source / drain regions and a source / drain region in the second plurality of source / drain regions.

[0005] This invention provides a semiconductor device structure. The structure includes a first gate electrode, a second gate electrode, and a dielectric material. The first gate electrode is divided into a first part and a second part by the dielectric material, and the second gate electrode is divided into a third part and a fourth part by the dielectric material. The structure also includes a first conductive feature disposed in a dielectric material and between a first portion and a second portion of a first gate electrode and between a third portion and a fourth portion of a second gate electrode; a first source / drain region disposed on a first side of the first portion of the first gate electrode; a second source / drain region disposed on a second side opposite to the first side of the first portion of the first gate electrode; a third source / drain region disposed on a third side of the second portion of the first gate electrode; and a fourth source / drain region disposed on a fourth side opposite to the third side of the second portion of the first gate electrode; a first conductive contact disposed on and electrically connected to the first conductive feature, the first source / drain region, and the third source / drain region; and a second conductive contact disposed on and electrically connected to the first conductive feature, the second source / drain region, and the fourth source / drain region. Attached Figure Description

[0006] The best understanding of the various features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a perspective view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0008] Figures 2A to 2D It is according to some embodiments along Figure 1 The cross-sectional side view of each stage of manufacturing a semiconductor device structure is taken from line segment AA.

[0009] Figures 3A to 8A It is according to some embodiments along Figure 1 The cross-sectional side view of each stage of manufacturing a semiconductor device structure is taken from line segment AA.

[0010] Figures 3B to 8B It is according to some embodiments along Figure 1 The line segment BB is a cross-sectional side view of each stage of the semiconductor device manufacturing structure.

[0011] Figures 9A to 13A It is according to some embodiments along Figure 1 The cross-sectional side view of each stage of manufacturing a semiconductor device structure is taken from line segment AA.

[0012] Figures 9B to 13B It is according to some embodiments along Figure 8B The line segment CC is used to capture cross-sectional side views of various stages of manufacturing a semiconductor device structure.

[0013] Figure 14 and Figure 15 This is a top view of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0014] Figures 16A to 19A This is a top view of the various stages of manufacturing the semiconductor device structure after flipping the semiconductor device structure, according to some embodiments.

[0015] Figures 16B to 19B It is according to some embodiments along Figure 1 The cross-sectional side view of each stage of manufacturing a semiconductor device structure is taken from line segment AA.

[0016] Figures 16C to 19C It is according to some embodiments along Figure 8B The line segment CC is used to capture cross-sectional side views of various stages of manufacturing a semiconductor device structure.

[0017] Figures 20A to 20C These are various views of a semiconductor device structure according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used in the text to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0020] While the embodiments disclosed herein are discussed in relation to nanostructured channel FETs, implementations of some aspects of this disclosure can be used with other processes and / or other devices, such as planar FETs, FinFETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, wafer FETs, nanowire FETs, forksheet FETs, complementary FETs (CFETs), and other suitable devices. It will be readily understood by those skilled in the art that other modifications are contemplated within the scope of this disclosure. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns with pitches, for example, smaller than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer wall is formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining gap walls can then be used to pattern the GAA structure.

[0021] Figures 1 to 19C An exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of this disclosure is shown. It should be understood that, for additional embodiments of this method, [further details may be needed]. Figures 1 to 19C Additional operations are provided before, during, and after the processes shown, and some of the operations described below can be substituted or eliminated. The order of operations / processes is unrestricted and can be interchanged.

[0022] Figure 1 This is a perspective view of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. On one hand, the insulating layer is an oxygen-containing layer.

[0023] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type impurities). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field-effect transistor (NFET) and boron for a p-type field-effect transistor (PFET).

[0024] Semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate components, such as nanostructure channel FETs. In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0025] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0026] The first semiconductor layer 106, or portions thereof, may form nanostructure channels of the semiconductor device structure 100 during later fabrication stages. The term "nanostructure" is used herein to refer to any material portion having nanoscale or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or rod-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructure transistors. Nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, ring gate (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gates surrounding the channels. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0027] Each first semiconductor layer 106 may have a thickness ranging from approximately 5 nm to approximately 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from approximately 2 nm to approximately 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged as follows... Figure 1 The alternating arrangement shown is for illustrative purposes and is not intended to limit the scope beyond the specific description in the request. It is understood that any number of first and second semiconductor layers 106, 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100.

[0028] Figures 2A to 2D It is according to some embodiments along Figure 1 The image shows a cross-sectional side view of each stage of the semiconductor device structure 100, taken from line segment AA. Figure 2A As shown, fin structures 112 are formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer 110 formed on the semiconductor layer stack 104 using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) over the hard mask layer 110, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask assembly layer including the photoresist. In some embodiments, patterning the photoresist layer to form a photomask assembly can be performed using an electron beam lithography process. The etching process forms trenches 114 in unprotected areas that penetrate the hard mask layer 110, through the semiconductor layer stack 104, and into the substrate 101, thereby leaving a plurality of extended fin structures 112. The trench 114 extends along the X direction. The trench 114 can be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0029] exist Figure 2BIn this process, after forming the fin structure 112, an isolation region 118 is formed on the substrate 101. This can be achieved by first filling the trench 114 between adjacent fin structures 112 with an insulating material, and then recessing the insulating material to form the isolation region 118. The recess in the insulating material exposes portions of the fin structures 112, such as the semiconductor layer stack 104. The recess in the insulating material exposes the trench 114 between adjacent fin structures 112. The top surface of the isolation region 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed from the substrate 101. The isolation region 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The isolation region 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0030] like Figure 2C As shown, the hard mask layer 110 is removed. The hard mask layer 110 can be removed using a selective etching process that substantially does not affect the isolation region 118 and the semiconductor layer stack 104. As... Figure 2D As shown, a sacrificial gate material 115 is formed on the fin structure 112 and the isolation region 118. A sacrificial gate dielectric layer (not shown) can be formed on the fin structure 112 and the isolation region 118 first, and the sacrificial gate material 115 can be formed on the sacrificial gate dielectric layer.

[0031] Figures 3A to 8A It is according to some embodiments along Figure 1 The image shows a cross-sectional side view of various stages of the semiconductor device structure 100, taken by line segment AA. Line segment AA shows a cross-section of the source / drain (S / D) region. Figures 3B to 8B It is according to some embodiments along Figure 1 The image shows a cross-sectional side view of various stages of the semiconductor device structure 100, taken by line segment BB. Line segment BB shows a cross-section along the fin structure 112. Figure 3A and Figure 3B As shown, one or more sacrificial gate electrodes 120 (only one is shown) are formed across one or more fin structures 112. The sacrificial gate electrodes 120 may be formed by patterning a sacrificial gate material 115. A sacrificial gate dielectric layer may also be patterned together with the sacrificial gate material 115. In some embodiments, the sacrificial gate electrodes 120 and the sacrificial gate dielectric layer may form a sacrificial gate structure together. Each sacrificial gate structure may be formed on a portion of the fin structure 112. Although one sacrificial gate structure is shown, in some embodiments two or more sacrificial gate structures may be arranged along the X-direction.

[0032] In some embodiments, a mask layer (not shown) may be formed on the sacrificial gate electrode 120, and the mask layer is part of the sacrificial gate structure. The sacrificial gate dielectric layer may include one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate electrode 120 may include polycrystalline silicon or amorphous silicon. The mask layer may include more than one layer, such as an oxide layer and a nitride layer.

[0033] like Figure 3A and Figure 3B As shown, a gate spacer 122 is then formed on the exposed portion of the sacrificial gate structure and fin structure 112. The gate spacer 122 can be one or more conformal layers. The gate spacer 122 can be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0034] Next, as Figure 4A and Figure 4B As shown, an anisotropic etching process is performed to remove a portion of the gate gap wall 122 formed on the horizontal surface, and to recess the exposed portion of the fin structure 112 not covered by the sacrificial gate structure. The portion of the fin structure 112 covered by the sacrificial gate electrode 120 of the sacrificial gate structure serves as a channel region of the semiconductor device structure 100.

[0035] The portion of fin structure 112 not covered by the sacrificial gate structure and gate spacer 122 is recessed to a level above, below, or above the top surface of isolation region 118. This recessing of the fin structure 112 can be achieved by an etching process, which can be a unidirectional or anisodirectional etching process, and the etching process can be selective relative to one or more crystal planes of substrate 101. The etching process can be dry etching, such as RIE, NBE, etc., or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant. After recessing the exposed portion of each fin structure 112, a portion of each well portion 116 is exposed.

[0036] Next, as Figure 5A and Figure 5BAs shown, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction, and a dielectric layer 124 is deposited on the exposed surface of the semiconductor device structure 100. Removing the edge portions of the second semiconductor layers 108 forms cavities. In some embodiments, portions of the second semiconductor layers 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine o-catechol (EDP), or potassium hydroxide (KOH) solution.

[0037] The dielectric layer 124 may be made of a dielectric material such as SiON, SiCN, SiOC, SiOCN, SiN, SiO2, AlO, or HfO. In some embodiments, the dielectric material is a low-k dielectric material (K value less than 7). In some embodiments, the dielectric material is a high-k dielectric material (K value greater than or equal to 7). The dielectric layer 124 may be formed via a conformal deposition process such as ALD. A portion of the dielectric layer 124 formed in the cavity created by removing the edge portion of the second semiconductor layer 108 may be a dielectric spacer 126, such as... Figure 5B As shown.

[0038] like Figure 6A and 6B As shown, a portion of the dielectric layer 124 is removed using an anisotropic etching process. As a result, the dielectric spacer walls 126 are not removed because they are protected by the first semiconductor layer 106 during the anisotropic etching process. The remaining second semiconductor layer 108 is covered between the dielectric spacer walls 126 along the X direction.

[0039] Next, as Figure 7A and 7B As shown, a source / drain (S / D) region 130 is formed from the well portion 116. The S / D region 130 can be grown vertically and horizontally to form facets, which can correspond to the material type of the crystal plane used in the well portion 116. In this disclosure, the source region and drain region are used interchangeably and their structures are substantially the same. Furthermore, the source / drain region may refer to the source or drain individually or jointly depending on the context. For an n-channel FET, the S / D region 130 may be made of one or more layers of Si, SiP, SiC, and SiCP, or for a p-channel FET, it may be made of Si, SiGe, or Ge. For a p-channel FET, a p-type dopant such as boron (B) may also be included in the S / D region 130. The S / D region 130 can be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0040] like Figure 8A and8B As shown, a contact etch stop layer (CESL) 132 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 132 covers the sidewalls of the sacrificial gate structure, isolation region 118, S / D region 130, and an S / D region (not shown) of the opposite type to S / D region 130, as well as a dielectric layer 124. CESL 132 may comprise oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or combinations thereof, and may be formed using CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 134 is formed on the CESL 132 above the semiconductor device structure 100. The material of ILD layer 134 may comprise compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials such as polymers may also be used for ILD layer 134. ILD layer 134 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 134 is formed, the semiconductor device structure 100 may be subjected to heat treatment to anneal the ILD layer 134.

[0041] After forming the ILD layer 134, a planarization operation such as CMP is performed on the semiconductor device structure 100 until the sacrificial gate electrode 120 is exposed, as shown below. Figure 8A and 8B As shown.

[0042] Figures 9A to 13A It is according to some embodiments along Figure 1 A cross-sectional side view of each stage of the semiconductor device structure 100, taken by line segment AA. Figures 9B to 13B It is according to some embodiments along Figure 8B A cross-sectional side view of each stage of the semiconductor device structure 100, taken by line segment CC. Figure 8B The line segment CC shows the cross-section in the gate / channel region.

[0043] Figure 9A and Figure 9B It shows the relationship with Figure 8A and Figure 8B The semiconductor device structure 100 shown is a semiconductor device structure 100 at the same manufacturing stage. Next, as... Figure 10A and 10BAs shown, the sacrificial gate structure and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure and the second semiconductor layer 108 forms an opening between the gate spacer 122 and the first semiconductor layer 106. The ILD layer 134 protects the epitaxial feature 130 during the removal process. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode 120 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode 120, but not the gate spacer 122, the ILD layer 134, and the CESL 132.

[0044] Selective wet etching can be used to remove the second semiconductor layer 108. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe while substantially not affecting the Si and the dielectric material of the gate spacer 122 and the isolation region 118. In one embodiment, the second semiconductor layer 108 can be removed using wet etchants such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), dry etchants such as fluorine-based etchants (e.g., F2) or chlorine-based gases (e.g., Cl2), or any suitable isotropic etchant.

[0045] After forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 131 is formed around the exposed portion of the first semiconductor layer 106, and a gate electrode 136 is formed on the gate dielectric layer 131. The gate dielectric layer 131 and the gate electrode 136 may be collectively referred to as a gate structure. In some embodiments, an interface layer (IL) 133 is formed between the gate dielectric layer 131 and the exposed surface of the first semiconductor layer 106. In some embodiments, the IL 133 is selectively formed on the well portion 116 and the semiconductor material of the first semiconductor layer 106, and then the gate dielectric layer 131 is formed on the IL 133 and the isolation region 118. In some embodiments, the gate dielectric layer 131 comprises one or more layers of dielectric material, such as silicon oxide, silicon, nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 131 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode 136 can comprise one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode 136 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode 136 can also be deposited above the upper surface of the ILD layer 134. The gate dielectric layer 131 and gate electrode 136 formed above the ILD layer 134 are then removed by using, for example, CMP, until the upper surface of the ILD layer 134 is exposed.

[0046] like Figure 12A and 12B As shown, a diced metal gate (CMG) process is performed. In some embodiments, openings are formed in the gate electrode 136 and the gate dielectric layer 131, and dielectric material 137 is formed in the openings. The openings may extend through the isolation region 118, and the dielectric material 137 extends through the isolation region 118, as shown. Figure 12B As shown. In some embodiments, the opening extends into the S / D regions, for example, between S / D regions 130, and dielectric material 137 is also formed between adjacent S / D regions 130, such as... Figure 12AAs shown. Dielectric material 137 divides the gate electrode 136 into two parts, and these parts can be controlled independently. Parts of dielectric material 137 can be formed on the gate electrode 136 and the ILD layer 134, and planarization processes such as CMP can be performed to remove the portions of dielectric material 137 formed on the gate electrode 136 and the ILD layer 134.

[0047] Next, as Figure 13A and Figure 13B As shown, another ILD layer 139 is formed on the gate electrode 136, dielectric material 137, and ILD layer 134. ILD layer 139 may include the same material as ILD layer 134 and may be formed using the same process as ILD layer 134. Conductive contacts 140 are formed in ILD layer 139. In some embodiments, portions of ILD layer 139, ILD layer 134, and CESL 132 are removed, and the conductive contacts 140 are as shown... Figure 13A As shown, it is formed above the S / D region 130. The conductive contact 140 may be conductive and may comprise one or more materials having Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN, and the conductive contact 140 may be formed by any suitable method, such as electrochemical plating (ECP) or PVD. The silicide layer 142 may be located between the conductive contact 140 and the S / D region 130, as shown. Figure 13A As shown. The silicide layer 142 may include one or more materials selected from WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.

[0048] Figure 14 and Figure 15 This is a top view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 14 yes Figure 13A and 13B A top view of the semiconductor device structure 100 shown. Figure 14 As shown, the semiconductor device structure 100 includes a plurality of conductive contacts 140 extending along the Y direction and traversing the fin structure 112 (or the S / D region 130 and the first semiconductor layer 106). In some embodiments, the plurality of conductive contacts 140 are disposed above and in contact with the dielectric material 137. Each conductive contact 140 in contact with the dielectric material 137 is disposed above at least two S / D regions 130, such as... Figure 14As shown. In some embodiments, the conductive contact 140 contacts at least two S / D regions 130. The conductive contact 140 may be separated by a dielectric material 144. In some embodiments, the dielectric material 144 is part of an ILD layer 139, for example, the ILD layer 139 may be patterned to form a plurality of openings, and the conductive contact 140 is formed in the openings. The remainder of the ILD layer 139 is the dielectric material 144.

[0049] Next, as Figure 15 As shown, a plurality of conductive features 146a, 146b are formed over a plurality of conductive contacts 140. The conductive features 146a, 146b are formed in a dielectric material, such as an intermetallic dielectric (IMD) layer, which is part of an interconnect structure. The IMD layer is made of a dielectric material, such as SiOx, SiOxCyHz, or SiOxCy, where x, y, and z are integers or non-integers. In some embodiments, the IMD layer comprises a dielectric material with a k value in the range of about 1 to about 5. The conductive features 146a, 146b may be conductive vias. In some embodiments, such as... Figure 15 As shown, conductive feature 146a is formed above the S / D region 130, and conductive feature 146b is formed above the dielectric material 137. Next, conductive feature 148 is formed above and electrically connected to conductive features 146a and 146b. Conductive feature 148 is a conductor with a different height in the Y direction, such as... Figure 15 As shown. Conductive features 146a, 146b, and 148 are made of copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, titanium silicon nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten silicon nitride, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof. Conductive features 146a, 146b, and 148 are formed in the interconnect structure through any suitable process (such as PVD, CVD, or ECP).

[0050] After completing the interconnect structure containing multilayer conductive features (such as conductive vias and conductive lines) embedded in the IMD layer, the semiconductor device structure 100 is flipped for back-side processing.

[0051] Figures 16A to 19A This is a top view of the various stages of manufacturing the semiconductor device structure 100 after flipping the semiconductor device structure 100, according to some embodiments. Figures 16B to 19B It is according to some embodiments along Figure 1 A cross-sectional side view of each stage of the semiconductor device structure 100, taken by line segment AA. Figures 16C to 19C It is according to some embodiments along Figure 8BThe figures above are cross-sectional side views of various stages of manufacturing the semiconductor device structure 100, taken by line segment CC. For clarity, interconnect structures formed on the semiconductor device structure 100 are omitted in the above figures. Figure 16A , 16B As shown in Figure 16C, substrate 101 is thinned to expose isolation region 118, well portion 116, and dielectric material 137. Substrate 101 can be thinned using any suitable process. In some embodiments, a planarization process such as CMP is performed to thin substrate 101. Figure 16A As shown, dielectric material 137 has a height H1 in the Y direction.

[0052] Next, as Figure 17A , 17B As shown in Figure 17C, a masking layer 150 is formed on the well portion 116 and the isolation zone 118, and an opening 151 is formed in the masking layer 150 to expose a portion of the dielectric material 137. The masking layer 150 may include any suitable material, such as oxides or nitrides. The opening 151 may be formed by any suitable process. In some embodiments, the opening 151 is formed by a dry etching process. A photoresist (not shown) may be formed on the masking layer 150 to expose a portion of the masking layer 150, and the exposed portion of the masking layer 150 may be removed to form the opening 151. Figure 17A As shown, the opening 151 has a height H2 that is substantially smaller than the height H1 of the dielectric material 137. The portion 137a of the dielectric material 137 located above and below the opening 151 (along the Y direction) is covered by the masking layer 150.

[0053] Next, the opening 151 is extended into the dielectric material 137, and a conductive feature 152 is formed in the opening 151, such as... Figure 18A , 18B As shown in Figure 18C. Conductive feature 152 may include the same material as conductive features 146a, 146b, and 148, and may be formed using the same process as conductive features 146a, 146b, and 148. In some embodiments, such as Figure 18B As shown, opening 151 extends into conductive contact 140 in the S / D region, and conductive feature 152 extends into conductive contact 140. Therefore, conductive contact 140 and conductive feature 152 are electrically connected. In the channel region, as... Figure 18C As shown, the conductive feature 152 is electrically isolated from the gate electrode 136 through a portion 137a of the dielectric material 137. The conductive feature 152 can also be formed on the mask layer 150. A process such as CMP can be performed to remove portions of the conductive feature 152 formed on the mask layer 150. A planarization process can also remove the mask layer 150, the conductive feature 152, and a portion 137a of the dielectric material 137. Figure 18A ,18B As shown in Figure 18C, isolation zone 118 and well section 116 are exposed.

[0054] Next, as Figure 19A , 19B As shown in Figure 19C, a dielectric layer 154 is formed on conductive feature 152, portion 137a of dielectric material 137, and isolation region 118, and conductive feature 156 is formed in dielectric layer 154. Dielectric layer 154 and conductive feature 156 may be part of an interconnect structure disposed on the back side of semiconductor device structure 100. Dielectric layer 154 may include the same material as the IMD layer, and conductive feature 156 may include the same material as conductive features 146a, 146b, and 148. Figure 19B As shown, conductive feature 156 is electrically connected to conductive contact 140 via conductive feature 152, and conductive contact 140 is electrically connected to S / D region 130. Therefore, power or signal can be supplied to S / D region 130 from conductive feature 156 located on the back side of semiconductor device structure 100 via conductive feature 152. This improves metal wiring efficiency.

[0055] Figures 20A to 20C These are various views of a semiconductor device structure 100 according to some embodiments. Figure 20A After the formation of conductive feature 152 Figure 14 The diagram shows a top view of the semiconductor device structure 100. Figure 20B It is along Figure 20A A cross-sectional side view of the semiconductor device structure 100, taken by line segment DD. Figure 20C It is along Figure 20A A cross-sectional side view of the semiconductor device structure 100, taken by line segment EE. (See attached image.) Figure 20A As shown, the semiconductor device structure 100 can be a standard logic (STD) cell with a gate pitch P. In some embodiments, the cell height H3 can be equal to 2P or 5P, the height H2 of the conductive feature 152 can be equal to P to about 3P, the width W2 of the conductive feature 152 can be equal to 1.5P to about 18P, and the width W1 of the conductive feature 140 can be equal to 0.3P to about 0.5P. By connecting the conductive features 152 (1.5P to 18P) in the small cell with conductive contacts 140 (0.3P to 0.5P), the conductive contacts 140 can be continuous (connecting two or more S / D regions 130). Continuous conductive contacts 140 solve area loss by directly inserting the conductive features 152 into the STD cell without increasing the cell height.

[0056] like Figure 20AAs shown, a first plurality of S / D regions 130 are arranged along the X direction, and a second plurality of S / D regions 130 are also arranged along the X direction. The first plurality of S / D regions 130 and the second plurality of S / D regions 130 are spaced apart in the Y direction. A conductive feature 152 is disposed between the first plurality of S / D regions 130 and the second plurality of S / D regions 130. A plurality of conductive contacts 140 are spaced apart along the X direction.

[0057] like Figure 20B and 20C As shown, multiple conductive contacts 140 contact conductive feature 152, and conductive feature 152 contacts conductive feature 156. Each conductive contact 140 contacts two or more S / D regions 130. Conductive feature 152 is permeated by dielectric material 137. Figure 19B , 19C ) with S / D region 130 and gate electrode 136 ( Figure 19C Electrical isolation.

[0058] Embodiments of the present invention provide a semiconductor device structure and a method for forming the same. In some embodiments, the semiconductor device structure includes a conductive feature 152 disposed between an S / D region 130 and a gate electrode 136. The conductive feature 152 is electrically connected to a plurality of consecutive conductive contacts 140, and each conductive contact 140 is electrically connected to two or more S / D regions 130. Some embodiments offer advantages. For example, by inserting the conductive feature 152 between adjacent S / D regions 130, the cell height is not increased. Furthermore, the use of consecutive conductive contacts 140 reduces process risk.

[0059] One embodiment is a semiconductor device structure. This structure includes a first plurality of source / drain regions disposed along a first direction, a second plurality of source / drain regions disposed along the first direction and spaced apart from the first plurality of source / drain regions, and a conductive feature disposed between the first plurality of source / drain regions. A plurality of conductive contacts are disposed above and in contact with the conductive feature. Each of the plurality of conductive contacts is in contact with a source / drain region in the first plurality of source / drain regions and a source / drain region in the second plurality of source / drain regions.

[0060] In some embodiments, the semiconductor device structure further includes a dielectric material disposed between the first plurality of source / drain regions and the second plurality of source / drain regions, wherein the conductive features are disposed in the dielectric material.

[0061] In some embodiments, the dielectric material has a first height in a top view, and the conductive feature has a second height in the top view that is substantially smaller than the first height.

[0062] In some embodiments, the semiconductor device structure further includes a first gate electrode disposed between adjacent source / drain regions of the first plurality of source / drain regions, and a second gate electrode disposed between adjacent source / drain regions of the second plurality of source / drain regions.

[0063] In some embodiments, the dielectric material is disposed between the first gate electrode and the second gate electrode.

[0064] In some embodiments, the conductive feature is disposed between the first gate electrode and the second gate electrode.

[0065] Another embodiment is a semiconductor device structure. The structure includes a first gate electrode, a second gate electrode, and a dielectric material. The first gate electrode is divided into a first portion and a second portion by the dielectric material, and the second gate electrode is divided into a third portion and a fourth portion by the dielectric material. The structure also includes a first conductive feature disposed in a dielectric material and between a first portion and a second portion of a first gate electrode and between a third portion and a fourth portion of a second gate electrode; a first source / drain region disposed on a first side of the first portion of the first gate electrode; a second source / drain region disposed on a second side opposite to the first side of the first portion of the first gate electrode; a third source / drain region disposed on a third side of the second portion of the first gate electrode; and a fourth source / drain region disposed on a fourth side opposite to the third side of the second portion of the first gate electrode; a first conductive contact disposed on and electrically connected to the first conductive feature, the first source / drain region, and the third source / drain region; and a second conductive contact disposed on and electrically connected to the first conductive feature, the second source / drain region, and the fourth source / drain region.

[0066] In some embodiments, the semiconductor device structure further includes a plurality of second conductive features disposed on the first conductive contact and the second conductive contact.

[0067] In some embodiments, the semiconductor device structure further includes a third conductive feature disposed on the plurality of second conductive features, wherein the third conductive feature has a varying height in a top view.

[0068] In some embodiments, the semiconductor device structure further includes a fourth conductive feature disposed below the first conductive feature, wherein the first, second, third and fourth conductive features are electrically connected.

[0069] In some embodiments, the dielectric material and the first conductive feature are disposed between the first source / drain region and the third source / drain region, and between the second source / drain region and the fourth source / drain region.

[0070] In some embodiments, the semiconductor device structure further includes a first plurality of semiconductor layers disposed between the first and second source / drain regions and a second plurality of semiconductor layers disposed between the third and fourth source / drain regions.

[0071] In some embodiments, the first portion of the first gate electrode surrounds the first plurality of semiconductor layers, and the second portion of the first gate electrode surrounds the second plurality of semiconductor layers.

[0072] Another embodiment is a method for forming a semiconductor device structure. This method includes forming a sacrificial gate electrode over portions of a first semiconductor layer stack and a second semiconductor layer stack, recessing exposed portions of the first and second semiconductor layer stacks not covered by the sacrificial gate electrode to expose first and second well portions on opposite sides of the first semiconductor layer stack, and third and fourth well portions on opposite sides of the second semiconductor layer stack, forming first, second, third, and fourth source / drain regions on the first, second, third, and fourth well portions, respectively, replacing the sacrificial gate electrode with a gate electrode, and forming a dielectric material between the first and third source / drain regions. The dielectric material divides the gate electrode into two portions. The method further includes forming a first conductive contact over the first and third source / drain regions, and the first conductive contact contacting the dielectric material. The method further includes forming a second conductive contact over the second and fourth source / drain regions, and the second conductive contact contacting the dielectric material. The method further includes flipping the semiconductor device structure and forming a first conductive feature in the dielectric material. The first conductive feature is electrically connected to the first conductive contact and the second conductive contact.

[0073] In some embodiments, forming the dielectric material includes forming openings in the gate electrode and in an isolation region located below the gate electrode, and filling the openings with the dielectric material.

[0074] In some embodiments, the method further includes removing portions of the dielectric material located between the first and third source / drain regions and between the second and fourth source / drain regions before forming the first and second conductive contacts.

[0075] In some embodiments, the method, wherein forming the first conductive feature includes: removing a portion of a substrate to expose the dielectric material; depositing a mask layer on the dielectric material; forming an opening in the mask layer to expose a first portion of the dielectric material, wherein a second portion of the dielectric material is covered by the mask layer; extending the opening into the dielectric material; and filling the opening with the first conductive feature.

[0076] In some embodiments, the opening extends into the first conductive contact, and the first conductive feature is formed in the first conductive contact.

[0077] In some embodiments, the method further includes forming a dielectric layer on the first conductive feature and the dielectric material.

[0078] In some embodiments, the method further includes forming a second conductive feature in the dielectric layer, wherein the second conductive feature is electrically connected to the first conductive feature.

[0079] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same benefits. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized in that, include: The first plurality of source / drain regions are arranged along the first direction; The second plurality of source / drain regions are arranged along the first direction and spaced apart from the first plurality of source / drain regions; A conductive feature is disposed between the first plurality of source / drain regions and the second plurality of source / drain regions; as well as A plurality of conductive contacts are disposed above and in contact with the conductive feature, wherein each of the plurality of conductive contacts is in contact with a source / drain region in the first plurality of source / drain regions and a source / drain region in the second plurality of source / drain regions.

2. The semiconductor device structure according to claim 1, characterized in that, It also includes a dielectric material disposed between the first plurality of source / drain regions and the second plurality of source / drain regions, wherein the conductive features are disposed in the dielectric material.

3. The semiconductor device structure according to claim 2, characterized in that, The dielectric material has a first height in the top view, and the conductive feature has a second height in the top view that is substantially smaller than the first height.

4. The semiconductor device structure according to claim 2, characterized in that, It also includes a first gate electrode disposed between adjacent source / drain regions of the first plurality of source / drain regions, and a second gate electrode disposed between adjacent source / drain regions of the second plurality of source / drain regions.

5. The semiconductor device structure according to claim 4, characterized in that, The dielectric material is disposed between the first gate electrode and the second gate electrode.

6. A semiconductor device structure, characterized in that, include: First gate electrode and second gate electrode; A dielectric material, wherein the first gate electrode is divided into a first portion and a second portion by the dielectric material, and the second gate electrode is divided into a third portion and a fourth portion by the dielectric material; A first conductive feature is disposed in the dielectric material and located between the first portion and the second portion of the first gate electrode and between the third portion and the fourth portion of the second gate electrode; The first source / drain region is disposed on the first side of the first portion of the first gate electrode; The second source / drain region is disposed on the second side of the first portion of the first gate electrode, opposite to the first side; The third source / drain region is disposed on the third side of the second portion of the first gate electrode; The fourth source / drain region is disposed on the fourth side of the second portion of the first gate electrode, opposite to the third side; A first conductive contact is disposed above the first conductive feature, the first source / drain region, and the third source / drain region and is in electrical contact with the first conductive feature, the first source / drain region, and the third source / drain region; as well as The second conductive contact is disposed above the first conductive feature, the second source / drain region, and the fourth source / drain region, and is in electrical contact with the first conductive feature, the second source / drain region, and the fourth source / drain region.

7. The semiconductor device structure according to claim 6, characterized in that, It also includes a plurality of second conductive features disposed on the first conductive contact and the second conductive contact.

8. The semiconductor device structure according to claim 7, characterized in that, It also includes a third conductive feature disposed on the plurality of second conductive features, wherein the third conductive feature has a varying height in a top view.

9. The semiconductor device structure according to claim 7, characterized in that, It also includes a fourth conductive feature disposed below the first conductive feature, wherein the first, second, third and fourth conductive features are electrically connected.

10. The semiconductor device structure according to claim 6, characterized in that, The dielectric material and the first conductive feature are disposed between the first source / drain region and the third source / drain region, and between the second source / drain region and the fourth source / drain region.

Images