Flip quantum chip and quantum computer

Abstract

The utility model relates to the technical field of quantum information, and discloses a flip quantum chip and a quantum computer, the flip quantum chip comprises a first chip and a second chip which are oppositely arranged, and the first chip and the second chip are in flip connection; the photoresist gasket is located between the first chip and the second chip, and the superconducting cylinder is located on the inner side of the photoresist gasket; wherein the superconducting cylinder is used for electrically conducting the first chip and the second chip, and the photoresist gasket is used for playing a uniform supporting role between the first chip and the second chip. The photoresist gasket is used as the supporting gasket between the first chip and the second chip, the thickness uniformity of the photoresist gasket is good, the thickness is easy to control, the problem of inclination caused by pure superconducting cylinder supporting can be avoided, and the distance between the first chip and the second chip can be better controlled. The photoresist gasket is simple to manufacture, can adapt to wafer-level processing, and is compatible with a manufacturing process of a low-loss chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum information, and particularly relates to a flip quantum chip and a quantum computer. BACKGROUND

[0002] The 3D integrated superconducting quantum chip is connected through a Flip-Chip mode, quantum bits and readout control are divided into two separate planes, and are respectively arranged on two chips, and are coupled and connected through capacitors and inductors, and superconducting metal is used as mechanical support and signal connection. The superconducting metal is usually indium which has good ductility and is easy to cold weld.

[0003] The distance between the two chips affects the frequency of the resonance characteristics, the impedance matching between different signal lines, and the capacitive and inductive coupling rate between elements. The relative inclination of the two chips affects the change of the distance in the local area between the two chips, and further causes local frequency shift. Since indium is soft, it is easy to tilt during flip bonding. In order to solve this problem, a hard blocking gasket can be added between the two chips. The hard blocking gasket can use a silicon spacer or a large indium pad. The large indium pad can significantly increase the surface area of the indium and dilute the bonding force. However, there are the following defects. For obtaining the silicon spacer, uniformly etching a large silicon substrate without increasing the surface roughness or loss rate is a major manufacturing challenge, which is very difficult to produce. The large indium pad needs to be deposited with a large thickness, and the height is difficult to control, which also has the problem of being very difficult to produce.

[0004] Therefore, how to solve the above technical problems should be the focus of the person skilled in the art. CONTENT OF THE UTILITY MODEL

[0005] The purpose of the present application is to provide a flip quantum chip and a quantum computer, which can realize good control of the distance between two chips and reduce the production difficulty.

[0006] To solve the above technical problems, the present application provides a flip quantum chip, comprising:

[0007] A first chip and a second chip are oppositely arranged, the first chip is flip connected with the second chip, a superconducting column and a photoresist gasket between the first chip and the second chip, the superconducting column is located on the inner side of the photoresist gasket.

[0008] The superconducting column is used for electrically connecting the first chip and the second chip, and the photoresist gasket is used for uniformly supporting the first chip and the second chip.

[0009] In some embodiments, the flip quantum chip further comprises:

[0010] a second superconducting layer and a Josephson junction of the second chip relative to a surface of the first chip.

[0011] In some embodiments, the flip-chip quantum chip further comprises:

[0012] a first superconducting layer and a readout control of the first chip relative to a surface of the second chip.

[0013] In some embodiments, a bottom metal layer between the first superconducting layer and the superconducting post, between the second superconducting layer and the superconducting post, the bottom metal layer comprising an adhesion barrier layer and an oxidation resistance layer stacked in a direction away from the surface of the first chip and the second chip.

[0014] In some embodiments, the adhesion barrier layer comprises any one or any combination of a chromium layer, a titanium layer, a nickel layer, a tungsten layer;

[0015] and / or, the oxidation resistance layer comprises a gold layer.

[0016] In some embodiments, the photoresist spacer has a thickness ranging from 5 microns to 10 microns.

[0017] In some embodiments, the first superconducting layer comprises any one of an aluminum superconducting layer, a tantalum superconducting layer, a niobium superconducting layer;

[0018] and / or, the second superconducting layer comprises any one of an aluminum superconducting layer, a tantalum superconducting layer, a niobium superconducting layer.

[0019] In some embodiments, the flip-chip quantum chip is a superconducting quantum chip, and the superconducting post is an indium post.

[0020] In some embodiments, the photoresist spacer comprises a photoresist of the SU-8 series.

[0021] A quantum computer is provided in the present application, comprising the flip-chip quantum chip as claimed in any one of the above.

[0022] It can be seen that the flip-chip quantum chip in the present application uses a photoresist spacer as a support spacer between the first chip and the second chip. The photoresist spacer has good thickness uniformity and thickness that is easy to control, can avoid the problem of tilting caused by pure superconducting post support, and can better control the spacing between the first chip and the second chip, so that large-scale expansion of superconducting quantum bits can be achieved. In addition, the photoresist spacer is simple to manufacture and can be adapted to wafer-level processing, and is compatible with the manufacturing process of low-loss chips.

[0023] In addition, the present application also provides a quantum computer with the above advantages. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments of the present application, and all other drawings obtained by those skilled in the art without creative labor on the basis of these drawings also belong to the protection scope of the present application.

[0025] Figure 1 The flow of the preparation method of the superconducting quantum chip provided by the embodiments of the present application Figure 1 ;

[0026] Figures 2 to 7 The flow of the preparation process of the superconducting quantum chip provided by the embodiments of the present application Figure 1 ;

[0027] Figure 8 The flow of the preparation method of the superconducting quantum chip provided by the embodiments of the present application Figure 2 ;

[0028] Figures 9 to 11 The flow of the preparation process of the superconducting quantum chip provided by the embodiments of the present application Figure 2 ;

[0029] Figure 12 The flow of the preparation method of the superconducting quantum chip provided by the embodiments of the present application Figure 3 ;

[0030] In the figure, 1 is a first substrate, 2 is a first superconducting layer, 3 is a readout control part, 4 is a second substrate, 5 is a second superconducting layer, 6 is a Josephson junction, 7 is a photoresist spacer, 8 is a superconducting column, 9 is a bottom metal layer, 1' is a first chip, and 4' is a second chip. DETAILED DESCRIPTION

[0031] In order to make the personnel in the technical field better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor also belong to the protection scope of the present application.

[0032] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.

[0033] As described in the background section, at present, silicon spacers or large indium pads are arranged between two chips to control the distance between the two chips, but both have the problem of difficult fabrication.

[0034] Therefore, the present application provides a preparation method of a superconducting quantum chip, please refer to Figure 1 The method can comprise:

[0035] Step S101: obtaining a pretreated first wafer and a pretreated second wafer; wherein the pretreated first wafer comprises a first substrate, a first superconducting layer on the surface of the first substrate, and a readout control part, and the pretreated second wafer comprises a second substrate, a second superconducting layer on the surface of the second substrate, and a Josephson junction.

[0036] The schematic diagram of the pretreated first wafer is shown in Figure 2 The first substrate 1 can be a silicon substrate, and the first superconducting layer 2 and the readout control part 3 are directly on the surface of the first substrate 1. The readout control part 3 can include XY control lines, Z control lines, readout resonant cavities, and readout lines. The surface where the first superconducting layer 2 and the readout control part 3 are located is the inner surface of the first substrate 1.

[0037] The schematic diagram of the pretreated second wafer is shown in Figure 3 The second substrate 4 can be a silicon substrate, and the second superconducting layer 5 and the Josephson junction 6 are directly on the surface of the second substrate 4. The surface where the second superconducting layer 5 and the Josephson junction 6 are located is the inner surface of the second substrate 4.

[0038] The first superconducting layer 2 and the second superconducting layer 5 include but are not limited to any one of an aluminum (Al) superconducting layer, a tantalum (Ta) superconducting layer, and a niobium (Nb) superconducting layer. The first superconducting layer 2 and the second superconducting layer 5 can be the same or different, both of which are within the protection scope of the present application.

[0039] Step S102: fabricating a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer.

[0040] It can be understood that the fabrication position of the photoresist pad includes three cases. The first case is to fabricate the photoresist pad only on the first superconducting layer; the second case is to fabricate the photoresist pad only on the second superconducting layer; and the third case is to fabricate the photoresist pad on both the first superconducting layer and the second superconducting layer.

[0041] For example, when the photoresist pad 7 is fabricated only on the first superconducting layer 2, as shown in Figure 4 .

[0042] The photoresist pad 7 is a negative photoresist pad 7, and the specific type of the photoresist pad 7 in this embodiment is not limited and can be set by the user. For example, the material of the photoresist pad 7 can be SU-8 series photoresist, such as SU-8 3010, SU-83000, SU-8 2000, and the like.

[0043] SU-8 photoresist is a commonly used negative photoresist based on epoxy resin, with a thickness of several hundred microns, and has good mechanical properties, chemical corrosion resistance, and thermal stability.

[0044] It should be noted that the number of photoresist pads 7 in each quantum chip in this embodiment is not limited and can be set by the user. For example, the number of photoresist pads 7 in each quantum chip can be 2, 3, 4, and the like.

[0045] It should also be noted that the size of each photoresist pad 7 in this embodiment is not limited and can be set by the user. For example, the size of each photoresist pad 7 can be 14.3 μm x 14.3 μm.

[0046] The manufacturing process of the photoresist pad 7 in this embodiment is not specifically limited, as long as the photoresist pad 7 can be manufactured on the surface of the first superconducting layer 2 and / or the second superconducting layer 5.

[0047] As an implementable manner, the manufacturing of the photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer includes:

[0048] Step S1021: spin-coating a negative photoresist layer on the surface of the first substrate and / or the second substrate.

[0049] It should be noted that the spin-coating speed during the spin-coating is not limited in this embodiment and can be set by the user. As an implementable manner, when the negative photoresist is spin-coated, the spin-coating speed ranges from 1500 r / min to 3000 r / min, and for example, the spin-coating speed can be 1500 r / min, 2000 r / min, 2500 r / min, 3000 r / min, and the like.

[0050] Step S1022: sequentially performing pre-baking, exposure, post-baking, and development on the negative photoresist layer.

[0051] The effects of pre-baking include: first, removing the solvent in the photoresist to reduce the residual solvent concentration; second, enhancing the adhesion between the photoresist and the first substrate and / or the second substrate; third, during the coating process of the photoresist, stress may be generated inside the photoresist film, which helps to release these stresses.

[0052] The effects of post-baking include: making the photochemical reaction that is not completely reacted after exposure completely reacted; and enhancing the etching resistance of the photoresist.

[0053] It should be noted that the temperature, time, and exposure dose of the pre-baking in the embodiment are not limited and can be set by the user.

[0054] As an implementable manner, the temperature of the pre-baking ranges from 90°C to 100°C, and the time ranges from 180s to 300s. For example, the temperature of the pre-baking can be 90°C, 95°C, 100°C, etc., and the time of the pre-baking can be 180s, 200s, 250s, 280s, 300s, etc.

[0055] It should be noted that the size of the exposure dose in the embodiment is not limited and can be determined according to the situation.

[0056] As an implementable manner, the wavelength of the light used in the exposure can be 365nm, and the exposure dose ranges from 180mJ / cm 2 to 300mJ / cm 2 . For example, the exposure dose can be 180mJ / cm 2 , 200mJ / cm 2 , 250mJ / cm 2 , 300mJ / cm 2 , etc.

[0057] It should be noted that the process of the post-baking in the embodiment is not limited.

[0058] As an implementable manner, the post-baking includes normal pressure baking and vacuum baking, wherein the temperature of the normal pressure baking ranges from 60°C to 75°C, and the time ranges from 90s to 120s; the temperature of the vacuum baking ranges from 80°C to 100°C, and the time ranges from 250s to 400s.

[0059] For example, the temperature of the normal pressure baking can be 60°C, 65°C, 70°C, 75°C, etc., and the time of the normal pressure baking can be 90s, 100s, 110s, 120s, etc. The temperature of the vacuum baking can be 80°C, 90°C, 95°C, 100°C, etc., and the time of the vacuum baking can be 250s, 300s, 350s, 400s, etc.

[0060] The normal pressure baking can promote the photochemical reaction, and the vacuum baking can remove the residual solvent and enhance the adhesion. Such post-baking can improve the quality of the photoresist pattern and reduce defects.

[0061] The mr-Dev 600 developer can be used for rinsing during the development, and the rinsing time can be 90s.

[0062] Step S1023: removing the photoresist residue after the development to form a photoresist gasket.

[0063] When removing the photoresist residue, isopropyl alcohol and mr-Dev 600 can be used to wash alternately for several times until the residue is removed completely.

[0064] Step S103: Superconducting columns are made on the surfaces of the first superconducting layer and the second superconducting layer.

[0065] As shown in Figure 5 and Figure 6 , superconducting columns 8 are made on the surfaces of the first superconducting layer 2 and the second superconducting layer 5 respectively.

[0066] The material of the superconducting column 8 can be indium. The process of making the superconducting column 8 can include defining the pattern of the superconducting column 8 by photolithography, and then coating indium by thermal evaporation.

[0067] The shape of the superconducting column 8 includes but is not limited to any of a cylinder, a prism, a prism frustum, a circular frustum.

[0068] The thickness of the superconducting column 8 can be 10 μm, the diameter can be 25 μm, and the distance between two adjacent superconducting columns 8 can be 100 μm.

[0069] It should be noted that the order of making the photoresist spacer and the superconducting column is not limited in the present application. In the present embodiment, the photoresist spacer is made first, and then the superconducting column is made. In other embodiments of the present application, the superconducting column can be made first, and then the photoresist spacer is made.

[0070] Step S104: Flip-chip bonding and cutting are performed on the pretreated first wafer and the pretreated second wafer through the superconducting column, to obtain a superconducting quantum chip, the photoresist spacer is located between the pretreated first wafer and the pretreated second wafer; the superconducting column is located on the inner side of the photoresist spacer; the first substrate is cut to form a first chip, and the second substrate is cut to form a second chip.

[0071] The inner side of the photoresist spacer refers to the side of the photoresist spacer close to the center of the superconducting quantum chip, that is, the side away from the periphery of the superconducting quantum chip.

[0072] The pretreated first wafer and the pretreated second wafer can be placed in a flip-chip bonder (the model can be FC150) for flip-chip bonding. The positions of the pretreated first wafer and the pretreated second wafer are adjusted for alignment by a CCD (charge coupled device) camera, and then bonding pressure is applied for bonding, so that the pretreated first wafer and the pretreated second wafer are bonded together. The schematic diagram of the superconducting quantum chip after bonding is shown in Figure 7 .

[0073] The bonding pressure can range from 10 N / mm 2 ~40 N / mm 2For example, the bonding pressure can be 10 N / mm 2 , 20 N / mm 2 , 30 N / mm 2 , 40 N / mm 2 , etc. Avoiding too small bonding pressure, resulting in not firm bonding, avoid too large bonding pressure, easy to damage the first wafer and the second wafer. Bonding pressure is preferably 20 N / mm 2 .

[0074] After the first substrate and the second substrate are cut, a plurality of first chips and second chips are formed.

[0075] In order to facilitate the alignment of the first wafer and the second wafer, alignment mark points can be arranged on the first wafer and the second wafer respectively.

[0076] In the preparation of superconducting quantum chips in this embodiment, after obtaining the first wafer and the second wafer, photoresist pads and superconducting columns are made, and then the first wafer and the second wafer are flip-chip bonded. The photoresist pad serves as a support pad between the first wafer and the second wafer. The photoresist pad made by photoresist has good thickness uniformity and easy thickness control, which can avoid the problem of inclination caused by pure superconducting column support, and can better control the distance between the first substrate and the second substrate, and can realize large-scale expansion of superconducting quantum bits. In addition, the photoresist pad is simple to make, which can be adapted to wafer-level processing, and is compatible with the manufacturing process of low-loss chips.

[0077] On the basis of the above embodiment, in an embodiment of the present application, after the negative photoresist layer is sequentially subjected to pre-baking, exposure, post-baking and development, it can further include:

[0078] The developed negative photoresist layer is baked again.

[0079] The re-baking of the photoresist after development can improve the mechanical resilience of the photoresist pad.

[0080] The time and temperature of re-baking the photoresist after development in this embodiment are not limited and can be set by oneself. As an implementable manner, the temperature range of re-baking the photoresist after development can be 150℃~200℃, and the baking time can be 800s~1200s.

[0081] For example, the temperature of re-baking the photoresist after development can be 150℃, 180℃, 200℃, etc., and the baking time can be 800s, 900s, 1000s, 1200s, etc.

[0082] Please refer to Figure 8In any of the above embodiments, in an embodiment of the present application, the method for manufacturing a superconducting quantum chip can comprise:

[0083] Step S201: obtaining a pre-processed first wafer and a pre-processed second wafer; wherein the pre-processed first wafer comprises a first substrate, a first superconducting layer on the surface of the first substrate, and a readout control part, and the pre-processed second wafer comprises a second substrate, a second superconducting layer on the surface of the second substrate, and a Josephson junction.

[0084] Step S202: making a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer.

[0085] Step S203: making a bottom metal layer on the surface of the first superconducting layer and the second superconducting layer, the bottom metal layer comprising an adhesion barrier layer and an oxidation-resistant layer stacked in a direction away from the surface of the first substrate and the second substrate.

[0086] As shown in Figure 9 and Figure 10 , the position of the bottom metal layer 9 corresponds to the position of the superconducting column to be made subsequently. By setting the bottom metal layer 9, the adhesion between the superconducting column and the first superconducting layer and the second superconducting layer can be enhanced, and the stability of the superconducting column can be improved.

[0087] The material of the adhesion barrier layer includes but is not limited to metals such as chromium (Cr), titanium (Ti), nickel (Ni), and tungsten (W); and the oxidation-resistant layer can be gold (Au) or the like.

[0088] The thickness of the adhesion barrier layer can be 20 nm to 50 nm, and the thickness of the oxidation-resistant layer can be 80 nm to 100 nm.

[0089] Step S204: making a superconducting column on the surface of the bottom metal layer on the first superconducting layer and the second superconducting layer, respectively.

[0090] Step S205: flip-chip bonding the pre-processed first wafer and the pre-processed second wafer through the superconducting column and cutting to obtain a superconducting quantum chip, the photoresist pad being between the pre-processed first wafer and the pre-processed second wafer; the superconducting column being inside the photoresist pad; the first substrate being cut to form a first chip, and the second substrate being cut to form a second chip.

[0091] The first substrate and the second substrate are cut to form a plurality of first chips 1' and second chips 4', and the superconducting quantum chip obtained after cutting is as shown in Figure 11 .

[0092] On the basis of any of the above embodiments, in an embodiment of the present application, a pretreated first wafer and a pretreated second wafer are obtained; wherein the pretreated first wafer comprises a first substrate, a first superconducting layer on the surface of the first substrate, and a readout control part, and the pretreated second wafer comprises a second substrate, a second superconducting layer on the surface of the second substrate, and a Josephson junction, and can further comprise a manufacturing process of the pretreated first wafer and the pretreated second wafer, which can comprise:

[0093] depositing the first superconducting layer on the surface of the first substrate;

[0094] manufacturing the readout control part on the surface of the first substrate;

[0095] depositing the second superconducting layer on the surface of the second substrate;

[0096] manufacturing the Josephson junction on the surface of the second substrate.

[0097] The order of manufacturing the first superconducting layer and the readout control part on the first substrate is not limited in the embodiment, and the order of manufacturing the second superconducting layer and the Josephson junction on the second substrate is also not limited in the embodiment.

[0098] The manufacturing method of the first superconducting layer and the second superconducting layer can be an electron beam evaporation method.

[0099] The manufacturing process of the readout control part and the Josephson junction can refer to the prior art, and will not be described in detail in the embodiment.

[0100] The readout control part can be obtained by manufacturing a first wiring layer on the surface of the first substrate. The first substrate defines a pattern through photolithography and development, and then a first wiring layer can be obtained through a wet etching process.

[0101] The Josephson junction can be obtained by manufacturing a second wiring layer on the surface of the second substrate, and the second wiring layer comprises a structure for manufacturing the Josephson junction. The Josephson junction is manufactured by using an EBL (electron beam lithography) technology and a cross evaporation method.

[0102] It should be noted that, in order to improve the combination stability of the first substrate and the first superconducting layer, the readout control part, and the combination stability of the second substrate and the second superconducting layer, the Josephson junction, a process of cleaning the first substrate and the second substrate can be further included, and the cleaning process comprises:

[0103] immersing the first substrate and the second substrate in a mixture of ammonium hydroxide solution and hydrogen peroxide solution to remove organic contaminants on the surface of the first substrate and the second substrate;

[0104] The first substrate and the second substrate are soaked in a hydrofluoric acid solution at room temperature to remove organic contaminants and remove a silicon dioxide oxide layer on the surface of the first substrate and the second substrate;

[0105] The cleaned first substrate and the cleaned second substrate are rinsed with deionized water.

[0106] The purity of the ammonium hydroxide solution can be 25%, the purity of the hydrogen peroxide solution can be 30%, the ratio of the ammonium hydroxide solution to the hydrogen peroxide solution can be 1:1, the soaking temperature for removing organic contaminants can be 80°C, and the soaking time can be 10 minutes. The purity of the hydrofluoric acid solution can be 7%, the soaking for removing the silicon dioxide layer can be at room temperature, and the soaking time can be 60 seconds.

[0107] After the first substrate and the second substrate are rinsed, the next step is preferably performed within 10 minutes, for example, the first substrate and the second substrate are sent to an electron beam evaporation system to deposit a first superconducting layer and a second superconducting layer.

[0108] The first substrate and the second substrate can be high-resistance silicon (>20KΩ·cm).

[0109] For reference Figure 12 On the basis of any of the above embodiments, in an embodiment of the present application, the method for manufacturing a superconducting quantum chip can include:

[0110] Step S301: obtaining a pretreated first wafer and a pretreated second wafer; wherein the pretreated first wafer includes a first substrate, a first superconducting layer on the surface of the first substrate, and a readout control part, and the pretreated second wafer includes a second substrate, a second superconducting layer on the surface of the second substrate, and a Josephson junction.

[0111] Step S302: spin-coating a negative photoresist layer on the surface of the first substrate and / or the second substrate.

[0112] Step S303: sequentially performing pre-baking, exposure, post-baking, and development on the negative photoresist layer.

[0113] Step S304: re-baking the developed negative photoresist layer.

[0114] Step S305: removing the photoresist residue after development to form a photoresist gasket.

[0115] Step S306: manufacturing a bottom metal layer on the surface of the first superconducting layer and the second superconducting layer, the bottom metal layer including an adhesion barrier layer and an oxidation-resistant layer stacked in a direction away from the surface of the first substrate and the second substrate.

[0116] Step S307: manufacturing a superconducting column on the surface of the bottom metal layer on the first superconducting layer and the second superconducting layer, respectively.

[0117] Step S308: spin-coating a protective glue on the surface of the pre-processed first wafer and the pre-processed second wafer.

[0118] The type of the protective glue includes, but is not limited to, any one of AZ4620, SPR220, and AZ9260.

[0119] When the size of the first substrate and the second substrate is large, a plurality of structures required for the superconducting quantum chip can be made on the first substrate and the second substrate, and then cutting can be performed according to the size required for each superconducting quantum chip, so that the production efficiency of the superconducting quantum chip can be improved.

[0120] For example, when the diameter of the first substrate and the second substrate is 50.8 cm, and the size of the pre-processed first wafer and the pre-processed second wafer in the final superconducting quantum chip is 14.3 mm x 14.3 mm and 12 mm x 12 mm respectively, cutting needs to be performed.

[0121] By coating the protective glue on the pre-processed first wafer and the pre-processed second wafer, the structures such as the first superconducting layer, the readout control part, the second superconducting layer, the Josephson junction, and the superconducting column can be protected in the subsequent cutting process, so that the yield of the superconducting quantum chip can be improved.

[0122] Step S309: cutting the pre-processed first wafer and the pre-processed second wafer.

[0123] Step S310: removing the protective glue on the surface of the cut pre-processed first wafer and the pre-processed second wafer.

[0124] When the protective glue is removed, a solution such as acetone or isopropyl alcohol can be used for removal.

[0125] It should be noted that after the protective glue spin-coating and removal process, there may be solvent residues used for removing the protective glue on the photoresist pad. The pre-processed first wafer and the pre-processed second wafer can be placed in a vacuum oven with a temperature range of 40°C to 60°C and a pressure of 2 x 10 4 Pa for 12 to 15 hours to remove the solvent residues.

[0126] Step S311: flip-chip bonding the cut pre-processed first wafer and the pre-processed second wafer through the superconducting column to obtain a superconducting quantum chip, and the photoresist pad is located between the pre-processed first wafer and the pre-processed second wafer; the superconducting column is located on the inner side of the photoresist pad.

[0127] The superconducting quantum chip obtained after flip-chip bonding is scanned by a profilometer, and the average spacing of the superconducting quantum chip is calculated to be 9.6±0.8 μm, and the average inclination is (76±36) μrad. It shows that the SU-8 photoresist pad in the application can accurately control the spacing of the superconducting quantum chip, and improve the inclination of the superconducting quantum chip.

[0128] The application also provides a flip-chip quantum chip, for example, a superconducting quantum chip, which can include: Figure 7 and Figure 11 as shown.

[0129] The first chip 1' and the second chip 4' are oppositely arranged;

[0130] The first superconducting layer 2 and the readout control part 3 are located on the surface of the first chip 1' relative to the second chip 4';

[0131] The second superconducting layer 5 and the Josephson junction 6 are located on the surface of the second chip 4' relative to the first chip 1';

[0132] The superconducting column 8 and the photoresist pad 7 are located between the first superconducting layer 2 and the second superconducting layer 5, and the superconducting column 8 is located on the inner side of the photoresist pad 7.

[0133] The inner side of the photoresist pad 7 refers to the side of the photoresist pad 7 close to the center of the superconducting quantum chip, that is, the side away from the periphery of the superconducting quantum chip.

[0134] The first chip 1' and the second chip 4' can be silicon substrates.

[0135] The readout control part 3 can include XY control lines, Z control lines, readout resonant cavities, and readout lines.

[0136] The first superconducting layer 2 and the second superconducting layer 5 include but are not limited to any one of an aluminum (Al) superconducting layer, a tantalum (Ta) superconducting layer, and a niobium (Nb) superconducting layer.

[0137] The superconducting column 8 can be an indium column.

[0138] The material of the photoresist pad 7 can include SU-8 series photoresist, such as SU-8 3010, SU-8 3000, SU-8 2000, etc. SU-8 series photoresist is a commonly used negative photoresist based on epoxy resin, with a thickness of up to several hundred microns, and good mechanical properties, chemical corrosion resistance, and thermal stability.

[0139] The superconducting quantum chip in the embodiment uses a photoresist pad as a supporting pad between the first chip and the second chip. The photoresist pad has good thickness uniformity and thickness that is easy to control, can avoid the problem of tilting caused by pure superconducting cylinder support, and can better control the spacing between the first chip and the second chip, and can realize large-scale expansion of superconducting quantum bits. In addition, the photoresist pad is simple to manufacture, can be adapted to wafer-level processing, and is compatible with the manufacturing process of low-loss chips.

[0140] The thickness of the photoresist pad 7 is not limited in the present application. For example, the thickness of the photoresist pad 7 can be determined according to the simulation of the chip spacing based on the superconducting quantum chip architecture design.

[0141] As an implementable manner, the thickness of the photoresist pad 7 can range from 5 microns to 10 microns. For example, the thickness of the photoresist pad 7 can be 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, 10 microns, etc.

[0142] As shown in FIG. 1, the superconducting quantum chip includes a first chip 1', a second chip 4', a superconducting cylinder 8, and a photoresist pad 7. Figure 11 As shown in FIG. 1, the superconducting quantum chip includes a first chip 1', a second chip 4', a superconducting cylinder 8, and a photoresist pad 7.

[0143] A bottom metal layer 9 is located between the first superconducting layer 2 and the superconducting cylinder 8 and between the second superconducting layer 5 and the superconducting cylinder 8. The bottom metal layer 9 includes an adhesion barrier layer and an oxidation-resistant layer stacked in a direction away from the surface of the first chip 1' and the second chip 4'.

[0144] The adhesion barrier layer includes but is not limited to any one or any combination of a chromium (Cr) layer, a titanium (Ti) layer, a nickel (Ni) layer, a tungsten (W) layer, etc. The oxidation-resistant layer can include a gold (Au) layer, etc. The thickness of the adhesion barrier layer can be 20 nm to 50 nm, and the thickness of the oxidation-resistant layer can be 80 nm to 100 nm.

[0145] The bottom metal layer 9 can enhance the adhesion between the superconducting cylinder 8 and the first superconducting layer 2 and the second superconducting layer 5, and improve the stability of the superconducting cylinder 8.

[0146] Alternatively, in some embodiments, part of the circuit in the readout control unit 3 can also be made on the second chip 4'.

[0147] The present application also provides a quantum computer including the flip-chip quantum chip described in any of the above embodiments.

[0148] The embodiments in the present specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other.

[0149] The superconducting quantum chip and the preparation method thereof provided in the application are described in detail above. The principles and implementation manners of the application are described by applying specific examples, and the above description of the examples is only used to help understand the scheme of the application and the core idea thereof. It should be pointed out that, for ordinary skilled persons in the technical field, some improvements and modifications can be made to the application without departing from the principles of the application, and these improvements and modifications also fall within the protection scope of the application.

Claims

1. An inverted quantum chip, characterized by, Comprise: a first chip and a second chip oppositely arranged, the first chip and the second chip are flip-chip connected; a superconducting column and a photoresist spacer between the first chip and the second chip, the superconducting column is inside the photoresist spacer; wherein the superconducting column is used for electrically connecting the first chip and the second chip, and the photoresist spacer is used for uniformly supporting the first chip and the second chip.

2. The inverted quantum chip of claim 1, wherein, Further comprise: a second superconducting layer and a Josephson junction on the surface of the second chip relative to the first chip.

3. The inverted quantum chip of claim 2, wherein, Further comprise: a first superconducting layer and a readout control unit on the surface of the first chip relative to the second chip.

4. The inverted quantum chip of claim 3, wherein, a bottom metal layer between the first superconducting layer and the superconducting column, and between the second superconducting layer and the superconducting column, the bottom metal layer comprises an adhesion barrier layer and an oxidation-resistant layer stacked in a direction away from the surface of the first chip and the second chip.

5. The inverted quantum chip of claim 4, wherein, The adhesion barrier layer comprises any one or any combination of a chromium layer, a titanium layer, a nickel layer, and a tungsten layer; and / or, the oxidation-resistant layer comprises a gold layer.

6. The inverted quantum chip of claim 1, wherein, The thickness of the photoresist spacer ranges from 5 microns to 10 microns.

7. The inverted quantum chip of claim 3, wherein, The first superconducting layer comprises any one of an aluminum superconducting layer, a tantalum superconducting layer, and a niobium superconducting layer; and / or, the second superconducting layer comprises any one of a superconducting layer, a tantalum superconducting layer, and a niobium superconducting layer.

8. The inverted quantum chip of claim 1, wherein, The flip-chip quantum chip is a superconducting quantum chip, and the superconducting column is an indium column.

9. The inverted quantum chip of any one of claims 1 to 8, wherein, The material of the photoresist spacer comprises SU-8 series photoresist.

10. A quantum computer, comprising: Comprise the flip-chip quantum chip according to any one of claims 1 to 9.

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