Semiconductor device
By using a seed layer and a wire layer structure in semiconductor processing, combined with multiple wet etching processes to form a bottom cut, the problem of poor wire yield in fine wire layers is solved, the reliability of wires and wiring space are improved, and the chip size is reduced.
Patent Information
- Application Number
- CN202422986443.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-12-04
AI Technical Summary
In semiconductor manufacturing, the redistribution layer of fine wires can easily lead to poor wire yield.
By forming conductive pads on the dielectric layer and using a seed layer and wire layer structure, combined with multiple wet etching processes, a wire structure with undercut is formed to enhance the adhesion between the wires and the dielectric layer and reduce the risk of peeling.
It improves the reliability of the conductors, reduces the occurrence of conductor breaks, increases the routing space, reduces the chip size, and reduces the number of conductor layers.
Smart Images
Figure CN223566577U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Some embodiments of the present utility model relate to semiconductor devices. BACKGROUND
[0002] In semiconductor processes, redistribution layers (RDL) can be used to add additional metal layers on the surface of a chip or wafer to redistribute and optimize the layout of circuit interconnections. In modern semiconductor industry, the wires in the redistribution layer will be formed thinner and thinner to accommodate enough wires in a smaller chip. However, when the wires are formed thinner, other problems can be caused, resulting in poor wire yield. SUMMARY
[0003] Some embodiments of the present utility model provide a semiconductor device, including a conductive pad, a dielectric layer, and a wire structure. The dielectric layer is above the conductive pad. The wire structure penetrates the dielectric layer and is electrically connected to the conductive pad, and includes a first seed layer, a second seed layer, and a wire layer. The first seed layer is on the dielectric layer. The second seed layer is on the first seed layer, wherein the width of the top of the second seed layer is substantially the same as the width of the first seed layer, and there is a first undercut between the first seed layer and the second seed layer. The wire layer is on the second seed layer.
[0004] In some embodiments, the angle of the first undercut is less than 60 degrees and greater than 15 degrees.
[0005] In some embodiments, the ratio of the width of the first undercut to the thickness of the second seed layer is between 0.6 and 1.8.
[0006] In some embodiments, the width of the top of the second seed layer is 1-8 microns.
[0007] In some embodiments, the width of the top of the second seed layer is substantially the same as the width of the wire layer.
[0008] In some embodiments, there is a second undercut between the first seed layer and the second seed layer, and the first undercut and the second undercut are located on opposite sides of the second seed layer.
[0009] In some embodiments, the first undercut is defined by the inclined side wall of the second seed layer and the upper surface of the first seed layer.
[0010] In some embodiments, the width of the top of the second seed layer is greater than the width of the bottom of the second seed layer.
[0011] In some embodiments, the material of the second seed layer is different from that of the first seed layer.
[0012] In some embodiments, the material of the second seed layer is the same as that of the wire layer. Attached Figure Description
[0013] Figures 1 to 9 A cross-sectional view of a semiconductor manufacturing apparatus according to some embodiments of the present invention is shown.
[0014] Figure 10 Draw Figure 9 A magnified view of region M. Detailed Implementation
[0015] Figures 1 to 9 A cross-sectional view illustrating a semiconductor manufacturing apparatus according to some embodiments of the present invention is shown. (Reference) Figure 1 A conductive pad 110, a passivation layer 120, and a sealing ring 130 may be formed on a substrate 100. The passivation layer 120 is formed on the conductive pad 110 and the sealing ring 130, exposing a first portion 110A of the conductive pad 110. The sealing ring 130 surrounds the semiconductor device. In some embodiments, the substrate 100 may be a carrier such as a wafer or interposer in which an integrated circuit is formed, and the conductive pad 110, the passivation layer 120, and the sealing ring 130 are formed in the fanout region of the wafer. In some embodiments, the conductive pad 110 may be made of a conductive material, such as a metal (e.g., aluminum). The passivation layer 120 may be made of a dielectric material. The sealing ring 130 may be made of a metal.
[0016] Next, a dielectric layer 140 is formed on the substrate 100, the conductive pad 110, and the passivation layer 120. The dielectric layer 140 covers the passivation layer 120 and the conductive pad 110, and exposes a second portion 110B of the first portion 110A of the conductive pad 110 and a portion of the passivation layer 120. In some embodiments, the dielectric layer 140 may be an organic layer, such as polyimide (PI) or polybenzoxazole (PBO).
[0017] refer to Figure 2 A seed layer 150 is formed on the dielectric layer 140, and a seed layer 160 is formed on the seed layer 150. The seed layer 150 contacts the second portion 110B of the conductive pad 110. Both seed layers 150 and 160 are formed of a conductor, such as a metal. In some embodiments, seed layers 150 and 160 are formed of different materials. For example, seed layer 150 may be formed of a material with good adhesion to the dielectric layer 140, such as titanium tungsten (TiW). Seed layer 160 may be formed of a material more suitable for forming a wire, such as copper (Cu). In some embodiments, the thickness of seed layer 150 is, for example, between 50 nanometers and 300 nanometers. The thickness of seed layer 160 is, for example, between 100 nanometers and 600 nanometers.
[0018] refer to Figure 3A patterned photoresist layer PR is formed on the seed layer 160, and the patterned photoresist layer PR includes a plurality of openings O. Specifically, the openings O can include an opening O1 and a plurality of openings O2 (e.g., two). The opening O1 has a larger width, and a portion of the opening O1 overlaps the conductive pad 110. The openings O2 have a smaller width, and do not overlap the conductive pad 110. The opening O1 will be used to electrically connect a subsequently formed conductive line layer to the underlying conductive pad 110, and the openings O2 will be used to form a conductive line layer having a fine line width. The openings O2 have a width W1, the distance between the two openings O2 has a width W2, and the width W1 is greater than the width W2. The width W1 of the openings O2 is greater than the predetermined width of the subsequently formed conductive line layer (e.g., the widths W10 of the second and third portions 170B, 170C of the conductive line layer 170). Figure 10 In some embodiments, the width W1 of the openings O2 can be between 2 micrometers and 8 micrometers, and the width W2 between the two openings O2 can be between 1 micrometer and 8 micrometers. For example, when the predetermined width of the subsequently formed conductive line layer (e.g., the second and third portions 170B, 170C of the conductive line layer 170) is 2 micrometers, the width W1 can be 3.5 micrometers, and the width W2 can be 1 micrometer. However, the present application is not limited thereto. Figure 10
[0019] Referring to FIG. 1C, a seed layer 160 is formed on the conductive pad 110. The seed layer 160 can be formed by a deposition process, such as a physical vapor deposition (PVD) process. The seed layer 160 can be made of a conductive material, such as a metal. In some embodiments, the seed layer 160 is made of the same material as the conductive pad 110, such as copper. In some embodiments, the seed layer 160 is made of a different material than the conductive pad 110. Figure 4 A conductive line layer 170 is formed in the openings O on the seed layer 160. Specifically, electroplating can be used to form the conductive line layer 170 in the openings O. The formation of the conductive line layer 170 is limited by the patterned photoresist layer PR, such that the conductive line layer 170 is divided into a first portion 170A, a second portion 170B, and a third portion 170C according to the patterned photoresist layer PR. The first portion 170A corresponds to the opening O1, and the second and third portions 170B, 170C correspond to the two openings O2, respectively. The width between the second and third portions 170B, 170C of the conductive line layer 170 is the width W2 between the two openings O2. Thus, the second and third portions 170B, 170C of the conductive line layer 170 have a width W1, the distance between the second and third portions 170B, 170C of the conductive line layer 170 has a width W2, and the width W1 is greater than the width W2. The first portion 170A of the conductive line layer 170 is electrically connected to the underlying conductive pad 110 through the seed layer 150 and the seed layer 160. In some embodiments, at least two of the first to third portions 170A-170C of the conductive line layer 170 can be connected to each other in a top view (not shown). The conductive line layer 170 can be made of a conductor, such as a metal. In some embodiments, the conductive line layer 170 and the seed layer 160 are made of the same material, such as copper, and the conductive line layer 170 and the seed layer 150 are made of different materials.
[0020] Next, referring to FIG. 1D, the patterned photoresist layer PR is removed. The conductive line layer 170 is then exposed. The conductive line layer 170 can be further processed, such as by a lithography process, to form a conductive line layer 170' having a fine line width. The conductive line layer 170' can be formed by a deposition process, such as a physical vapor deposition (PVD) process. The conductive line layer 170' can be made of a conductive material, such as a metal. In some embodiments, the conductive line layer 170' is made of the same material as the conductive line layer 170, such as copper. In some embodiments, the conductive line layer 170' is made of a different material than the conductive line layer 170. Figure 5 The patterned photoresist layer PR is removed. After removing the patterned photoresist layer PR, the conductive layer 170 remains on the seed layer 160. Based on the distribution of the first to third portions 170A to 170C of the conductive layer 170, the first portion 160A, the second portion 160B, and the third portion 160C of the seed layer 160 are exposed. In some embodiments, the conductive layer 170 may serve as a redistribution layer (RDL). However, this invention is not limited thereto.
[0021] refer to Figure 6 Using the conductive layer 170 as a mask, the seed layer 160 is etched. Specifically, a first wet etching process is performed to remove the first to third portions 160A to 160C of the seed layer 160 exposed by the conductive layer 170. At this time, the seed layer 160 retains its fourth portion 160D, fifth portion 160E, and sixth portion 160F. Based on the distribution of the fourth to sixth portions 160D to 160F of the seed layer 160, the first portion 150A, second portion 150B, and third portion 150C of the seed layer 150 are exposed. After etching, the fifth and sixth portions 160E and 160F of the seed layer 160 have a width W3. In some embodiments, the conductive layer 170 and the seed layer 160 are made of the same material, so the first wet etching process has substantially the same etching rate for the conductive layer 170 and the seed layer 160. The first wet etching process can further reduce the width of the second and third portions 170B and 170C of the conductive layer 170 from W1 to W4, and the width W5 between the second and third portions 170B and 170C of the conductive layer 170 is compared to the width W2 before performing the first wet etching process (shown in...). Figure 4 Therefore, the width W4 of the conductive layer 170 is substantially the same as the width W3 of the seed layer 160. In some embodiments, the width W3 can be between 1 micrometer and 8 micrometers, the width W4 can be between 1 micrometer and 8 micrometers, and the width W5 can be between 2 micrometers and 8 micrometers. For example, when the width W1 is 3.5 micrometers and the width W2 is 1 micrometer, after performing the first wet etching process, the widths W4 and W3 can be 3 micrometers, and the width W5 can be 1.5 micrometers. However, the present invention is not limited thereto. In some embodiments, the etching solution of the first wet etching process can be a mixture of phosphoric acid and hydrogen peroxide. In some embodiments, the etching time of the first wet etching process can be between 5 seconds and 40 seconds.
[0022] refer to Figure 7With the wire layer 170 and the seed layer 160 as a mask, the seed layer 150 is etched. Specifically, a second wet etching process can be performed to remove the first to third portions 150A-150C of the seed layer 150 exposed by the seed layer 160. At this time, the seed layer 160 leaves its fourth portion 150D, fifth portion 150E, and sixth portion 150F. Since the material of the seed layer 150 is different from that of the seed layer 160, the second wet etching process does not substantially etch the seed layer 160 when etching the seed layer 150. Thus, the width W6 of the seed layer 150 can be less than the width W3 of the seed layer 160 due to over-etching of the second wet etching process. In other words, the two opposite walls (e.g., left and right walls) of the fourth portion 160D of the seed layer 160 are not aligned with the two opposite walls (e.g., left and right walls) of the fourth portion 150D of the seed layer 150, respectively, the two opposite walls (e.g., left and right walls) of the fifth portion 160E of the seed layer 160 are not aligned with the two opposite walls (e.g., left and right walls) of the fifth portion 150E of the seed layer 150, respectively, and the two opposite walls (e.g., left and right walls) of the sixth portion 160F of the seed layer 160 are not aligned with the two opposite walls (e.g., left and right walls) of the sixth portion 150F of the seed layer 150, respectively, such that the second wet etching process is likely to form an undercut UC1 on the surface of the dielectric layer 140 corresponding to the fourth to sixth portions 150D-150F of the seed layer 150. In some embodiments, the width of each undercut UC1 (e.g., the horizontal distance between the left wall of the fifth portion 160E of the seed layer 160 and the left wall of the fifth portion 150E of the seed layer 150) is 0.5 micrometers. When the undercut UC1 is generated, the bonding force between the interfaces where the undercut UC1 is located can affect the structural strength. For example, when the bonding force between the interfaces where the undercut is located is weak, the structure formed thereon can be prone to peeling off. Since the undercut UC1 is formed on the surface of the dielectric layer 140, and the bonding force between the dielectric layer 140 and the seed layer 150 thereon is weak, the seed layer 150, the seed layer 160, and the wire layer 170 are prone to peeling off. The peeling off of the wire layer 170 can cause the wire to be broken. The weak bonding force between the dielectric layer 140 and the seed layer 150 thereon is caused by the different properties of the materials, e.g., one is an organic material and the other is a metal material. In some embodiments, the etching liquid of the second wet etching process can be hydrogen peroxide. In some embodiments, the etching time of the second wet etching process can be between 3 minutes and 20 minutes.
[0023] Reference Figure 8After etching the seed layer 150, a plasma treatment P can be performed to remove metal residues on the dielectric layer 140. These metal residues can be byproducts of the etching of the seed layer 150, seed layer 160, and conductive layer 170 as described above. Removing these metal residues reduces the likelihood of leakage current in the conductive layer 170.
[0024] refer to Figure 9 Then, the conductive layer 170 and the seed layer 160 are etched again. Specifically, a third wet etching process can be performed to reduce the width of the seed layer 160 and the conductive layer 170. Figure 10 Draw Figure 9 A magnified view of region M. (Reference) Figure 9 and Figure 10 After etching the seed layer 160 and the conductive layer 170 again, the semiconductor device 90 may include a substrate 100, a conductive pad 110, a passivation layer 120, a sealing ring 130, a dielectric layer 140, and a conductive structure 180. The conductive structure 180 includes a seed layer 150, a seed layer 160, and a conductive layer 170. The dielectric layer 140 is above the conductive pad 110. The conductive structure 180 penetrates the dielectric layer 140 and is electrically connected to the conductive pad 110. The seed layer 150 is on the dielectric layer 140. The seed layer 160 is on the seed layer 150, wherein an undercut UC2 is formed between the seed layer 150 and the seed layer 160. The conductive layer 170 is on the seed layer 160. Here, the "undercut UC2" can be considered as a groove formed between the seed layer 160 and the seed layer 150. For example, the fifth portion 160E of the seed layer 160 may have a substantially vertical left sidewall and an inclined sidewall extending downward from the substantially vertical sidewall, wherein the undercut UC2 is defined by the inclined sidewall of the fifth portion 160E of the seed layer 160 and the substantially horizontal upper surface of the fifth portion 150E of the seed layer 150.
[0025] The third wet etching process causes the top of each of the fifth and sixth portions 160E, 160F of the seed layer 160 to have a width W7, and the bottom of each of the fifth and sixth portions 160E, 160F of the seed layer 160 to have a width W8, which is less than the width W7. In other words, the third wet etching process reduces the top of each of the fifth and sixth portions 160E, 160F of the seed layer 160 from the width W3 to the width W7, and the width of the bottom of each of the fifth and sixth portions 160E, 160F from the width W3 to the width W8. In some embodiments, the width W7 is substantially the same as the width W6. In some embodiments, the wire layer 170 and the seed layer 160 are made of the same material, and thus the third wet etching process has substantially the same etching rate on the fifth and sixth portions 160E, 160F of the seed layer 160 and the wire layer 170. The third wet etching process can also reduce the second and third portions 170B, 170C of the wire layer 170 from the width W4 to a width W10. In some embodiments, the width W7 is substantially the same as the width W10.
[0026] Since the material of the seed layer 160 and the wire layer 170 is different from the material of the seed layer 150, the third wet etching process does not substantially etch the seed layer 150 when etching the seed layer 160 and the wire layer 170, or the third wet etching process has a greater etching rate on the seed layer 160 and the wire layer 170 than on the seed layer 150. Thus, Figure 8The undercut UC1 in the fifth and sixth portions 150E, 150F of the seed layer 150 disappears due to the reduced width of the seed layer 160 and the wire layer 170. Because the bottom corners of the seed layer 160 are more easily etched by the third wet etching process, the width W8 of the bottom of each of the fifth and sixth portions 160E, 160F of the seed layer 160 can be smaller than the width W7 of the top of each of the fifth and sixth portions 160E, 160F of the seed layer 160, and an undercut UC2 is formed on the surface of each of the fifth and sixth portions 150E, 150F of the seed layer 150. The undercut UC2 formed on the surface of each of the fifth and sixth portions 150E, 150F of the seed layer 150 concentrates the force on the undercut UC2 when an external force is applied, and the interface where peeling occurs is between the seed layer 150 and the seed layer 160, which has a stronger bonding force than the bonding force between the seed layer 150 and the dielectric layer 140, so that the wire structure 180 is less likely to peel off and the open circuit problem can be reduced. In some embodiments, the angle a of the undercut UC2 is less than 60 degrees. In some embodiments, the angle a of the undercut UC2 is greater than 15 degrees. Here, the "angle a" can be the angle between the inclined sidewall of the seed layer 160 and the upper surface of the seed layer 150. In some embodiments, the ratio of the width W9 of the undercut UC2 to the thickness T1 of the seed layer 160 is between 0.6 and 1.8. For example, when the thickness T1 of the seed layer 160 is 0.3 microns, the width W9 of the undercut UC2 can be between 0.18 microns and 0.54 microns. In some embodiments, there is also an undercut UC3 between the fifth portion 150E of the seed layer 150 and the fifth portion 160E of the seed layer 160, and the undercut UC2 and the undercut UC3 are located on opposite sides of the fifth portion 160E of the seed layer 160; and there is also an undercut UC3 between the sixth portion 150F of the seed layer 150 and the sixth portion 160F of the seed layer 160, and the undercut UC2 and the undercut UC3 are located on opposite sides of the sixth portion 160F of the seed layer 160.
[0027] In addition, because the third wet etching process further reduces the line width of the wire layer 170, the wire layer 170 formed can have a finer line width to increase the space for the wire. For example, in some embodiments, after the third wet etching process, the width W7 of the top of the seed layer 160 and the width W10 of the wire layer 170 can be between 1 micron and 8 microns, and the width W11 of the distance between the wire layers 170 can be between 2 microns and 8 microns. In this way, the wafer size can be reduced, and the number of layers of the wire layer 170 can also be reduced. In some embodiments, the etching solution of the third wet etching process can be a mixture of phosphoric acid and hydrogen peroxide. In some embodiments, the etching time of the third wet etching process can be within 5 seconds.
[0028] The above merely illustrates some of the embodiments of the present application, and is not all the embodiments. Any equivalent changes made by those skilled in the art to the technical scheme of the present application by reading the specification of the present application are all covered by the claims of the present application.
[0029] SYMBOL DESCRIPTION
[0030] 90: semiconductor device
[0031] 100: substrate
[0032] 110: conductive pad
[0033] 110A, 150A, 160A, 170A: first portion
[0034] 110B, 150B, 160B, 170B: second portion
[0035] 120: passivation layer
[0036] 130: sealing ring
[0037] 140: dielectric layer
[0038] 150, 160: seed layer
[0039] 150C, 160C, 170C: third portion
[0040] 150D, 160D: fourth portion
[0041] 150E, 160E: fifth portion
[0042] 150F, 160F: sixth portion
[0043] 170: wire layer
[0044] 180: wire structure
[0045] a: angle
[0046] M: region
[0047] O, O1, O2: opening
[0048] P: plasma treatment
[0049] PR: photoresist layer
[0050] T1: thickness
[0051] UC1, UC2, UC3: undercut
[0052] W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11: width
Claims
1. A semiconductor device, characterized by comprising: Comprising: a conductive pad; a dielectric layer over the conductive pad; and a wire structure penetrating through the dielectric layer and electrically connected to the conductive pad, and comprising: a first seed layer on the dielectric layer; a second seed layer on the first seed layer, wherein a top portion of the second seed layer has substantially the same width as the first seed layer, and a first undercut is between the first seed layer and the second seed layer; and a wire layer on the second seed layer. An angle of the first undercut is less than 60 degrees and greater than 15 degrees.
2. The semiconductor device according to claim 1, wherein A ratio of a width of the first undercut to a thickness of the second seed layer is between 0.6 and 1.
8.
3. The semiconductor device according to claim 1, wherein The width of the top portion of the second seed layer is between 1 micrometer and 8 micrometers.
4. The semiconductor device according to claim 1, wherein The width of the top portion of the second seed layer is substantially the same as a width of the wire layer.
5. The semiconductor device according to claim 1, wherein A second undercut is between the first seed layer and the second seed layer, and the first undercut and the second undercut are on opposite sides of the second seed layer.
6. The semiconductor device according to claim 1, wherein The first undercut is defined by an inclined sidewall of the second seed layer and an upper surface of the first seed layer.
7. The semiconductor device according to claim 1, wherein The width of the top portion of the second seed layer is greater than a width of a bottom portion of the second seed layer.
8. The semiconductor device according to claim 1, wherein The second seed layer is of a different material than the first seed layer.
9. The semiconductor device according to claim 1, wherein The second seed layer is of the same material as the wire layer.
10. The semiconductor device according to claim 1, wherein