Packaging module and packaging circuit
By using connectors to interconnect between chips and functional modules, the problems of increasing package size and difficulty in improving interconnect density in existing technologies are solved, achieving efficient package module and circuit design, and reducing losses and costs.
Patent Information
- Application Number
- CN202421565331.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-03
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-07-03
AI Technical Summary
Existing technologies struggle to effectively achieve efficient interconnection between chips and between functional modules, leading to problems such as increased package size, high losses, high costs, and difficulty in improving interconnection density.
By using packaged modules and packaged circuits, interconnection between chips and functional modules is achieved through connectors, which shortens the transmission distance, reduces losses, simplifies the interconnection interface design, and increases interconnection density.
It achieves efficient interconnection between chips and functional modules, reduces package size and loss, simplifies interconnect interface design, increases interconnect density, and avoids unrestrained expansion of package size and cost.
Smart Images
Figure CN223566619U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor, more particularly, a kind of packaging module and packaging circuit. BACKGROUND
[0002] With the explosive growth of cloud computing and AI computing, the demand for performance improvement of single-chip computing power and expansion of computing power of multi-chip cluster is also increasing, therefore, how to realize efficient interconnection of chips to meet the demand for performance evolution is particularly important. SUMMARY
[0003] Therefore, the utility model embodiment provides a packaging module and packaging circuit to realize the interconnection between chips, functional modules or between chips and functional modules through connectors, shorten the transmission distance between components, reduce the loss, and at the same time, as the transmission distance between components is shortened, the required driving is reduced, so the design of interconnection interface can be simplified, thereby the size of interconnection interface can be reduced and the interconnection density can be improved.
[0004] In a first aspect, the utility model embodiment provides a packaging module, which comprises:
[0005] at least two components, the components being chips or functional modules; and
[0006] at least one connector for realizing the interconnection of the components through corresponding connection lines.
[0007] Optionally, the contact spacing of the connector is determined according to the size of the components and / or the required interconnection density.
[0008] Optionally, the packaging module comprises a component carrier board, and the components and the corresponding connectors are arranged on the corresponding component carrier boards.
[0009] Optionally, the at least one connector corresponding to the components is arranged on one or more sides, the front or the back of the corresponding component carrier board.
[0010] Optionally, the connection line is made of metal wire, optical fiber or flexible board.
[0011] Optionally, the connector is attached by reflow, hot pressing, laser-assisted welding or plug-in.
[0012] Optionally, the component carrier board can be made of organic carrier board, ceramic carrier board, glass carrier board, silicon-based carrier board or RDL.
[0013] Optionally, the functional module is a storage module, a computing acceleration module or a network interconnection module.
[0014] Optionally, the assembly has a plurality of corresponding interconnection interfaces and a corresponding driving circuit of the interconnection interfaces, and output power of the driving circuit is determined according to a communication transmission distance of the assembly.
[0015] In a second aspect, the utility model embodiment provides a packaging circuit, the packaging circuit includes:
[0016] A circuit board; and
[0017] At least one packaging module arranged on the circuit board.
[0018] The packaging module embodiment of the utility model embodiment includes at least two assemblies and at least one connector for realizing the interconnection of the assemblies through corresponding connecting lines, wherein the assembly is a chip or a functional module. Therefore, the utility model embodiment can realize the interconnection between chips, between functional modules or between chips and functional modules through the connector, shorten the transmission distance between assemblies, reduce the loss, and simultaneously, since the transmission distance between assemblies is shortened, the required driving is reduced, so the design of the interconnection interface can be simplified, thereby the size of the interconnection interface can be reduced and the interconnection density can be improved. BRIEF DESCRIPTION OF DRAWINGS
[0019] The above and other objects, features and advantages of the utility model will become more apparent from the following description of the utility model embodiments with reference to the accompanying drawings, in which:
[0020] Figures 1-3 It is the chip packaging schematic diagram of related comparative example;
[0021] Figure 4 It is the packaging module schematic diagram of the interconnection between two chips of the utility model embodiment;
[0022] Figure 5 It is the packaging module schematic diagram of the interconnection of a plurality of chips of the utility model embodiment;
[0023] Figure 6 It is the packaging module schematic diagram of the interconnection of a plurality of chips of another utility model embodiment;
[0024] Figure 7 It is the packaging module schematic diagram of the interconnection between chip and functional module of the utility model embodiment;
[0025] Figure 8 It is the schematic diagram of the packaging circuit of the utility model embodiment. DETAILED DESCRIPTION
[0026] The present application is described herein below with reference to examples, but the present application is not limited to these examples. In the following detailed description of the present application, some specific details are described in order to provide a thorough understanding of the present application. The present application can be fully understood without these detailed descriptions. In order to avoid obscuring the essence of the present application, well-known methods, procedures, processes, elements and circuits are not described in detail.
[0027] In addition, it should be understood that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
[0028] Meanwhile, it should be understood that, in the following description, "circuitry" refers to a conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is said to be "connected to" another element or said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0029] Unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For ordinary skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0030] For ease of description, spatially relative terms such as "inner", "outer", "below", "lower", "bottom", "top", "upper", and the like, can be used herein for describing an element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
[0031] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0032] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0033] With the explosive growth of cloud computing and AI computing, the demand for scaling up single-chip computing power (i.e., improving the performance of a single chip to meet the ever-increasing computing needs) and scaling out multi-chip clusters (i.e., expanding computing power by increasing the number of chips or the size of the cluster) is also increasing. Therefore, high-efficiency, high-bandwidth interconnects between chips and between chips and modules are particularly important. Due to limitations in package size and RDL manufacturing, even with advanced packaging technologies such as chiplets, it is still difficult for chip products with HighIO / High bandwidth interconnects to meet the demands of their performance evolution.
[0034] Chiplet packaging technology is an integrated circuit packaging technology that integrates multiple small chips into a single package to form a powerful system-on-a-chip (SoC).
[0035] Figures 1-3 This is a schematic diagram of the chip package for comparison. For example... Figure 1 As shown in the comparison, chip Die1 is interconnected via an RDL layer. The RDL (Redistribution Layer) is primarily used at the package level to manage and optimize the interconnections between chips. The RDL layer is a metallic wiring layer that allows for the replanning and redistribution of interconnections between chips at the package level to achieve more efficient signal transmission. For example... Figure 1 As shown, all chip dies are placed on the RDL layer. Although high-bandwidth interconnects are achieved, the chip size and wiring complexity have increased significantly due to chip performance requirements. This has led to an increasing RDL size, which poses a great challenge to the production and assembly of large-size RDLs. Furthermore, the RDL layer has further expanded the package size, bringing a series of engineering challenges to chip board-level assembly.
[0036] like Figure 2As shown in the comparative example, the chip Die2 is located on the chip carrier board and is interconnected through the PCB traces. However, the chip interconnection through the PCB board results in a long transmission distance, large loss, and a strong interconnection drive required for the long transmission distance, which causes insufficient chip size and large power consumption. Meanwhile, the interconnection bandwidth is difficult to improve due to the density of the PCB traces.
[0037] As Figure 3 As shown in the comparative example, the chip Die3 is interconnected with the module through the PCB traces. For a High I / O product, a large number of I / O pins are required, which causes the chip package size to increase and brings about manufacturing and cost challenges. Moreover, the bandwidth evolution is difficult to achieve due to the density of the PCB interconnection, which brings great challenges to the design of the chip interface and the system interconnection design.
[0038] Therefore, the embodiment of the present application provides a packaging module, which includes at least two components and at least one connector for realizing the interconnection of the components through corresponding connection lines, wherein the components are chips or functional modules. The embodiment of the present application can integrate the connector when the chips and / or functional modules are packaged, realize the interconnection between the components (chips or functional modules) through corresponding connection lines (cables), shorten the transmission distance between the components, reduce the loss, and simplify the design of the interconnection interface due to the reduced transmission distance between the components and the required drive, thereby reducing the size of the interconnection interface and improving the interconnection density. Meanwhile, for a High Bandwidth product, the embodiment of the present application can further split the Chiplet design based on the 2.5D advanced packaging, avoid the production and cost challenges caused by the uncontrolled expansion of the interposer (interposer) / RDL size. For a High I / O product, the embodiment of the present application can realize the interconnection to achieve the purpose of not requiring corresponding pins (pins), thereby avoiding the production and cost challenges caused by the uncontrolled expansion of the package size.
[0039] In an optional implementation, the chip of the embodiment can be a chip die. The functional module is a circuit module with independent functions, such as various storage modules, computing acceleration modules, network interconnection modules, etc. Among them, the storage module is a hardware device for data storage, such as RAM (Random Access Memory) module, SSD (Solid State Disk) module, HDD (Hard Disk Drive) module, Flash Memory Module (Flash Memory Module), NVMe SSD module, etc. The storage module can be integrated. The computing acceleration module is a hardware component for enhancing the processing speed of a specific type of computing task, such as GPU (Graphics Processing Unit), FPGA (Field-Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), TPU (Tensor Processing Unit), DPU (Data Processing Unit), AI accelerator, GPGPU (General-Purpose computing on Graphics Processing Units), etc. The network interconnection module is a hardware device or component responsible for data transmission in network communication, enabling different computer systems or devices to communicate and exchange information with each other, such as Wireless Access Point (WAP), Fiber Transceiver, Modem, etc. It should be understood that the utility model embodiment can be applied to various chips and functional modules that need to be interconnected, and the above is only an illustrative example, and the utility model embodiment is not limited thereto.
[0040] In an optional implementation, the connector of the embodiment can be a Fine Pitch connector. The Fine Pitch connector is a connector with very close contact pitch. The pitch refers to the distance between the centers of two adjacent contact points in the connector. It should be understood that the embodiment does not limit the type of connector, and existing connectors that can be adapted to the interconnection between chips, or between chips and modules, or between modules, or connectors designed in the future as the manufacturing technology develops can be applied in the embodiment.
[0041] Further, the contact spacing of the connector of the embodiment can be determined according to the size of the assembly and / or the required interconnection density. Since the size of the chip or functional module is generally small, the embodiment can set the contact spacing of the connector to increase the interconnection density as much as possible within the limited size of the assembly (chip or functional module). In another alternative implementation, the contact spacing of the connector of the embodiment can also be determined according to the interconnection density required by the computing requirement of the system, so as to increase the contact spacing of the connector as much as possible within the limited size of the assembly while meeting the interconnection density, so as to reduce the production difficulty and cost and improve the production efficiency.
[0042] In an alternative implementation, the connector of the embodiment can be attached by reflow, thermal compression bonding, laser-assisted welding, or through-hole technology, according to the actual integration requirement.
[0043] Reflow attachment, also known as reflow soldering, is mainly used for welding of surface mount technology (SMT) components. It uses the characteristics of solder paste to melt and form intermetallic bonds during preheating and heating, so as to fix the device on the corresponding circuit board or carrier board.
[0044] Thermal compression bonding, also known as thermal compression bonding or thermal compression welding, is a method of forming a reliable electrical and mechanical connection by tightly contacting two surfaces under high temperature and high pressure, using conductive glue, anisotropic conductive film (ACF) or other conductive materials.
[0045] Laser-assisted welding is a welding method that combines traditional welding techniques and laser technology. It uses laser as a heat source or auxiliary heat source, combined with conventional welding processes (such as MIG / MAG, TIG or resistance welding), to improve welding quality and efficiency.
[0046] Through-hole technology (THT) is an electronic component mounting technology, which is opposite to surface mount technology (SMT). In THT, the pins of electronic components pass through the holes on the circuit board (PCB), and then are welded on the other side to achieve mechanical and electrical connection.
[0047] Since the connector can be adapted to multiple types of mounting manners, the connector can be applied in a wide range, i.e., the connector can be applied in chip packages mounted in various manners, thereby simplifying the packaging difficulty. It should be understood that the above mounting manners are only exemplary, and other existing mounting manners and new mounting manners developed in the future that can mount the connector can be applied in the embodiment, and the embodiment does not limit the mounting manner of the connector.
[0048] In an optional implementation, the transmission medium used by the cable of the connector of the embodiment can be a metal wire (such as copper, etc.), an optical fiber, or a flexible board, etc. The transmission medium can be selected according to actual production information, attribute information of the chip or functional module, etc. The actual production information can include production cost, production equipment, production demand (such as interconnection density demand, etc.), etc. The attribute information of the chip or functional module can include type and / or size of the chip or functional module, etc. It should be understood that the embodiment does not limit the transmission medium used by the cable, as long as it can realize information transmission.
[0049] In an optional implementation, the packaging module of the embodiment further includes an assembly carrier board, and the assembly and the corresponding connector are arranged on the corresponding assembly carrier board.
[0050] The assembly carrier board can play a key role in integrated circuit packaging, which can be located between the assembly (chip or functional module) and the printed circuit board (such as a PCB board), and can play a role of a bridge. The assembly carrier board can transmit the electrical signals of the corresponding assembly to the printed circuit board, and at the same time, provide physical support and heat dissipation path, and can provide electrical isolation or electromagnetic shielding when needed, to prevent interference between signals.
[0051] Further optionally, the assembly carrier board can be an organic carrier board, a ceramic carrier board, a glass carrier board, a silicon-based carrier board, or an RDL type carrier board. The assembly carrier board can be a BGA (Ball Grid Array) carrier board, an FC-BGA (Flip Chip Ball Grid Array) carrier board, a CSP (Chip Scale Package) carrier board, a SiP (System in Package) carrier board, etc. It should be understood that the above carrier board types are only exemplary, and the embodiment is not limited thereto, and other types of assembly carrier boards can be applied in the embodiment, which can be selected according to the demand in actual production and application.
[0052] In an alternative implementation, one component can be interconnected with one other component via one connector, interconnected with multiple other components via one connector, interconnected with one other component via multiple connectors, or interconnected with multiple other components via multiple connectors. The number of connectors and the manner of connection for interconnecting components are not limited in the embodiment, which can meet the actual production needs.
[0053] Further alternatively, in the embodiment, the at least one connector corresponding to the component is arranged on one or more sides, the front or the back of the component carrier. That is, when one component has one corresponding connector, the connector can be arranged on the front or the back of any side of the component carrier, that is, the connection line corresponding to the connector can be led out from the front or the back of any side of the component carrier. When one component has multiple corresponding connectors, the multiple connectors can be arranged on multiple sides of the component carrier, or on the front and back of the same side, or on the front of some sides, or on the back of some sides, etc. The distribution of the multiple connectors on the corresponding component carrier is not limited in the embodiment, which can be arranged according to the actual production needs. Alternatively, the number of connectors on the component carrier can be determined according to the number of connectors, the mounting mode in the packaging process, and / or the interconnection relationship between other components, so as to reduce the packaging size and packaging difficulty while achieving interconnection.
[0054] In an alternative implementation, the components that need to be interconnected in the embodiment have multiple interconnection interfaces (such as physical layer interfaces PHY) and driving circuits corresponding to the interconnection interfaces. The output power of the driving circuit is determined according to the communication transmission distance between the components. In the embodiment, the interconnection between chips, functional modules, or chips and functional modules can be achieved through the connector, the transmission distance between the components is shortened, the required driving is reduced, the power consumption of the driving circuit of the interconnection interface is reduced, the design of the interconnection interface is simplified, and the size of the interconnection interface is reduced. Therefore, the number of interconnection interfaces can be increased under the limited size of the component, and the interconnection density is further improved.
[0055] The packaging module of the embodiment is described illustratively based on the following diagram, and it should be understood that the packaging module of the embodiment can be implemented based on any of the above embodiments, and is not limited to the following examples.
[0056] Figure 4 is a schematic diagram of the packaging module for interconnecting two chips in the embodiment of the utility model. As shown in the figure, Figure 4As shown in the figure, the chip die1 is arranged on the component carrier board 41, and the chip die2 is arranged on the component carrier board 42. The size of the component carrier board 41 corresponds to the size of the chip die1 and packaging requirements, and the size of the component carrier board 42 corresponds to the size of the chip die2 and packaging requirements. The connector c1 corresponding to the chip die1 is led out from the front surface of one side (E side) of the component carrier board 41 through the corresponding connecting line and connected to the connector c2 corresponding to the chip die2 to realize high-density interconnection. The connector c2 corresponding to the chip die2 is arranged on the front surface of one side (W side) of the component carrier board 42. Thus, the embodiment can realize the interconnection between the chip die1 and the die2 through the connectors c1 and c2, shorten the transmission distance between the chip die1 and the die2, reduce the loss, and simplify the design of the interconnection interface due to the reduced driving required by the shortened transmission distance between the chip die1 and the die2, so as to reduce the size of the interconnection interface and further improve the interconnection density.
[0057] Figure 5 It is a packaging module schematic diagram of multiple chip interconnections of the embodiment of the utility model. The chip can realize interconnection packaging with multiple other chips through multiple connectors. Figure 5 As shown in the figure, the chip die3 is arranged on the component carrier board 51, the chip die4 is arranged on the component carrier board 52, and the chip die5 is arranged on the component carrier board 53. The size of the component carrier board 51 corresponds to the size of the chip die3 and packaging requirements, the size of the component carrier board 52 corresponds to the size of the chip die4 and packaging requirements, and the size of the component carrier board 53 corresponds to the size of the chip die5 and packaging requirements. The connector c3 corresponding to the chip die3 is led out from the front surface of one side (E side) of the component carrier board 51 through the corresponding connecting line and connected to the connector c4 corresponding to the chip die4 to realize high-density interconnection between the chip die3 and the chip die4. The connector c5 corresponding to the chip die3 is led out from the front surface of the other side (S side) of the component carrier board 51 through the corresponding connecting line and connected to the connector c6 corresponding to the chip die5 to realize high-density interconnection between the chip die3 and the chip die5. The connector c4 corresponding to the chip die4 is arranged on the front surface of one side (W side) of the component carrier board 52, and the connector c6 corresponding to the chip die5 is arranged on the front surface of one side (N side) of the component carrier board 53.
[0058] Figure 6 It is another packaging module schematic diagram of multiple chip interconnections of the embodiment of the utility model. As shown in the figure, Figure 6As shown, in another alternative implementation, the connector c5 can also be arranged on the back of the assembly carrier board 51, that is, the connector c5 corresponding to the chip die 3 is led out from the back of the other side (that is, the S side) of the assembly carrier board 51 through the corresponding connecting line, and is connected to the connector c6 corresponding to the chip die 5, so as to realize the high-density interconnection between the chip die 3 and the chip die 5.
[0059] In the embodiment, the chip die 3 in the packaging module can realize high-density interconnection with the chip die 4 through the connectors c3 and c4, and realize high-density interconnection with the chip die 5 through the connectors c5 and c6. Thus, the transmission distance between the chip die 3 and the chip die 4 and the chip die 5 is shortened, and the loss is reduced. At the same time, since the transmission distance between the chip die 3 and the chip die 4 and the chip die 5 is shortened, the required driving is reduced, so the design of the interconnection interface can be simplified, thereby the size of the interconnection interface can be reduced, and the interconnection density is further improved.
[0060] Figure 7 It is a packaging module schematic diagram of the chip and the functional module interconnection of the embodiment of the utility model. As shown in the figure, Figure 7 As shown, the functional module M1 has at least one integrated circuit chip chip to execute a specific function. The functional module M1 is provided with a corresponding connector c8, the connector c8 is led out from one side of the functional module M1 through the corresponding connecting line, and is connected to the connector c7 corresponding to the chip die 6, so as to realize the high-density interconnection between the functional module M1 and the chip die 6. Wherein, the connector c7 corresponding to the chip die 6 is arranged on the front of one side of the assembly carrier board 71. Thus, the embodiment can realize the interconnection between the functional module M1 and the chip die 6 through the connectors c1 and c2, the transmission distance between the functional module M1 and the chip die 6 is shortened, and the loss is reduced. At the same time, since the transmission distance between the functional module M1 and the chip die 6 is shortened, the required driving is reduced, so the design of the interconnection interface can be simplified, thereby the size of the interconnection interface can be reduced, and the interconnection density is further improved.
[0061] In other alternative implementations, the embodiment can also realize high-density interconnection between functional modules, high-density interconnection between chips and chips and functional modules, and the like, which will not be exemplarily described one by one here.
[0062] The embodiment of the utility model can realize the interconnection between the chips, between the functional modules or between the chip and the functional module through the connector, shorten the transmission distance between the components, reduce the loss, and simultaneously, because the transmission distance between the components is shortened, the required driving is reduced, thus the design of the interconnection interface can be simplified, the size of the interconnection interface can be reduced, and the interconnection density can be improved. Meanwhile, for the High Bandwidth product, the embodiment of the utility model can realize the further splitting of the Chiplet design based on the 2.5D advanced packaging, avoid the production and manufacturing challenge and the cost challenge caused by the uncontrolled expansion of the interposer (interposer) / RDL size. For the High I / O product, the embodiment of the utility model can realize the interconnection to achieve the purpose that the I / O does not require the corresponding pin (Pin), and thus avoid the production and manufacturing challenge and the cost challenge caused by the uncontrolled expansion of the packaging size.
[0063] Figure 8 The utility model discloses an encapsulation circuit's schematic diagram. Another embodiment of the utility model still provides a kind of encapsulation circuit, wherein, encapsulation circuit includes circuit board and at least one encapsulation module being arranged on circuit board, to realize corresponding function. As shown in Figure 8 The encapsulation circuit of the embodiment includes circuit board 81 (for example, printed circuit board PCB) and encapsulation module 82 arranged on the circuit board. Wherein, encapsulation module 82 can be packaged based on actual production demand using any of the above implementation ways.
[0064] In an alternative implementation, the encapsulation circuit can also include other encapsulation modules, chips, or peripheral circuits of the encapsulation modules, etc. to realize corresponding functions, and the embodiment does not limit this.
[0065] The encapsulation module in the encapsulation circuit of the embodiment of the utility model can realize the interconnection between the chips, between the functional modules or between the chip and the functional module through the connector, shorten the transmission distance between the components, reduce the loss, and simultaneously, because the transmission distance between the components is shortened, the required driving is reduced, thus the design of the interconnection interface can be simplified, the size of the interconnection interface can be reduced, and the interconnection density can be improved. Meanwhile, for the High Bandwidth product, the embodiment of the utility model can realize the further splitting of the Chiplet design based on the 2.5D advanced packaging, avoid the production and manufacturing challenge and the cost challenge caused by the uncontrolled expansion of the interposer (interposer) / RDL size. For the High I / O product, the embodiment of the utility model can realize the interconnection to achieve the purpose that the I / O does not require the corresponding pin (Pin), and thus avoid the production and manufacturing challenge and the cost challenge caused by the uncontrolled expansion of the packaging size.
[0066] The above descriptions are only the preferred embodiment of the application, not intended to limit the application. The application can be variously changed and modified by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.
Claims
1. A packaging module, characterized by The package module comprises: at least two components, the components being chips or functional modules; and one or more connectors corresponding to each of the components, for realizing interconnection of the components through corresponding connection lines, the contact spacing of the connectors corresponding to each of the components being determined according to the size of the components and / or required interconnection density; wherein the package module further comprises component carrier boards, the components and corresponding connectors being arranged on corresponding component carrier boards, the size of the component carrier boards corresponding to the size of the chips arranged on the component carrier boards and packaging requirements; the connection lines being selected according to actual production information and attribute information of the chips or functional modules, the attribute information of the chips or functional modules including the type and / or size of the chips or functional modules; the components having corresponding multiple interconnection interfaces and corresponding driving circuits of the interconnection interfaces, the output power of the driving circuits being determined according to the communication transmission distance of the components.
2. The package module of claim 1, wherein At least one connector corresponding to each of the components is arranged on one or more sides, front or back of the corresponding component carrier board.
3. The package module of claim 1, wherein The connection lines adopt metal wires, optical fibers or flexible boards.
4. The package module of claim 1, wherein The connectors are attached through reflow, hot pressing, laser-assisted welding or plug-in.
5. The package module of claim 1, wherein The component carrier boards adopt organic carrier boards, ceramic carrier boards, glass carrier boards, silicon-based carrier boards or re-distribution layers.
6. The package module of claim 1, wherein The functional modules are storage modules, computing acceleration modules or network interconnection modules.
7. A packaged circuit, characterized by The package circuit comprises: a circuit board; and at least one package module according to any one of claims 1-6 arranged on the circuit board.