Packaging structure and bare chip structure

Abstract

A package structure and a die structure are provided. The package structure includes an interconnect structure, a first logic die, a molding material, a conductive via, and a redistribution layer. The interconnect structure is attached to the package substrate. A first logic die is disposed over the interconnect structure. The first logic die includes an upper through-silicon via on an upper portion of the first logic die and a lower through-silicon via on a lower portion of the first logic die, and the lower through-silicon via is electrically connected to the interconnect structure. An upper portion of the first logic die includes a device layer and a power transfer layer, and an upper through-silicon via penetrates the device layer and is physically connected to the power transfer layer. The molding material is over the interconnect structure and surrounds the first logic die. The conductive through hole penetrates through the mold sealing material. A redistribution layer is over the first logic die and the molding material. The redistribution layer is electrically connected to the upper silicon through hole and the conductive through hole of the first logic die.

Description

TECHNICAL FIELD

[0001] The utility model embodiment relates to a kind of packaging structure, die structure, more particularly to a kind of packaging structure, die structure with through device layer of Silicon Via and physical connection to power transmission layer. BACKGROUND

[0002] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. Individual dies are typically packaged separately. Packaging not only provides protection from environmental contamination for the semiconductor devices, but also provides a connection interface for the semiconductor devices packaged therein.

[0003] Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked on top of each other, such as package-on-package (PoP) and system-in-package (SiP) packaging technologies. Some three dimensional integrated circuits are fabricated on a semiconductor wafer level by placing dies on top of dies. Three dimensional integrated circuits provide improved integration density and other advantages, such as faster speed and higher bandwidth, due to, for example, reduced interconnect length between stacked dies. However, there are still many challenges associated with three dimensional integrated circuits. SUMMARY

[0004] The utility model discloses a kind of packaging structure and die structure, to solve at least one of the above problems.

[0005] The utility model embodiment provides a kind of packaging structure, including interconnect structure, first logic die, mold sealing material, conductive via and redistribution layer. Interconnect structure is attached to packaging substrate. First logic die is arranged above interconnect structure. First logic die includes upper Silicon Via (TSV) on the upper portion of first logic die and lower Silicon Via on the lower portion of first logic die, and lower Silicon Via is electrically connected to interconnect structure. The upper portion of first logic die includes device layer and power transmission layer, and upper Silicon Via penetrates device layer and is physically connected to power transmission layer. Mold sealing material is located above interconnect structure and surrounds first logic die. Conductive via penetrates mold sealing material. Redistribution layer is located above first logic die and mold sealing material. Redistribution layer is electrically connected to the upper Silicon Via of first logic die and conductive via.

[0006] According to one embodiment of the utility model, the mold sealing material exposes the upper Silicon Via of the first logic die.

[0007] According to one of the embodiments of the present application, the first logic die further comprises: a first substrate, wherein the lower through-silicon via penetrates through the first substrate; and a second substrate, wherein the upper through-silicon via penetrates through the second substrate, wherein a device in the device layer is separated from the upper through-silicon via in a vertical direction.

[0008] According to one of the embodiments of the present application, in a vertical direction, a height of the upper through-silicon via is different from a height of the conductive via.

[0009] According to one of the embodiments of the present application, a second logic die is further included, which is arranged adjacent to the first logic die and electrically connected to the conductive via.

[0010] According to one of the embodiments of the present application, a device element is further included, which is located above the redistribution layer.

[0011] The embodiment of the present application provides a die structure, which comprises a first packaging element and a second packaging element. The first packaging element comprises a first through-silicon via in a first substrate, a first device layer above the first substrate, and a first power transmission layer above the first device layer. The first through-silicon via extends to the first power transmission layer. The first device layer comprises a plurality of first devices, and the first devices are electrically connected to the first through-silicon via. The second packaging element comprises a second through-silicon via in a second substrate, a second device layer above the second substrate, and a second power transmission layer above the second device layer. The second device layer comprises a plurality of second devices, and the second devices are electrically connected to the second through-silicon via. The first device layer is bonded to the second device layer through dielectric-to-dielectric bonding and metal-to-metal direct bonding of the first power transmission layer and the second power transmission layer.

[0012] According to one of the embodiments of the present application, the first device layer further comprises a plurality of first bonding pads, the second device layer further comprises a plurality of second bonding pads, and each of the plurality of first bonding pads is aligned with one of the plurality of second bonding pads of the second device layer.

[0013] According to one of the embodiments of the present application, the plurality of first devices are in contact with the first substrate.

[0014] According to one of the embodiments of the present application, the second through-silicon via penetrates through the second device layer, and the first through-silicon via is offset from a projection area of the second through-silicon via on the second substrate. BRIEF DESCRIPTION OF DRAWINGS

[0015] The concepts of the embodiments of the present application will be better understood from the following detailed description with reference to the accompanying drawings. It should be noted that the various features of the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily expanded or reduced for the sake of clarity. Like numbers refer to like features throughout the specification and drawings.

[0016] Figures 1A-1C Cross-sectional views showing various stages of fabricating a die structure according to some embodiments of the present application.

[0017] Figures 2A-2E Cross-sectional views showing various stages of fabricating a die structure according to some embodiments of the present application.

[0018] Figures 3A-3E Cross-sectional views showing various stages of fabricating a package structure according to some embodiments of the present application.

[0019] Figure 4 Cross-sectional views showing a package structure according to some embodiments of the present application.

[0020] Figure 5A Top view schematic diagrams showing a package structure according to some embodiments of the present application.

[0021] Figure 5B Top view schematic diagrams showing a package structure according to some embodiments of the present application.

[0022] Figures 6A-6F Cross-sectional views showing various stages of fabricating a package structure according to some embodiments of the present application.

[0023] The following reference signs are used:

[0024] 10, 10A, 10B: package structure

[0025] 12: first carrier substrate

[0026] 14: second carrier substrate

[0027] 16: third carrier substrate

[0028] 20: conductive substrate

[0029] 21: dielectric layer

[0030] 22: conductive feature

[0031] 25: under bump metal structure

[0032] 26: bump structure

[0033] 30: interconnect structure

[0034] 31: Dielectric layer

[0035] 32: Electrical conductivity characteristics

[0036] 33: Under-bump metal structure

[0037] 40: Molding Material

[0038] 40A: Top surface

[0039] 43: Conductive via

[0040] 50: Redistribution layer

[0041] 51: Dielectric layer

[0042] 52: Electrical conductivity characteristics

[0043] 55: Under-bump metal structure

[0044] 56: Protrusion Structure

[0045] 60: Device Components

[0046] 70: Molding Material

[0047] 80: Packaging substrate

[0048] 85: Protrusion Structure

[0049] 100: Die Architecture (First Logic Die)

[0050] 101: First basement

[0051] 101A: Upper surface

[0052] 101B: Lower surface

[0053] 103: First Through Silicon Via (Lower Through Silicon Via)

[0054] 110:: First Device Layer

[0055] 111: First dielectric layer

[0056] 112: First electrical conductivity characteristic

[0057] 115: First device

[0058] 117: First joint pad

[0059] 120: First packaged component (lower part)

[0060] 131: Second basement

[0061] 133: Second through-silicon via (upper through-silicon via)

[0062] 140: Second device layer

[0063] 141: second dielectric layer

[0064] 142: second conductive feature

[0065] 145: second device

[0066] 147: second bond pad

[0067] 150: second packaging element (upper)

[0068] 200: die structure

[0069] 201: first substrate

[0070] 201A: upper surface

[0071] 201B: lower surface

[0072] 202: carrier substrate

[0073] 203: first through-silica via (lower through-silica via)

[0074] 210: first device layer

[0075] 211: first dielectric layer

[0076] 212: first conductive feature

[0077] 215: first device

[0078] 220: power delivery layer

[0079] 221: dielectric layer

[0080] 222: conductive feature

[0081] 225: first bond pad

[0082] 230: first packaging element (lower)

[0083] 242: carrier substrate

[0084] 243: second through-silica via (upper through-silica via)

[0085] 250: second device layer

[0086] 251: second dielectric layer

[0087] 255: second device

[0088] 260: power delivery layer

[0089] 261: dielectric layer

[0090] 262: conductive feature

[0091] 265: second bonding pad

[0092] 270: second packaging element (upper portion)

[0093] 300: die structure (second logic die)

[0094] 400: die structure

[0095] 401: first substrate

[0096] 403: first through-silicon via (lower through-silicon via)

[0097] 410: first device layer

[0098] 411: first dielectric layer

[0099] 412: first conductive feature

[0100] 415: first device

[0101] 420: first packaging element

[0102] 431: second substrate

[0103] 433: second through-silicon via (upper through-silicon via)

[0104] 440: second device layer

[0105] 441: second dielectric layer

[0106] 442: second conductive feature

[0107] 445: second device

[0108] 450: second packaging element DETAILED DESCRIPTION

[0109] The following disclosure provides many different embodiments, or examples, for implementing different features of the present embodiments. Reference can be made to these various examples in conjunction with the above description of the present embodiments. It should be noted that the various embodiments described herein can be used alone or in combination with one another. Moreover, the following description provides specific examples for the various features of the present embodiments. One skilled in the art will recognize that the specific examples provided herein have been included for the purpose of providing a thorough and complete disclosure of the present embodiments. It should be noted that these specific examples are included for illustrative purposes only and are not intended to limit or otherwise narrow the scope of the present embodiments. For example, although the following description refers to a first feature being formed on or over a second feature, this can include embodiments where the first and second features are in direct contact, as well as embodiments where additional features are formed between the first and second features such that the first and second features can not be in direct contact.

[0110] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0111] Embodiments of the present application provide a package structure and a die structure. The package structure includes a die structure having at least one through-silicon via (TSV) and at least one through-silicon via. Thus, power can be transmitted to a device on the opposite side of the die structure, thereby reducing power loss and / or increasing the transmission speed of power.

[0112] Figures 1A-1C Cross-sectional views illustrating various stages of fabricating a die structure 100 according to some embodiments of the present application are shown. For example, a first substrate 101 includes a semiconductor substrate including, for example, doped or undoped silicon, or an active layer of a silicon-on-insulator (SOI) substrate. In some embodiments, the first substrate 101 includes other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP), or combinations of the foregoing. However, the present application is not so limited. Other substrates, such as a multilayer substrate or a graded substrate, can also be used. In some embodiments, the first substrate 101 has an upper surface 101 A and a lower surface 101 B, where the lower surface 101 B is opposite the upper surface 101 A.

[0113] In some embodiments, a first device layer 110 can be formed over the first substrate 101. For example, the first device layer 110 can be formed over the upper surface 101 A of the first substrate 101. In some embodiments, the first device layer 110 includes a plurality of first dielectric layers 111 and a plurality of first conductive features 112, and the first conductive features 112 are embedded in the first dielectric layers 111. It should be noted that the first dielectric layers 111 are shown as single layers for simplicity, and the present application is not so limited. In addition, the first device layer 110 also includes a plurality of first devices 115 disposed over the upper surface 101 A of the first substrate 101. In some embodiments, the first devices 115 are surrounded by the first dielectric layers 111 and in contact with the first substrate 101 (e.g., the upper surface 101 A).

[0114] For example, the first dielectric layer 111 includes a dielectric material such as Si02, SiN, SiCN, SiOC, SiOCN, etc. However, the present application is not so limited. In some other embodiments, the first dielectric layer 111 includes a polymer such as polybenzoxazoles (PBO), polyimide (PI), benzocyclobutene (BCB), etc. The first dielectric layer 111 can be formed, for example, by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. Other insulating materials formed by any acceptable process can also be used. In some embodiments, the first conductive features 112 can include a conductive material. The conductive material can include a metal such as copper, aluminum, nickel, titanium, combinations of the foregoing, or other suitable metals.

[0115] In some embodiments, the first device 115 includes a semiconductor device such as a fin field-effect transistor (FinFET). However, various embodiments can be applied to dies including other types of transistors such as nanostructure FETs, complementary field-effect transistors (CFETs), thin film transistors (TFTs), planar transistors, etc. in place of or in combination with FinFETs. It should be noted that the present application is not so limited. Any possible semiconductor device is included within the scope of the present application.

[0116] Next, as Figure 1BAs shown, a first through-silicon via (TSV) 103 is formed in the first substrate 101. The first through-silicon via 103 is electrically connected to a first conductive feature 112 in the first device layer 110, such that the first through-silicon via 103 can extend into the first device layer 110 and be in physical contact with the first conductive element 112. In some embodiments, the first substrate 101 and the first device layer 110 can be flipped to form the first through-silicon via 103. For example, a patterned photoresist layer (not shown) is formed over the lower surface 101B of the first substrate 101. The patterned photoresist layer can be formed by a deposition process and a patterning process. The deposition process for forming the patterned photoresist layer can include a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process, or other suitable processes. The patterning process for forming the patterned photoresist layer can include a photolithography process and an etching process. The photolithography process can include photoresist coating (e.g., spin-on), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinse, and dry (e.g., hard bake). The etching process can include a dry etching process or a wet etching process.

[0117] In some embodiments, the first substrate 101 is etched to form a first opening (not shown separately) that penetrates the first substrate 101 by the patterned photoresist layer. The first opening can partially expose the first conductive feature 112, which means that the first opening can extend into the first device layer 110 (e.g., through the first dielectric layer 111). However, the present disclosure is not limited thereto. Next, a first conductive material is filled into the first opening to form the first through-silicon via 103. The first conductive material can include a metal, such as copper, aluminum, nickel, titanium, a combination of the foregoing, or other suitable metals. Other suitable materials are also within the scope of the present disclosure. In this way, the first package element 120 is formed.

[0118] Although an example process for forming the first through-silicon via 103 is described, the present disclosure is not limited thereto. In some other embodiments, the first through-silicon via 103 can be formed in the first substrate 101 before the first device layer 110 is formed over the first substrate 101. Thus, in embodiments where the first through-silicon via 103 is formed before the first device layer 110, the first conductive feature 112 can be formed on the upper surface 101A of the first substrate 101 and in physical contact with the first through-silicon via 103.

[0119] Next, as shown in FIG. 1C, a second device layer 130 is formed over the first substrate 101. The second device layer 130 can include a second dielectric layer 131 and a second conductive element 132. The second conductive element 132 can be formed on the upper surface 101A of the first substrate 101 and in physical contact with the first through-silicon via 103. The second conductive element 132 can be formed by a deposition process and a patterning process. The deposition process for forming the second conductive element 132 can include a CVD process, a HDPCVD process, a spin-on process, a sputtering process, or other suitable processes. The patterning process for forming the second conductive element 132 can include a photolithography process and an etching process. The photolithography process can include photoresist coating (e.g., spin-on), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinse, and dry (e.g., hard bake). The etching process can include a dry etching process or a wet etching process. Figure 1CAs shown, the first packaging element 120 is bonded to the second packaging element 150 to form a die structure 100, such as a logic die. In some embodiments, the second packaging element 150 is formed using the same process and materials as the first packaging element 120. For example, the second packaging element 150 includes a second substrate 131 and a second device layer 140 positioned above the second substrate 131.

[0120] In some embodiments, the second device layer 140 includes a plurality of second dielectric layers 141 and a plurality of second conductive features 142, and the second conductive features 142 are embedded in the second dielectric layers 141. It should be noted that the second dielectric layers 141 are shown as single layers for simplicity, but the present disclosure is not limited thereto. In addition, the second device layer 140 further includes a plurality of second devices 145 disposed above the second substrate 131. In some embodiments, the second devices 145 are surrounded by the second dielectric layers 141 and in contact with the second substrate 131. However, the present disclosure is not limited thereto.

[0121] In some embodiments, a second through-silica via (TSV) 133 is formed in the second substrate 131. The second TSV 133 is electrically connected to the second conductive features 142 in the second device layer 140, and thus the second TSV 133 can extend to the second device layer 140 and be in physical contact with the second conductive features 142. In some embodiments, the second TSV 133 is formed using the same method and materials as the first TSV 103, but the present disclosure is not limited thereto.

[0122] In some embodiments, the first packaging element 120 and the second packaging element 150 are bonded via dielectric-to-dielectric bonding and metal-to-metal direct bonding. More specifically, a plurality of first bonding pads 117 are formed in the first device layer 110 and exposed to the first dielectric layer 111. In some embodiments, the first bonding pads 117 are electrically connected to the first conductive features 112. However, the present disclosure is not limited thereto. For example, the first bonding pads 117 include a conductive material, such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing.

[0123] Similarly, a plurality of second bonding pads 147 are formed in the second device layer 140 and exposed to the second dielectric layer 141. In some embodiments, the second bonding pads 147 are electrically connected to the second conductive features 142. However, the present application is not limited thereto. For example, the second bonding pads 147 comprise a conductive material, such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing. In some embodiments, each of the first bonding pads 117 of the first device layer 110 is aligned with one of the second bonding pads 147 of the second device layer 140, referred to as a metal-to-metal direct bonding. The outermost first dielectric layer 111 is bonded to the outermost second dielectric layer 141, referred to as a dielectric-to-dielectric bonding.

[0124] It should be noted that, for clarity, the first package element 120 can be referred to as a lower portion 120 of the die structure 100, and the first through-silicon via 103 can be referred to as a lower through-silicon via 103. Similarly, the second package element 150 can be referred to as an upper portion 150 of the die structure 100, and the second through-silicon via 133 can be referred to as an upper through-silicon via 133.

[0125] Figures 2A-2E Cross-sectional views showing various stages of fabricating a die structure 200 according to some embodiments of the present application are shown. For example, the first substrate 201 comprises a semiconductor substrate, including, for example, doped or undoped silicon, or an active layer of a silicon-on-insulator (SOI) substrate. In some embodiments, the first substrate 201 comprises other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP), or a combination of the foregoing. However, the present application is not limited thereto. Other substrates can also be used, such as a multilayer substrate or a graded substrate. In some embodiments, the first substrate 201 has an upper surface 201 A and a lower surface 201 B. The lower surface 201 B is opposite the upper surface 201 A.

[0126] In some embodiments, a first device layer 210 may be formed over a first substrate 201. For example, the first device layer 210 is formed over the upper surface 201A of the first substrate 201. In some embodiments, the first device layer 210 includes a plurality of first dielectric layers 211 and a plurality of first conductive features 212, and the first conductive features 212 are embedded in the first dielectric layers 211. It should be noted that, for the sake of simplicity, the first dielectric layer 211 is shown as a single layer, but the present invention is not limited thereto. In addition, the first device layer 210 also includes a plurality of first devices 215 disposed over the upper surface 201A of the first substrate 201. In some embodiments, the first devices 215 are surrounded by the first dielectric layers 211 and are in contact with the first substrate 201 (e.g., the upper surface 201A).

[0127] For example, the first dielectric layer 211 comprises a dielectric material such as SiO2, SiN, SiCN, SiOC, SiOCN, etc. However, the present invention is not limited thereto. In some other embodiments, the first dielectric layer 211 comprises polymers such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc. The first dielectric layer 211 can be formed, for example, by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. Other insulating materials formed by any acceptable process can also be used. In some embodiments, the first conductive feature 212 may comprise a conductive material. The conductive material may comprise a metal, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals.

[0128] In some embodiments, the first device 215 includes, for example, a semiconductor element comprising a FinFET. However, various embodiments may employ other types of transistors (e.g., nanostructure FETs, complementary field-effect transistors (CFETs), thin-film transistors (TFTs), planar transistors, etc.) instead of a FinFET or a die combined with a FinFET. It should be noted that the present invention is not limited thereto. Any possible semiconductor device is included within the scope of this invention.

[0129] Next, as Figure 2B As shown, the carrier substrate 202 is bonded to the first device layer 210. In some embodiments, the first device layer 210 is located between the first substrate 201 and the carrier substrate 202 at this stage. For example, the carrier substrate 202 may be a wafer (e.g., a silicon wafer), but the present invention is not limited thereto. The carrier substrate 202 may provide structural support during subsequent process steps and in the completed structure.

[0130] Subsequently, as Figure 2CAs shown, the first substrate 201 is removed, and a power transmission layer 220 is formed on the first device layer 210. In some embodiments, the first device layer 210 is located between the power transmission layer 220 and the carrier substrate 202 at this stage. In some embodiments, the power transmission layer 220 is connected to an external power source and supplies power to the first device layer 210. In some embodiments, the power transmission layer 220 includes a plurality of dielectric layers 221 and a plurality of conductive features 222, the conductive features 222 being embedded in the dielectric layers 221. It should be noted that, for simplicity, the dielectric layer 221 is shown as a single layer, but the present invention is not limited thereto.

[0131] For example, dielectric layer 221 includes dielectric materials such as SiO2, SiN, SiCN, SiOC, SiOCN, etc. However, the present invention is not limited thereto. In some other embodiments, dielectric layer 221 includes polymers such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc. Dielectric layer 221 can be formed, for example, by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. Other insulating materials formed by any acceptable process can also be used. In some embodiments, conductive feature 222 may include a conductive material. The conductive material may include metals such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals.

[0132] Next, as Figure 2D As shown, a first through-silicon via (TSV) 203 is formed through the carrier substrate 202 and the first device layer 210. The first TSV 203 is electrically connected to a conductive feature 222 in the power transmission layer 220, thus the first TSV 203 can extend into the power transmission layer 220 and physically contact the conductive feature 222. For example, a patterned photoresist layer (not shown) is formed over the carrier substrate 202. The patterned photoresist layer can be formed by a deposition process and a patterning process. The deposition process for forming the patterned photoresist layer can include chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), spin coating, sputtering, or other suitable processes. The patterning process for forming the patterned photoresist layer can include a photolithography process and an etching process. The photolithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process can include a dry etching process or a wet etching process.

[0133] In some embodiments, the carrier substrate 202 is etched to form a first opening (not shown separately) through which a patterned photoresist layer penetrates the carrier substrate 202 and the first device layer 210. The first opening may partially expose conductive features 222, meaning the first opening may extend into the power transmission layer 220 (e.g., through the dielectric layer 221). However, the invention is not limited thereto. Next, a first conductive material is filled into the first opening to form a first through-silicon via 203. The first conductive material may include a metal, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. Other suitable materials are also within the scope of this invention. In this way, a first package element 230 is formed.

[0134] Next, as Figure 2E As shown, a first package element 230 is bonded to a second package element 270 to form a die structure 200, such as a logic die. In some embodiments, the second package element 270 is formed using the same processes and materials as the first package element 230. For example, the second package element 270 includes a carrier substrate 242, a second device layer 250 above the carrier substrate 242, and a power transport layer 260 above the second device layer 250. In some embodiments, the second device layer 250 includes a plurality of second dielectric layers 251 and a plurality of second conductive features, wherein the second conductive features are embedded in the second dielectric layers 251. It should be noted that, for simplicity, the second dielectric layer 251 is shown as a single layer, but the invention is not limited thereto. In addition, the second device layer 250 also includes a plurality of second devices 255 surrounded by the second dielectric layer 251 and in contact with the power transport layer 260. However, the invention is not limited thereto. In some embodiments, the power transport layer 260 is connected to an external power source and supplies power to the second device layer 250.

[0135] In some embodiments, the first package element 230 and the second package element 270 are joined via dielectric-to-dielectric bonding and metal-to-metal direct bonding of the power transmission layers 220 and 260. More specifically, a plurality of first bonding pads 225 are formed in the power transmission layer 220 and exposed to the dielectric layer 221. In some embodiments, the first bonding pads 225 are electrically connected to the conductive feature 222. However, the present invention is not limited thereto. For example, the first bonding pads 225 comprise conductive materials such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or combinations thereof.

[0136] Similarly, a plurality of second bonding pads 265 are formed in the power delivery layer 260 and exposed to the dielectric layer 261. In some embodiments, the second bonding pads 265 are electrically connected to the conductive features 262. However, the present disclosure is not limited thereto. For example, the second bonding pads 265 comprise a conductive material, such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing. In some embodiments, each of the first bonding pads 225 is aligned with one of the second bonding pads 265, referred to as a metal-to-metal direct bond. The outermost dielectric layer 221 is bonded to the outermost dielectric layer 261, referred to as a dielectric-to-dielectric bond.

[0137] It should be noted that, for clarity, the first package element 230 can be referred to as a lower portion 230 of the die structure 200, and the first through-silicon via 203 can be referred to as a lower through-silicon via 203. Similarly, the second package element 270 can be referred to as an upper portion 270 of the die structure 200, and the second through-silicon via 243 can be referred to as an upper through-silicon via 243.

[0138] Although the die structure 100 and the die structure 200 are described above, the present disclosure is not limited thereto. It should be noted that any two of the first package elements 120, 230 and the second package elements 150, 270 can be combined to form a die structure, and such configurations are included within the scope of the present disclosure. Furthermore, the package elements 120, 150, 230, and 270 are merely examples, and any package elements having one or more through-silicon vias are considered within the scope of the present disclosure, as long as the resulting die structure has at least one upper through-silicon via and at least one lower through-silicon via.

[0139] With the configuration of the upper through-silicon vias (e.g., the second through-silicon via 133) and the lower through-silicon vias (e.g., the first through-silicon via 103), power can be delivered more quickly to devices (e.g., the first device 115 and the second device 145) in the die structure (e.g., the die structure 100). More specifically, power can be delivered to devices on opposite sides of the die structure (e.g., as indicated by the arrows in FIG. 1), thereby reducing power loss and / or increasing power delivery speed. For example, power can be delivered through a conductive via that is wider than the through-silicon vias in the die structure, which can significantly reduce power loss due to the lower resistance value of the conductive via compared to the resistance value of the conductive features in the die structure. Figure 1C and / or Figure 2E With the configuration of the upper through-silicon vias (e.g., the second through-silicon via 133) and the lower through-silicon vias (e.g., the first through-silicon via 103), power can be delivered more quickly to devices (e.g., the first device 115 and the second device 145) in the die structure (e.g., the die structure 100). More specifically, power can be delivered to devices on opposite sides of the die structure (e.g., as indicated by the arrows in FIG. 1), thereby reducing power loss and / or increasing power delivery speed. For example, power can be delivered through a conductive via that is wider than the through-silicon vias in the die structure, which can significantly reduce power loss due to the lower resistance value of the conductive via compared to the resistance value of the conductive features in the die structure.

[0140] Figures 3A-3E Cross-sectional views showing various stages of fabricating a package structure 10 according to some embodiments of the present disclosure are shown. As shown in FIG. 2A, a substrate 210 is provided. The substrate 210 can comprise any suitable material, such as silicon, germanium, gallium arsenide, or any other suitable material. In some embodiments, the substrate 210 comprises a semiconductor material, such as silicon or germanium. In some embodiments, the substrate 210 comprises a compound semiconductor material, such as gallium arsenide. In some embodiments, the substrate 210 comprises a combination of a semiconductor material and a compound semiconductor material. In some embodiments, the substrate 210 comprises a combination of a semiconductor material and a compound semiconductor material, such as a combination of silicon and gallium arsenide. Figure 3AAs shown, a carrier substrate 12 is provided, and the die structure 100 can be disposed above the carrier substrate 12. For example, the carrier substrate 12 can be a wafer (e.g., a silicon wafer), although the present disclosure is not so limited. The carrier substrate 12 can provide structural support for the die structure 100.

[0141] In some embodiments, the electrically conductive substrate 20 is bonded to the die structure 100. The electrically conductive substrate 20 includes a plurality of dielectric layers 21 and a plurality of electrically conductive features 22, and the electrically conductive features 22 are embedded in the dielectric layers 21. It should be noted that the dielectric layers 21 are shown as a single layer for simplicity, although the present disclosure is not so limited. For example, the dielectric layers 21 include a dielectric material, such as SiO2, SiN, SiCN, SiOC, SiOCN, or the like. However, the present disclosure is not so limited. In some other embodiments, the dielectric layers 21 include a polymer, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or the like. The dielectric layers 21 can be formed, for example, by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. Other insulating materials formed by any acceptable process can also be used. In some embodiments, the electrically conductive features 22 can include an electrically conductive material. The electrically conductive material can include a metal, such as copper, aluminum, nickel, titanium, combinations of the foregoing, or other suitable metals. In some embodiments, the electrically conductive features 22 are electrically connected to the die structure 100 via, for example, the second through-silicon via 133.

[0142] Additionally, as Figure 3AAs shown, an under-bump metallization (UBM) structure 25 is formed in the dielectric layer 21 of the conductive substrate 20 and electrically connected to the conductive feature 22. The UBM structure 25 may comprise multiple layers of copper, nickel, gold, or other similar materials formed by electroplating processes, etc. A bump structure 26 is formed on the UBM structure 25. In some embodiments, the bump structure 26 may be a conductive ball structure (e.g., a ball grid array (BGA)), a conductive pillar structure, or a conductive paste structure, mounted on the conductive substrate 20 and the die structure 100 in a bonding process and electrically coupled to the conductive substrate 20 and the die structure 100. The formation of the bump structure 26 may include placing solder balls on the exposed portion of the UBM structure 25 and reflowing the solder balls. In some embodiments, the formation of the bump structure 26 includes performing an electroplating step to form a solder region over the UBM structure 25, followed by reflowing the solder region. The under-bump metal structure 25 and the bump structure 26 can be used to provide input / output connections to other electronic components (e.g., other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc.). The under-bump metal structure 25 and the bump structure 26 can provide signal, supply voltage, and / or ground connections to the first device 115 and the second device 145 in the die structure 100.

[0143] Next, as Figure 3B As shown, the interconnect structure 30 is bonded to the conductive substrate 20. For example, the interconnect structure 30 may be an interlayer and include an inorganic interlayer material, such as a silicon-based dielectric material (e.g., silicon oxide), porous or non-porous organosilicon glass, silicon carbonitride, silicon nitride, or any other inorganic interconnect-level dielectric material. However, the present invention is not limited thereto.

[0144] The interconnect structure 30 includes a plurality of dielectric layers 31 and a plurality of conductive features 32, with the conductive features 32 embedded in the dielectric layers 31. It should be noted that, for simplicity, the dielectric layer 31 is shown as a single layer, but the invention is not limited thereto. For example, the dielectric layer 31 includes dielectric materials such as SiO2, SiN, SiCN, SiOC, SiOCN, etc. However, the invention is not limited thereto. In some other embodiments, the dielectric layer 31 includes polymers such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc. The dielectric layer 31 can be formed, for example, by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. Other insulating materials formed by any acceptable process can also be used. In some embodiments, the conductive features 32 may include conductive materials. Conductive materials may include metals such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. In some embodiments, the conductive feature 32 is electrically connected to the die structure 100 via, for example, a bump structure 26.

[0145] Furthermore, an under-bump metallization (UBM) structure 33 is formed in the dielectric layer 31 of the interconnect structure 30 and electrically connected to the conductive feature 32. The UBM structure 33 may comprise multiple layers of copper, nickel, gold, or other similar materials formed by electroplating processes or the like. A bump structure 26 is bonded to the UBM structure 33. Therefore, the interconnect structure 30 can be bonded to the conductive substrate 20 via the bump structure 26.

[0146] Next, as Figure 3C As shown, a molding compound 40 can be formed on the interconnect structure 30 and around the conductive substrate 20 and the die structure 100. In some embodiments, the molding compound 40 can encapsulate the die structure 100 and the conductive substrate 20 on the interconnect structure 30 in a horizontal direction (e.g., X / Y direction) (i.e., covering the die structure 100 and the conductive substrate 20). For example, the molding compound 40 may include an epoxy polymer material (e.g., epoxy molding compound (EMC)). The molding compound 40 can be formed by deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques. However, the present invention is not limited thereto.

[0147] For example, a planarization process can be performed on the upper surface 40A of the mold encapsulation material 40 until the upper surface 40A exposes the top surface of the die structure 100 (e.g., the through-silicon via of the die structure 100). In some embodiments, the upper surface 40A of the mold encapsulation material 40 is substantially flush with the top surface of the die structure 100. The planarization process can include, for example, a mechanical grinding process and / or a chemical mechanical polish (CMP) process.

[0148] In addition, at least one (e.g., two as shown in the present embodiment) conductive via 43 is formed through the mold encapsulation material 40. The conductive via 43 is electrically connected to the interconnect structure 30 and laterally separated from the die structure 100. In some embodiments, the die structure 100 can be sandwiched between adjacent conductive vias 43. In some embodiments, the conductive via 43 can include a metal, such as copper, aluminum, nickel, titanium, a combination of the foregoing, or other suitable metal. Other suitable materials are also contemplated within the scope of the present disclosure. In some embodiments, the conductive via 43 can be formed by the same material and the same method as the first through-silicon via 103 or the second through-silicon via 133. However, the present disclosure is not limited thereto. In some embodiments, the conductive via 43 is formed by using a different material or method from the first through-silicon via 103 or the second through-silicon via 133. In some embodiments, the height of the first through-silicon via 103 or the second through-silicon via 133 is different from the height of the conductive via 43 in the vertical direction (e.g., the Z direction).

[0149] Next, as shown in FIG. 1C, a first dielectric layer 50 is formed on the upper surface 40A of the mold encapsulation material 40. The first dielectric layer 50 can include, for example, a polymer material, such as a polyimide material. In some embodiments, the first dielectric layer 50 can include a material that is different from the material of the mold encapsulation material 40. In some embodiments, the first dielectric layer 50 can include a material that is the same as the material of the mold encapsulation material 40. Figure 3DAs shown, a redistribution layer 50 is disposed over the mold encapsulation material 40 and the die structure 100. In some embodiments, the redistribution layer 50 includes a plurality of dielectric layers 51 and a plurality of conductive features 52, and the conductive features 52 are embedded in the dielectric layers 51. It should be noted that the dielectric layers 51 are shown as a single layer for simplicity, and the present disclosure is not limited thereto. For example, the dielectric layers 51 include a dielectric material, such as Si02, SiN, SiCN, SiOC, SiOCN, etc. However, the present disclosure is not limited thereto. In some other embodiments, the dielectric layers 51 include a polymer, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc. The dielectric layers 51 can be formed, for example, by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. Other insulating materials formed by any acceptable process can also be used. In some embodiments, the conductive features 52 can include a conductive material. The conductive material can include a metal, such as copper, aluminum, nickel, titanium, combinations of the foregoing, or other suitable metals. In some embodiments, the conductive features 52 are electrically connected to the die structure 100 and the conductive vias 43, and thus power can be supplied to devices (e.g., the first device 115 and / or the second device 145) in the die structure 100 via the conductive vias 43 and the conductive features 52.

[0150] In addition, an under bump metal (UBM) structure 55 is formed in the dielectric layers 51 of the redistribution layer 50 and is electrically connected to the conductive features 52. The under bump metal structure 55 can include multiple layers of copper, nickel, gold, or other similar materials formed by an electroplating process or the like. A bump structure 56 is formed on the under bump metal structure 55. In some embodiments, the bump structure 56 can be a conductive ball structure (e.g., a ball grid array (BGA), a conductive pillar structure, or a conductive paste structure) that is mounted on and electrically coupled to the redistribution layer 50. The formation of the bump structure 56 can include placing solder balls on exposed portions of the under bump metal structure 55 and reflowing the solder balls. In some embodiments, the formation of the bump structure 56 includes performing an electroplating step to form a solder region over the under bump metal structure 55, followed by reflowing the solder region. The under bump metal structure 55 and the bump structure 56 can be used to provide input / output connections to other electronic components (e.g., other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc.). The under bump metal structure 55 and the bump structure 56 can provide signal, supply voltage, and / or ground connections to the first device 115 and the second device 145 in the die structure 100.

[0151] Next, as shown in FIG. 2, a redistribution layer 50 is formed over the die structure 100 and the mold encapsulation material 40. In some embodiments, the redistribution layer 50 includes a plurality of dielectric layers 51 and a plurality of conductive features 52, and the conductive features 52 are embedded in the dielectric layers 51. It should be noted that the dielectric layers 51 are shown as a single layer for simplicity, and the present disclosure is not limited thereto. For example, the dielectric layers 51 include a dielectric material, such as Si02, SiN, SiCN, SiOC, SiOCN, etc. However, the present disclosure is not limited thereto. In some other embodiments, the dielectric layers 51 include a polymer, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc. The dielectric layers 51 can be formed, for example, by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. Other insulating materials formed by any acceptable process can also be used. In some embodiments, the conductive features 52 can include a conductive material. The conductive material can include a metal, such as copper, aluminum, nickel, titanium, combinations of the foregoing, or other suitable metals. In some embodiments, the conductive features 52 are electrically connected to the die structure 100 and the conductive vias 43, and thus power can be supplied to devices (e.g., the first device 115 and / or the second device 145) in the die structure 100 via the conductive vias 43 and the conductive features 52. Figure 3EAs shown, a plurality of device elements 60 are disposed above the redistribution layer 50 and are electrically connected to the redistribution layer 50 by, for example, bump structures 56. By way of example, the device elements 60 can be device dies, have packages with element dies encapsulated therein, system-on-chip (SoC) dies including multiple element dies packaged as a system, or the like. The device elements 60 can be or include logic dies, memory dies, input / output dies, integrateed passive devices (IPDs), or the like, or combinations of the foregoing. By way of example, logic device dies in the device elements 60 can be central processing unit (CPU) dies, graphic processing unit (GPU) dies, mobile application dies, micro control unit (MCU) dies, baseband (BB) dies, application processor (AP) dies, or the like. Memory dies in the device elements 60 can include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, or the like. The device elements 60 can include semiconductor substrates and interconnect structures, which are not separately shown in the present embodiment. In some embodiments, the die structure 100 can control operations of the device elements 60, and thus the die structure 100 can also be referred to as a “logic die 100”.

[0152] In some embodiments, a mold encapsulation material 70 can be formed above the redistribution layer 50 and around the device elements 60. In some embodiments, the mold encapsulation material 70 can encapsulate (i.e., cover) the device elements 60 in a horizontal direction (e.g., X / Y direction). By way of example, the mold encapsulation material 70 can include an epoxy polymer material (e.g., an epoxy mold compound (EMC)). The mold encapsulation material 70 can be formed by, for example, a chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD), a physical vapor deposition (PVD), a spin coating, a lamination, or other suitable deposition techniques. However, the present disclosure is not limited thereto.

[0153] By way of example, a planarization process can be performed on the upper surface of the mold encapsulation material 70 until the top surface of the device element 60 is exposed. In some embodiments, the upper surface of the mold encapsulation material 70 is substantially flush with the top surface of the device element 60. The planarization process can include, for example, a mechanical polishing process and / or a chemical mechanical polishing (CMP) process. However, the present application is not limited thereto. In some other embodiments, the planarization process can be omitted, and thus the top surface of the device element 60 can be covered by the mold encapsulation material 70.

[0154] Furthermore, a package substrate 80 is bonded to the interconnect structure 30. In some embodiments, the package substrate 80 is made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, a compound material such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, a combination of the foregoing, etc. can also be used. In addition, in some embodiments, the package substrate 80 includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, silicon on insulator (SOI), silicon germanium on insulator (SGOI), or a combination of the foregoing. In an alternative embodiment, the package substrate 80 is based on an insulating core such as a fiberglass reinforced resin core. One example of a core material is fiberglass resin. Alternatives to the core material include bismaleimide triazine (BT) resin, or other printed circuit board (PCB) materials or thin films. Build-up film or other laminated materials can also be used for the package substrate 80.

[0155] In some embodiments, the package substrate 80 includes a bump structure 85. In some embodiments, the bump structure 85 can be a conductive ball structure (e.g., a ball grid array (BGA)), a conductive pillar structure, or a conductive paste structure that is mounted on and electrically coupled to the package substrate 80 in a bonding process. Thus, the package structure 10 is formed. It should be noted that the package structure 10 of the present embodiment is merely by way of example, and one skilled in the art to which the present application pertains should be able to add other elements to the present application to achieve the desired functionality.

[0156] Figure 4 A cross-sectional view of a package structure 10A according to some embodiments of the present application is shown. It should be noted that the package structure 10A of the present embodiment includes the same or similar elements as the package structure 10 shown Figure 3E For the sake of clarity and simplicity, these elements will be denoted using the same reference numerals, and will not be described in detail. As shown in FIG. 1 A, the package structure 10A includes a device element 60, a mold encapsulation material 70, and a package substrate 80. The device element 60 can be a semiconductor device such as a transistor, a diode, a capacitor, an inductor, a resistor, a memory device, a logic device, a combination of the foregoing, etc. The device element 60 can be formed on a substrate 65 such as a silicon wafer, a silicon on insulator (SOI) wafer, a silicon germanium on insulator (SGOI) wafer, a gallium arsenide wafer, a gallium indium phosphide wafer, a combination of the foregoing, etc. The device element 60 can be formed by a variety of processes such as a deposition process, an etching process, a photolithography process, a combination of the foregoing, etc. Figure 4As shown, the package structure 10A further includes a die structure 300 disposed adjacent to the die structure 100, with the first logic die 100 sandwiched between the second logic die 300 and the conductive via 43. To further distinguish the die structure 100 and the die structure 300, the die structure 100 can be referred to as the "first logic die 100", and the die structure 300 can be referred to as the "second logic die 300". In some embodiments, the second logic die 300 includes a plurality of through-silicon vias, and the through-silicon vias of the second logic die 300 can partially overlap with the through-silicon vias of the second logic die 300. However, the utility model is not limited thereto. In some embodiments, the second logic die 300 can be identical to the first logic die 100.

[0157] Figure 5A A top view of a die structure 400 according to some embodiments of the utility model is shown. Figure 5B A cross-sectional view of the die structure 400 according to some embodiments of the utility model is shown. It should be noted that the die structure 400 shown in the present embodiment includes the same or similar elements as the die structure 100 shown in the above embodiments. For the sake of clarity and simplicity, these elements will be denoted using the same reference numerals, and will not be described in detail again. As shown in the present embodiment, the die structure 400 includes a first device layer 410, a first dielectric layer 411, a first conductive feature 412, a first substrate 401, a first through-silicon via 403, a first dielectric layer 411, a first conductive feature 412, a second dielectric layer 431, a second conductive feature 432, a second substrate 431, a second through-silicon via 433, a second dielectric layer 431, a second conductive feature 432, a third dielectric layer 441, a third conductive feature 442, a third substrate 441, a third through-silicon via 443, a third dielectric layer 441, a third conductive feature 442, a fourth dielectric layer 451, a fourth conductive feature 452, a fourth substrate 451, a fourth through-silicon via 453, a fourth dielectric layer 451, and a fourth conductive feature 452. Figure 1C The die structure 100 shown in the present embodiment includes the same or similar elements as the die structure 100 shown in the above embodiments. For the sake of clarity and simplicity, these elements will be denoted using the same reference numerals, and will not be described in detail again. As shown in the present embodiment, the die structure 100 includes a first device layer 410, a first dielectric layer 411, a first conductive feature 412, a first substrate 401, a first through-silicon via 403, a first dielectric layer 411, a first conductive feature 412, a second dielectric layer 431, a second conductive feature 432, a second substrate 431, a second through-silicon via 433, a second dielectric layer 431, and a second conductive feature 432. Figure 5A and Figure 5B As shown, the die structure 400 is formed by joining the first package element 420 and the second package element 450. In some embodiments, the first through-silicon via 403 in the first package element 420 (e.g. the first substrate 401) does not overlap with the second through-silicon via 433 in the second package element 450. That is, the first through-silicon via 403 is offset from the projection area of the second through-silicon via 433 on the second substrate 431. However, the utility model is not limited thereto.

[0158] In some embodiments, the first device 415 in the first device layer 410 (including the first dielectric layer 411 and the first conductive feature 412) is separated from one of the first through-silicon vias 403 (i.e. the lower through-silicon vias) in the vertical direction (e.g. the Z direction). In this way, the overall layout design of the die structure 400 can be simplified, thereby reducing the manufacturing cost of the die structure 400. In some embodiments, the first devices 415 in the first device layer 410 respectively overlap with one of the first through-silicon vias 403 (i.e. the lower through-silicon vias) in the vertical direction. In this way, the space required by the die structure 400 can be reduced, thereby miniaturizing the lateral dimension of the die structure 400.

[0159] Similarly, a second device 445 in a second device layer 440 (including a second dielectric layer 441 and a second conductive feature 442) is separated from one of the second through-silicon vias 433 (i.e., upper through-silicon vias) in a vertical direction (e.g., Z-direction). In this way, the design of the overall layout of the die structure 400 can be simplified, thereby reducing the manufacturing cost of the die structure 400. In some embodiments, the second device 445 in the second device layer 440 respectively overlaps one of the second through-silicon vias 433 (i.e., upper through-silicon vias) in a vertical direction. In this way, the space required by the die structure 400 can be reduced, thereby miniaturizing the lateral dimension of the die structure 400.

[0160] It should be noted that although the present embodiments show a plurality of first through-silicon vias 403 and a plurality of second through-silicon vias 433, the present disclosure is not limited thereto. The number and position of the first through-silicon vias 403 and the second through-silicon vias 433 can be adjusted based on the present disclosure, as long as the die structure 400 includes at least one first through-silicon via 403 and at least one second through-silicon via 433.

[0161] Figures 6A-6F are cross-sectional views showing various stages of fabricating a package structure 10B according to some embodiments of the present disclosure. As shown in Figure 6A A first carrier substrate 12 is provided, and the die structure 100 can be disposed above the first carrier substrate 12. For example, the first carrier substrate 12 can be a wafer (e.g., a silicon wafer), although the present disclosure is not limited thereto. The carrier substrate 12 can provide structural support for the die structure 100.

[0162] In some embodiments, a conductive substrate 20 is bonded to the die structure 100. The conductive substrate 20 includes a plurality of dielectric layers 21 and a plurality of conductive features 22, and the conductive features 22 are embedded in the dielectric layers 21. It should be noted that the dielectric layers 21 are shown as a single layer for simplicity, although the present disclosure is not limited thereto. In some embodiments, the conductive features 22 can include a conductive material. The conductive material can include a metal, such as copper, aluminum, nickel, titanium, a combination of the foregoing, or other suitable metals. In some embodiments, the conductive features 22 are electrically connected to the die structure 100.

[0163] Next, as shown in Figure 6BAs shown, a second carrier substrate 14 is provided, and a conductive substrate 20 can be supported above the second carrier substrate 14. In some embodiments, the conductive substrate 20 and the die structure 100 are flipped over and placed on the second carrier substrate 14, but the present invention is not limited thereto. Any suitable process is included within the scope of the present invention, as long as the conductive substrate 20 faces the second carrier substrate 14 and is supported by the second carrier substrate 14. For example, the second carrier substrate 14 may be a wafer (e.g., a silicon wafer), but the present invention is not limited thereto.

[0164] Next, as Figure 6C As shown, a molding compound 40 can be formed on the second carrier substrate 14 and around the conductive substrate 20 and the die structure 100. In some embodiments, the molding compound 40 can encapsulate the die structure 100 and the conductive substrate 20 in a horizontal direction (e.g., X / Y direction) (i.e., cover the die structure 100 and the conductive substrate 20). For example, the molding compound 40 may include an epoxy polymer material (e.g., epoxy molding compound (EMC)). The molding compound 40 can be formed by deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques. However, the present invention is not limited thereto.

[0165] Next, as Figure 6D As shown, a conductive via 43 is formed through the molding material 40, and a redistribution layer 50 is disposed above the molding material 40 and the die structure 100. The conductive via 43 is electrically connected to the redistribution layer 50 and is laterally spaced from the die structure 100. In some embodiments, the conductive via 43 may comprise a metal, such as copper, aluminum, nickel, titanium, a combination thereof, or other suitable metals. Other suitable materials are also within the scope of this invention.

[0166] In some embodiments, the redistribution layer 50 includes a plurality of dielectric layers 51 and a plurality of conductive features 52, with the conductive features 52 embedded in the dielectric layers 51. It should be noted that, for simplicity, the dielectric layer 51 is shown as a single layer, but the invention is not limited thereto. In some embodiments, the conductive features 52 are electrically connected to the die structure 100 and the conductive via 43, and thus can supply power to devices in the die structure 100 (e.g., first device 115 and / or second device 145) via the conductive via 43 and the conductive features 52.

[0167] Next, as Figure 6EAs shown, a third carrier substrate 16 is provided, and the redistribution layer 50 can be supported on the third carrier substrate 16. Any suitable process is included within the scope of this invention, as long as the redistribution layer 50 faces the third carrier substrate 16 and is supported by the third carrier substrate 16. For example, the third carrier substrate 16 may be a wafer (e.g., a silicon wafer), but this invention is not limited thereto.

[0168] In some embodiments, an under-bump metallization (UBM) structure 25 is formed in the dielectric layer 21 of the conductive substrate 20 and is electrically connected to the conductive feature 22. The UBM structure 25 may comprise multiple layers of copper, nickel, gold, or other similar materials formed by electroplating processes or the like. A bump structure 26 is formed on the UBM structure 25. In some embodiments, the bump structure 26 may be a conductive ball structure (e.g., a ball grid array (BGA)), a conductive pillar structure, or a conductive paste structure, which is mounted on the conductive substrate 20 and the die structure 100 during a bonding process and electrically coupled to the conductive substrate 20 and the die structure 100.

[0169] Next, as Figure 6F As shown, the package substrate 80 is bonded to the bump structure 26. In some embodiments, the package substrate 80 is made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or combinations thereof may be used. Additionally, in some embodiments, the package substrate 80 includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), or combinations thereof. In an alternative embodiment, the package substrate 80 is based on an insulating core, such as a glass fiber reinforced resin core. One exemplary core material is glass fiber resin. Alternatives to the core material include bismaleimide triazine (BT) resin, or other printed circuit board (PCB) materials or films. Additive films or other lamination materials may also be used for the package substrate 80.

[0170] In some embodiments, the package substrate 80 includes a bump structure 85. In some embodiments, the bump structure 85 may be a conductive ball structure (e.g., a ball grid array (BGA)), a conductive pillar structure, or a conductive paste structure, which is mounted on and electrically coupled to the package substrate 80 during the bonding process. Thus, a package structure 10B is formed. It should be noted that the package structure 10B of this embodiment is merely an example, and those skilled in the art should be able to add other elements based on this invention to achieve the desired functionality.

[0171] Embodiments of the present application provide a package structure and a die structure. The package structure includes a die structure having at least one through-silicon via (TSV) and at least one through-silicon via. Thus, power can be transmitted to a device on the opposite side of the die structure, thereby reducing power loss and / or increasing the transmission speed of power. In some embodiments, the device in the die structure is separated from the through-silicon via in a vertical direction, thereby simplifying the design of the overall layout of the die structure, and thereby reducing the manufacturing cost of the die structure. In some embodiments, the devices in the die structure all overlap with one of the through-silicon vias in a vertical direction, thereby reducing the space required by the die structure, and thereby miniaturizing the lateral dimension of the die structure.

[0172] According to some embodiments of the present application, the package structure includes an interconnect structure, a first logic die, a mold material, a conductive via, and a redistribution layer. The interconnect structure is attached to a package substrate. The first logic die is disposed above the interconnect structure. The first logic die includes an upper through-silicon via (TSV) on an upper portion of the first logic die and a lower through-silicon via on a lower portion of the first logic die, and the lower through-silicon via is electrically connected to the interconnect structure. The upper portion of the first logic die includes a device layer and a power transmission layer, and the upper through-silicon via penetrates the device layer and is physically connected to the power transmission layer. The mold material is disposed above the interconnect structure and surrounds the first logic die. The conductive via penetrates the mold material. The redistribution layer is disposed above the first logic die and the mold material. The redistribution layer is electrically connected to the upper through-silicon via of the first logic die and the conductive via.

[0173] In some embodiments, the mold material exposes the upper through-silicon via of the first logic die.

[0174] In some embodiments, the first logic die further includes a first substrate and a second substrate. The lower through-silicon via penetrates the first substrate. The upper through-silicon via penetrates the second substrate.

[0175] In some embodiments, the device in the device layer is separated from the upper through-silicon via in a vertical direction.

[0176] In some embodiments, in a vertical direction, the height of the upper through-silicon via is different from the height of the conductive via.

[0177] In some embodiments, the package structure further includes a second logic die disposed to abut the first logic die and electrically connected to the conductive via.

[0178] In some embodiments, the package structure further includes a device element disposed above the redistribution layer.

[0179] According to some embodiments of the present application, the die structure includes a first package element and a second package element. The first package element includes a first through silicon via in a first substrate, a first device layer above the first substrate, and a first power delivery layer above the first device layer. The first through silicon via extends to the first power delivery layer. The first device layer includes a plurality of first devices, and the first devices are electrically connected to the first through silicon via. The second package element includes a second through silicon via in a second substrate, a second device layer above the second substrate, and a second power delivery layer above the second device layer. The second device layer includes a plurality of second devices, and the second devices are electrically connected to the second through silicon via. The first device layer is bonded to the second device layer through dielectric-to-dielectric bonding and metal-to-metal direct bonding of the first power delivery layer and the second power delivery layer.

[0180] In some embodiments, the first device layer further includes a plurality of first bonding pads, the second device layer further includes a plurality of second bonding pads, and each of the first bonding pads is aligned with one of the second bonding pads of the second device layer.

[0181] In some embodiments, the first device is in contact with the first substrate.

[0182] In some embodiments, the second through silicon via penetrates the second device layer.

[0183] In some embodiments, the first through silicon via is offset from a projected area of the second through silicon via on the second substrate.

[0184] According to some embodiments of the present application, a method of manufacturing a package structure includes forming a first package element, which includes forming a first device layer above a first substrate; forming a power delivery layer above the first device layer; etching the first substrate to form a first opening; and filling the first opening with a first conductive material to form a first through silicon via. The first opening extends to the first substrate, the first device layer, and the power delivery layer. The method also includes forming a second package element, which includes forming a second device layer above a second substrate; etching the second substrate to form a second opening; and filling the second opening with a second conductive material to form a second through silicon via. The method further includes bonding the first package element and the second package element to form a first logic die. The first package element and the second package element are bonded through dielectric-to-dielectric bonding and metal-to-metal direct bonding. The method includes disposing the first logic die above an interconnect structure, and forming a mold encapsulation material above the interconnect structure and around the first logic die. The method also includes forming a first conductive via to penetrate the mold encapsulation material, and forming a redistribution layer above the first logic die and the mold encapsulation material. The redistribution layer is electrically connected to the first through silicon via and the first conductive via of the first logic die.

[0185] In some embodiments, the first device layer includes a plurality of first dielectric layers and a plurality of first conductive features, and the first conductive features are embedded in the first dielectric layers.

[0186] In some embodiments, the mold encapsulation material exposes the first through silicon via of the first logic die from a top surface of the mold encapsulation material, and the top surface of the mold encapsulation material is further from the interconnect structure than a bottom surface of the mold encapsulation material.

[0187] In some embodiments, the method further includes forming a second conductive via through the mold encapsulation material, wherein the first logic die is between the first conductive via and the second conductive via.

[0188] In some embodiments, the method further includes disposing a second logic die over the interconnect structure, wherein the second logic die is surrounded by the mold encapsulation material, and the first logic die is between the second logic die and the first conductive via.

[0189] In some embodiments, the method further includes forming a plurality of bump structures on the redistribution layer, wherein the bump structures are electrically connected to the first conductive via.

[0190] In some embodiments, the method further includes disposing a device die over the bump structures, wherein the device die is electrically connected to the bump structures.

[0191] In some embodiments, the method further includes bonding the interconnect structure to a package substrate after forming the redistribution layer over the first logic die and the mold encapsulation material.

[0192] The above summarizes the features of many embodiments, so that those skilled in the art to which the present application belongs can more easily understand the various embodiments of the present application. Those skilled in the art to which the present application belongs should understand that other processes and structures can be easily designed or changed based on the embodiments of the present application to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art to which the present application belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present application. Various changes, substitutions and variations can be made to the embodiments of the present application without departing from the spirit and scope of the appended claims.

Claims

1. A packaging structure, characterized in that, include: An interconnect structure is attached to a package substrate; A first logic die is disposed above the interconnect structure, wherein the first logic die includes an upper silicon via on an upper part of the first logic die and a lower silicon via on a lower part of the first logic die, and the lower silicon via is electrically connected to the interconnect structure, wherein the upper part of the first logic die includes a device layer and a power transmission layer, and the upper silicon via penetrates the device layer and is physically connected to the power transmission layer; A molded material, surrounding the first logic bare die; A conductive through-hole penetrates the molding material; as well as A redistribution layer is located above the first logic die and the molding material, wherein the redistribution layer is electrically connected to the on-silicon via and the conductive via of the first logic die.

2. The packaging structure as described in claim 1, characterized in that, The molding material exposes the on-silicon via of the first logic die.

3. The packaging structure as described in claim 1, characterized in that, The first logic wafer also includes: A first substrate, wherein the lower silicon via penetrates the first substrate; and A second substrate, wherein the through-silicon via extends through the second substrate, wherein a device in the device layer is separated from the through-silicon via in a vertical direction.

4. The packaging structure as described in claim 3, characterized in that, In a vertical direction, the height of the upper silicon via is different from the height of the conductive via.

5. The packaging structure as described in claim 1, characterized in that, It also includes a second logic die, configured to be adjacent to the first logic die and electrically connected to the conductive via.

6. The packaging structure as described in claim 1, characterized in that, It also includes a device element located above the redistribution layer.

7. A bare die structure, characterized in that, include: A first packaged component, comprising: A first through-silicon via is located in a first substrate; A first device layer is located above the first substrate, wherein the first device layer includes a plurality of first devices, and the plurality of first devices are electrically connected to the first through-silicon via; and A first power transmission layer is located above the first device layer, wherein the first through-silicon via extends into the first power transmission layer; and A second packaged component, comprising: A second through-silicon via is located in a second substrate; A second device layer is located above the second substrate, wherein the second device layer includes a plurality of second devices, and the plurality of second devices are electrically connected to the second through-silicon via; and A second power transmission layer, located above the second device layer. The first device layer is joined to the second device layer by dielectric-to-dielectric bonding and metal-to-metal direct bonding of the first power transmission layer and the second power transmission layer.

8. The bare die structure as described in claim 7, characterized in that, The first device layer also includes a plurality of first bonding pads, and the second device layer also includes a plurality of second bonding pads, and each of the plurality of first bonding pads is aligned with one of the plurality of second bonding pads of the second device layer.

9. The bare die structure as described in claim 7, characterized in that, Multiple of the first devices are in contact with the first substrate.

10. The bare die structure as described in claim 7, characterized in that, The second through-silicon via penetrates the second device layer, and the first through-silicon via is offset from a projection area of ​​the second through-silicon via on the second substrate.

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