Semiconductor device structure

Abstract

A semiconductor device structure includes an interposer including an interposer dielectric material layer having an interposer metal interconnect structure and a die-side interposer bonding pad formed therein; at least one semiconductor die having an intra-die bonding pad formed therein, the intra-die bonding pad being bonded to a corresponding one of the die-side interposer bonding pads by metal-to-metal bonding; and a composite die frame laterally surrounding the at least one semiconductor die. The composite grain frame comprises a molding compound grain frame part, the molding compound grain frame part comprises a molding compound material and a frame edge strengthening structure, the frame edge strengthening structure is located at a corner of the composite grain frame, and the frame edge strengthening structure comprises a material of a low thermal expansion coefficient molding compound material at 20 degrees Celsius.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor device structures, and more particularly to semiconductor device structures having a composite die frame. BACKGROUND

[0002] Temperature variations on a semiconductor package can cause warpage within the package structure. Warpage can be caused by differences in the coefficient of thermal expansion (CTE) between different bonding layers within the package structure, such as silicon and organic substrates. Such warpage can also cause cracking within or between various material elements due to the mismatch in CTE. SUMMARY

[0003] It is a purpose of the present utility model to provide a semiconductor device structure to address at least one of the above problems.

[0004] A semiconductor device structure is provided, comprising: a mediator comprising a mediator dielectric material layer having a mediator metal interconnect structure and a die-side mediator bonding pad formed therein; at least one semiconductor die, each of the at least one semiconductor die comprising a respective set of semiconductor devices and a respective in-die dielectric material layer having an in-die metal interconnect structure and an in-die bonding pad formed therein, wherein the in-die bonding pad is bonded to a respective one of the die-side mediator bonding pads by metal-to-metal bonding; and a composite die frame laterally surrounding the at least one semiconductor die and contacting a horizontal surface of one of the mediator dielectric material layers, wherein the composite die frame comprises a molding compound die frame portion comprising a molding compound material and a plurality of frame edge reinforcement structures located at corners of the composite die frame, the frame edge reinforcement structures comprising a material having a coefficient of thermal expansion at 20 degrees Celsius that is lower than the molding compound material.

[0005] According to one embodiment of the present utility model, one of the frame edge reinforcement structures comprises at least one outer sidewall surface that is physically exposed to a vapor phase environment.

[0006] According to one embodiment of the present utility model, one of the frame edge reinforcement structures comprises at least one inner sidewall surface that is in direct contact with the at least one semiconductor die.

[0007] According to one of the embodiments of the present application, one of the frame edge reinforcement structures includes a proximal horizontal surface that is in direct contact with a horizontal surface of the interposer dielectric material layer.

[0008] According to one of the embodiments of the present application, one of the frame edge reinforcement structures includes a distal horizontal surface that is in direct contact with a horizontal surface of the molded plastic die package portion.

[0009] According to one of the embodiments of the present application, one of the frame edge reinforcement structures includes a pair of vertically extending sidewalls that are in direct contact with vertical surfaces of the molded plastic die package portion.

[0010] According to one of the embodiments of the present application, the at least one semiconductor die includes a plurality of semiconductor dies that are laterally separated from one another by the molded plastic die package portion; and the frame edge reinforcement structure is entirely located outside a region of a gap between a pair of the semiconductor dies in a plan view.

[0011] According to one of the embodiments of the present application, the frame edge reinforcement structure has a height that is less than a height of the at least one semiconductor die.

[0012] The present application provides a semiconductor device structure, comprising: a silicon interposer comprising a silicon substrate, a through-silicon via structure provided in the silicon substrate, and an interposer dielectric material layer having an interposer metal interconnect structure and a die side interposer bonding pad formed therein; at least one semiconductor die comprising a die-in bonding pad bonded to the die side interposer bonding pad; and a composite die package laterally surrounding the at least one semiconductor die and comprising a molded plastic die package portion comprising a molded plastic material and a frame edge reinforcement structure located at a corner of the composite die package and comprising a material having a coefficient of thermal expansion at 20 degrees Celsius that is lower than that of the molded plastic material.

[0013] According to one of the embodiments of the present application, at least one of the frame edge reinforcement structures has an L-shaped horizontal cross-sectional shape.

[0014] This disclosure provides a method for forming a semiconductor device structure, comprising: providing a structure including a silicon interposer, the silicon interposer including a portion of a silicon substrate, a through-silicon via structure provided within the silicon substrate, and an interposer dielectric material layer, wherein an interposer metal interconnect structure and a die-side interposer bonding pad are formed in the interposer dielectric material layer; bonding at least one semiconductor die including an in-die bonding pad to the silicon interposer to bond the in-die bonding pad to the die-side interposer bonding pad; and forming a composite die frame surrounding at least one semiconductor die, wherein the composite die frame includes a molding compound die frame portion, the molding compound die frame portion including a molding compound material and a frame edge reinforcement structure, the frame edge reinforcement structure being located at a corner of the composite die frame and including a material whose coefficient of thermal expansion at 20 degrees Celsius is lower than that of the molding compound material. Attached Figure Description

[0015] The manner of this disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily enlarged or reduced.

[0016] FIG. 1A This is a vertical cross-sectional view of a silicon wafer after a through-substrate via structure and a metal interconnect structure have been formed according to an embodiment of the present disclosure.

[0017] FIG. 1B for FIG. 1A A top view of a silicon wafer.

[0018] FIG. 2A This is a vertical cross-sectional view of an assembly of a silicon wafer and a semiconductor die according to an embodiment of the present disclosure.

[0019] FIG. 2B for FIG. 2A A top view of the components.

[0020] FIG. 3A This is a vertical cross-sectional view of an intermediate structure after an in-process frame edge reinforcement structure is positioned on top of an assembly, according to an embodiment of the present disclosure. This intermediate structure includes an assembly of a silicon wafer and a semiconductor die.

[0021] FIG. 3B for FIG. 3A A top view of the intermediate structure.

[0022] FIG. 3C According to an embodiment of this disclosure FIG. 3A as well as FIG. 3B A vertical cross-sectional view of an alternative embodiment of the example structure.

[0023] FIG. 4A Vertical cross-sectional view of an intermediate structure after forming a mold compound material layer according to an embodiment of the present disclosure.

[0024] FIG. 4B Vertical cross-sectional view of an intermediate structure after polishing a top side of an example structure according to an embodiment of the present disclosure. FIG. 4A Vertical cross-sectional view of an alternative embodiment of the example structure of

[0025] FIG. 5A Vertical cross-sectional view of an intermediate structure after thinning a back side of a silicon substrate according to an embodiment of the present disclosure.

[0026] FIG. 5B Top view of an intermediate structure of FIG. 5A

[0027] Vertical cross-sectional view of an alternative embodiment of the example structure of FIG. 5C FIG. 5A Vertical cross-sectional view of an intermediate structure after attaching a carrier wafer according to an embodiment of the present disclosure.

[0028] FIG. 6 Vertical cross-sectional view of an intermediate structure after forming a back side insulating layer according to an embodiment of the present disclosure.

[0029] FIG. 7 Vertical cross-sectional view of an intermediate structure after forming a back side metal bonding pad and a solder material portion according to an embodiment of the present disclosure.

[0030] FIG. 8 Vertical cross-sectional view of an intermediate structure after separating a carrier wafer according to an embodiment of the present disclosure.

[0031] FIG. 9 Vertical cross-sectional view of a fan-out package after singulating the example structure of

[0032] FIG. 10 Top view of the fan-out package of

[0033] FIG. 11A FIG. 10 Top view of the fan-out package in a first alternative state of

[0034] FIG. 11B Top view of the fan-out package in a second alternative state of FIG. 11A

[0035] Top view of the fan-out package in a third alternative state of FIG. 11C FIG. 11A Top view of the fan-out package in a fourth alternative state of

[0036] FIG. 11D FIG. 11A ​​​​​

[0037] FIG. 11E FIG. 1 1 is a top view of a fourth alternative state of the fan-out package of FIG. 11A

[0038] FIG. 11F FIG. 12 is a top view of a fourth alternative state of the fan-out package of FIG. 11A

[0039] FIG. 11G FIG. 13 is a vertical cross-sectional view of an alternative state of the fan-out package.

[0040] FIG. 12 FIG. 14 is a vertical cross-sectional view of components of an example structure including a fan-out package and a package substrate according to an embodiment of the present disclosure.

[0041] FIG. 13 FIG. 15 is a vertical cross-sectional view of the example structure after attachment of a stabilization ring according to an embodiment of the present disclosure.

[0042] FIG. 14 FIG. 16 is a vertical cross-sectional view of the example structure after attachment of components including a fan-out package and a package substrate to a printed circuit board according to an embodiment of the present disclosure.

[0043] FIG. 15 FIG. 17 is a vertical cross-sectional view of a first alternative state of the example structure according to an embodiment of the present disclosure.

[0044] FIG. 16 FIG. 18 is a vertical cross-sectional view of a second alternative state of the example structure according to an embodiment of the present disclosure.

[0045] FIG. 17 FIG. 19 is a vertical cross-sectional view of a third alternative state of the example structure according to an embodiment of the present disclosure.

[0046] FIG. 18 FIG. 20 shows a flowchart for forming a semiconductor device structure according to an embodiment of the present disclosure.

[0047] Reference signs are as follows:

[0048] 100: PCB

[0049] 168: PCB bonding pads

[0050] 190: Solder joint

[0051] 192: Underfill material portion

[0052] 200: Package substrate

[0053] 221: Adhesive layer

[0054] 230: Cap structure​​

[0055] 231: thermally conductive paste

[0056] 248: substrate bonding pad

[0057] 268: substrate bonding pad

[0058] 290: solder material portion

[0059] 292: underfill material portion

[0060] 310: carrier wafer

[0061] 311: adhesive layer

[0062] 400: interposer / silicon interposer

[0063] 400W: interposer wafer

[0064] 410: silicon substrate

[0065] 412: front insulating liner

[0066] 420: through-substrate via structure / TSV structure

[0067] 432: backside insulating layer

[0068] 438: backside metal bonding pad

[0069] 460: interposer dielectric material layer

[0070] 480: metal interconnect structure / interposer metal interconnect structure 488: die side interposer bonding pad

[0071] 700: semiconductor die

[0072] 709: semiconductor die substrate

[0073] 720: semiconductor device

[0074] 760: intra-die dielectric material layer

[0075] 780: intra-die metal interconnect structure

[0076] 788: intra-die bonding pad

[0077] 790: composite die frame

[0078] 792: frame edge stiffening structure

[0079] 792': frame edge stiffening structure in process

[0080] 794: molding compound die frame portion

[0081] 794': Molding material layer

[0082] 800: Fan-out package

[0083] 800W: Reconstituted chip

[0084] 1810, 1820, 1830: Steps

[0085] hd1: First horizontal direction

[0086] hd2: Second horizontal direction

[0087] LDD1: Lateral dimension of the first grain

[0088] LDD2: Lateral dimension of the second grain

[0089] RSD1: First reinforced structural dimension

[0090] RSD2: Second Reinforcement Structure Dimension

[0091] t1: First thickness

[0092] t2: Second thickness

[0093] UA: Cell Region Detailed Implementation

[0094] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0095] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn. Unless otherwise explicitly stated, each element with the same reference numeral is assumed to have the same material composition and a thickness within the same thickness range.

[0096] Differences in coefficients of thermal expansion (CTE) between elements of a package structure can cause cracking within the package structure. For example, if the temperature of a fan-out package including a semiconductor die, molding surrounding the semiconductor die, a silicon interposer, a package substrate, and a lid structure covering the semiconductor die is raised, elements having a higher CTE, such as the molding, the lid, and the package substrate, can expand more than the semiconductor die and the silicon interposer. As a result, tensile stress can be applied between the semiconductor die and the silicon interposer. In this case, cracking can occur at the interface.

[0097] Embodiments of the present disclosure provide structures and methods for mitigating the development of such cracking. In particular, a frame edge strengthening structure can be used in combination with a molding compound frame element to provide a composite die frame. The molding compound frame element includes a molding compound material and can be provided at a location where mechanical stress is less. The frame edge strengthening structure can be located at a frame edge that is subject to the highest level of mechanical stress caused by thermal expansion and includes a material having a lower CTE than the molding compound material. During use of the package structure, the composite die frame provides enhanced resistance to thermally induced cracking. Various ways of the present disclosure are now described with reference to the accompanying drawings.

[0098] Referring to FIG. 1A and FIG. 1B , an intermediate structure is shown according to an embodiment of the present disclosure, including a silicon wafer, a through-substrate via structure 420 formed in an upper portion of the silicon wafer, and an interposer dielectric material layer 460 having formed therein metal interconnect structures 480 and metal bonding pads, referred to in the present disclosure as die-side interposer bonding pads 488. The silicon wafer can include a silicon substrate 410 composed of a silicon-based semiconductor material. The silicon-based semiconductor material can be single-crystalline or polycrystalline and can be doped or undoped with electrical dopants, such as n-type or p-type dopants. In one embodiment, the silicon wafer can be a commercially available silicon wafer having a diameter of 150 mm, 200 mm, 300 mm, or 450 mm.

[0099] For example, an array of via cavities can be formed in an upper portion of a silicon wafer by forming an etch mask layer including a hard mask material (e.g., borosilicate glass), patterning the etch mask layer using a pattern of a separate array of openings, and transferring the pattern in the etch mask layer into the upper portion of the silicon wafer. The depth of the via cavities can be in a range of 3 microns to 30 microns, such as 5 microns to 20 microns, while the lateral dimension (e.g., diameter) of the via cavities can be in a range of 0.5 microns to 10 microns, such as 1 micron to 6 microns, although smaller or larger dimensions can be used. In one embodiment, the pattern of the array of via cavities can have a two-dimensional periodicity over the silicon wafer. A repeating unit pattern can be within a unit area UA, which can be a rectangular area corresponding to the area of a spacer to be singulated from the example structure in a subsequent process step.

[0100] A front insulating liner 412 can be formed in the surrounding portions of the via cavities and over the top surface of the silicon substrate 410. The front insulating liner 412 includes an insulating material, such as silicon oxide, and the thickness of the front insulating liner 412 is in a range of 1% to 20% of the lateral dimension of each via cavity, such as 2% to 5%. At least one conductive material, such as at least one metallic material, can be deposited in the remaining unfilled volume of the via cavities. In one embodiment, the at least one conductive material can include a combination of a metallic barrier material (e.g., titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium carbide, tantalum carbide, tungsten carbide, etc.) and a metallic fill material (copper, cobalt, ruthenium, molybdenum, tungsten, etc.). Other suitable metallic barrier materials and metallic fill materials are also within the contemplation of the present disclosure. Excess portions of the at least one conductive material can be removed from the level of the top surface of the horizontally extending portion including the front insulating liner 412 by a planarization process including a chemical mechanical polishing process (CMP) and / or a recess etch process. Each remaining portion of the at least one conductive material within a corresponding via cavity can include a through-silicon via (TSV) structure 420. An array of TSV structures can be formed within each unit area UA.

[0101] An interposer dielectric material layer 460, a metal interconnect structure 480, and a die-side interposer bonding pad 488 can be subsequently formed over the TSV structure 420 and over the front insulating liner 412. The interposer dielectric material layer 460 includes and / or consists essentially of an interlayer dielectric (ILD) material, such as silicon oxide, silicon nitride, organosilicate glass, etc. Other suitable dielectric materials are within the contemplation of the present disclosure. In an embodiment, the interposer dielectric material layer 460 can include and / or consist essentially of an inorganic dielectric material, such as silicon oxide and silicon nitride. The metal interconnect structure 480 can include metal line and metal via structures that are interconnected to one another to provide electrically conductive paths. The die-side interposer bonding pad 488 is electrically connected to the metal interconnect structure 480.

[0102] In an embodiment, a first subset of the die-side interposer bonding pads 488 can be electrically connected to one another and provide electrically conductive paths to and from a semiconductor die that is subsequently bonded to the die-side interposer bonding pads 488. In an embodiment, one or more of the die-side interposer bonding pads 488 within the first subset of the die-side interposer bonding pads 488 can be electrically isolated from the TSV structure 420. In an embodiment, a second subset of the die-side interposer bonding pads 488 is electrically connected to a respective one of the TSV structures 420 and electrically isolated from the other die-side interposer bonding pads 488. In an embodiment, a third subset of the die-side interposer bonding pads 488 is electrically connected to a respective one of the TSV structures 420 and electrically connected to a respective one of the additional die-side interposer bonding pads 488.

[0103] The die-side interposer bonding pads 488 can be formed within a topmost one of the interposer dielectric material layers 460. In an embodiment, a top surface of the die-side interposer bonding pads 488 can be located within a same horizontal plane as a top surface of the topmost one of the interposer dielectric material layers 460.

[0104] The intermediate structure shown in FIG. 1A The intermediate structure shown in FIG. 1B includes an interposer wafer 400W that contains a two-dimensional array of interposers 400 that are contiguous with one another. Each of the interposers 400 is located within a respective unit area UA and can be a silicon interposer 400, i.e., an interposer 410 that includes a silicon substrate.

[0105] Generally, this structure includes a silicon interposer 400 that contains a portion of a silicon substrate 410, a TSV structure 420 located within the silicon substrate 410, and an interposer dielectric material layer 460 having an interposer metal interconnect structure 480 and a die side interposer bonding pad 488 formed therein. In one embodiment, this structure includes a two-dimensional array of silicon interposers 400.

[0106] Referring to FIG. 2A With FIG. 2B A set of at least one semiconductor die 700 can be disposed over a respective silicon interposer 400 that is located within a respective unit area UA. Each semiconductor die 700 can include a respective semiconductor die substrate 709, a respective set of semiconductor devices 720 located in, on, or above the respective semiconductor die substrate 709, and a respective intra-dielectric material layer 760 having an intra-die metal interconnect structure 780 and an intra-die bonding pad 788 formed therein. In one embodiment, the respective semiconductor die substrate 709 can be a silicon substrate, and the respective set of semiconductor devices can include various semiconductor devices known in the art, such as field effect transistors. The intra-dielectric material layer 760 can include an inorganic ILD material, such as silicon oxide or silicon nitride. The intra-die metal interconnect structure 780 can include metal via structures and metal line structures that are interconnected to the semiconductor devices 720 and to each other. The intra-die bonding pad 788 can be formed in the topmost dielectric material layer of the intra-dielectric material layer 760 and can be electrically connected to the intra-die metal interconnect structure 780. In one embodiment, a top surface of the intra-die bonding pad 788 can be formed within a horizontal plane that includes a top surface of the topmost dielectric material layer of the intra-dielectric material layer 760.

[0107] Each group of at least one semiconductor die 700 includes at least one semiconductor die and can include a plurality of semiconductor dies 700. For example, each group of at least one semiconductor die 700 can include at least one system-on-chip (SoC) die and / or at least one memory die. Each SoC die can include an application processor die, a central processing unit die, or a graphics processing unit die. In one embodiment, at least one memory die can include a high bandwidth memory (HBM) die that includes a vertical stack of static random access memory (SRAM) dies. In one embodiment, at least one semiconductor die can include at least one SoC die and at least one HBM die. Each HBM die can include a vertical stack of SRAM dies that are interconnected to each other by an array of microbumps and are laterally surrounded by a respective plastic enclosure frame.

[0108] Referring to FIG. 3A With FIG. 3B According to one way of the disclosure, a discrete material portion can be located at each corner of the rectangular area of the cell area UA at the level of the semiconductor die 700. The discrete material portion is then incorporated into the die frame and provides a function of enhancing the structural stability of the die frame during thermal expansion. Prior to incorporation into the respective die frame, the discrete material portion can be segmented into a respective group of segmented material portions. Thus, the discrete material portion refers to an in-process frame edge strengthening structure 792’ in the disclosure. As used in the disclosure, an “in-process” structural element refers to a structural element that is subsequently modified in structure or material composition.

[0109] Generally, the in-process frame edge strengthening structure 792' comprises and / or is substantially comprised of a material having a CTE lower than a material of a subsequently used mold compound material to form a mold compound die frame layer. Typical mold compound materials used in the semiconductor industry have a CTE at 20 degrees Celsius in the range of 20 ppm / °C (parts per million per degree) to 40 ppm / °C. Materials that can be used for the in-process frame edge strengthening structure 792' include additional mold compound materials having a CTE lower than a subsequently used mold compound material to form a mold compound die frame layer, die attach films, epoxy materials, underfill materials, and semiconductor materials (e.g., silicon). The CTE (at 20 degrees Celsius) of the material used for the in-process frame edge strengthening structure 792' can be in the range of 2 ppm / °C to 25 ppm / °C, preferably in the range of 2 ppm / °C to 20 ppm / °C, and more preferably in the range of 2 ppm / °C to 15 ppm / °C. However, it should be recognized that various embodiments of the present disclosure can practice any combination of a first material for the in-process frame edge strengthening structure 792' and a second material for the mold compound die frame layer, as long as the CTE of the first material is lower than the CTE of the second material at 20 degrees Celsius.

[0110] Generally, the in-process frame edge strengthening structure 792' can have any shape as long as the in-process frame edge strengthening structure 792' can fit into a gap at a rectangular corner of a cell region located between a pair of adjacent groups of at least one semiconductor die 700, each group of at least one semiconductor die 700 bonded to a respective interposer 400. In one embodiment, the in-process frame edge strengthening structure 792' can have a shape that causes each in-process frame edge strengthening structure 792' to be in direct contact with a respective group of semiconductor dies 700. In one embodiment, where the in-process frame edge strengthening structure 792' has a cross shape in a top view, the in-process frame edge strengthening structure 792' can contact sidewalls of four semiconductor dies 700. For example, a cross-shaped in-process frame edge strengthening structure 792' can contact eight sidewalls of four semiconductor dies 700.

[0111] In one embodiment, the in-process frame edge strengthening structure 792' can be disposed directly on top of a top surface of the interposer dielectric material layer 460 surrounding the semiconductor dies 700. In one embodiment, the at least one semiconductor die 700 located within the cell region UA comprises a plurality of semiconductor dies 700. In one embodiment, the in-process frame edge strengthening structure 792' can be positioned entirely outside of a gap between a pair of adjacent groups of the plurality of semiconductor dies 700 in a plan view. In one embodiment, the in-process frame edge strengthening structure 792' has a height that is not less than a maximum height of the semiconductor dies 700.

[0112] In one embodiment, one, more, and / or each of the frame edge reinforcement structures 792' in the process includes a vertically extending sidewall physically exposed to the gas phase environment. In one embodiment, one, more, and / or each of the frame edge reinforcement structures 792' in the process includes at least one internal sidewall in direct contact with the corresponding semiconductor die 700. In one embodiment, one, more, and / or each of the frame edge reinforcement structures 792' in the process includes a proximal water surface in direct contact with the horizontal surface of the dielectric material layer 460.

[0113] The bonding pads 788 within the semiconductor die 700 can be aligned with the die-side intermediate bonding pads 488 of the corresponding intermediate 400 located within the intermediate wafer 400W. The frame edge reinforcement structure 792' in the process can be aligned with the gap between groups covering at least one semiconductor die 700 of adjacent pairs of intermediates 400.

[0114] In one embodiment, each array of in-die bonding pads 788 located within a semiconductor die 700 can be bonded to a corresponding subset of the array of die-side intermediate bonding pads 488 via metal-to-metal bonding, such as copper-to-copper bonding. Furthermore, the topmost dielectric layer within the in-die dielectric layer 760 of each semiconductor die 700 can be bonded to the topmost dielectric layer within the intermediate dielectric layer 460 via dielectric-to-dielectric bonding, such as oxide-to-oxide bonding. Generally, the semiconductor die 700 can be disposed above a two-dimensional array of intermediate 400 such that each array of in-die bonding pads 788 contacts a corresponding subset of the array of die-side intermediate bonding pads 488. Metal-to-metal bonding or dielectric-to-dielectric bonding can be performed sequentially or simultaneously by performing a thermal annealing process in a temperature range of 200°C to 400°C while pressing the semiconductor die 700 against the intermediate wafer 400W. At least one semiconductor die 700 located within each unit region UA ​​may include a plurality of semiconductor dies 700 laterally separated from each other, or may include a single semiconductor die 700.

[0115] Reference FIG. 3C , to show FIG. 3A and FIG. 3B A vertical cross-sectional view of an alternative embodiment of the example structure in the diagram. This can be achieved by using a frame edge reinforcement structure 792' in a process with a height smaller than that of the semiconductor die 700. FIG. 3A and FIG. 3B The example structure shown derives this replacement state.

[0116] Referring FIG. 4A , a mold compound material can be applied over the interposer wafer 400W, over the array of the set of at least the semiconductor die 700 bonded to the array of silicon interposers 400 in the interposer wafer 400W, and over the frame edge strengthening structure 792' in the process. The mold compound material includes an epoxy-containing compound that can be hardened (e.g., cured) to provide a dielectric material portion that is sufficiently rigid and mechanically strong. The mold compound material can include an epoxy resin, a hardener, silica as a filler material, and other additives. The mold compound material can be provided in a liquid form or a solid form depending on the viscosity and flowability. The liquid mold compound material generally provides better handling, good flowability, less voids, better filling, and less flow marks. The solid mold compound material generally provides less cure shrinkage, better stand-off, and less die drift. A high filler content (e.g., 85% by weight) in the mold compound material can reduce the time in the mold, reduce mold shrinkage, and reduce mold warpage. A uniform filler size distribution in the mold compound material can reduce flow marks and enhance flowability.

[0117] A mold compound material layer 794' can be formed by the mold compound material. The mold compound material layer 794' can fill the remaining gaps between the adjacent pairs of semiconductor dies 700. The mold compound material layer 794' can cover each semiconductor die 700 and can have a top surface that extends continuously over each semiconductor die 700. Generally, the CTE of the mold compound material at 20 degrees Celsius is higher than the CTE of the frame edge strengthening structure 792' in the process. In an embodiment, the CTE of the material of the frame edge strengthening structure 792' in the process is less than the CTE of the mold compound material at any temperature in the temperature range of 20 degrees Celsius to 100 degrees Celsius. In an embodiment, the CTE of the frame edge strengthening structure 792' in the process can be less than 90% and / or 80% and / or 70% and / or 60% and / or 50% and / or 40% and / or 30% of the CTE of the mold compound material at any temperature in the temperature range of 20 degrees Celsius to 100 degrees Celsius. The combination of the interposer wafer 400W, the semiconductor dies 700, the frame edge strengthening structure 792' in the process, and the mold compound material layer 794' constitutes a reconstituted wafer 800W that includes a plurality of fan-out packages in manufacturing, i.e., a plurality of fan-out packages in the process.

[0118] Referring FIG. 4B , an alternative embodiment of the example structure after the process steps described in Referring FIG. 4A to FIG. 8A is shown. The mold compound material layer 794' can be formed by applying a mold compound material and by forming the mold compound material layer 794' from the mold compound material.FIG. 3C An alternative embodiment of the example structure shown derives from FIG. 4B An alternative embodiment of the example structure shown, the layer of molding compound material 794' can have the same material properties as the layer of molding compound material 794' described above. In FIG. 4A An alternative embodiment of the example structure shown, the top surface of the frame edge strengthening structure 792' in the process can be formed below the horizontal plane of the top surface of the thickest semiconductor die 700 among the semiconductor dies 700 in the reconstituted wafer 800W. FIG. 4B

[0119] Referring to FIG. 5A With FIG. 5B A polishing process can be performed to remove the horizontally extending portions of the layer of molding compound material 794' above the horizontal plane of the top surface of the thinnest semiconductor die 700. For example, a CMP process can be performed to remove the horizontally extending portions of the layer of molding compound material 794' and optionally remove the topmost portions of the semiconductor dies 700. All physically exposed top surfaces of the semiconductor dies 700 and the polished horizontal surfaces of the layer of molding compound material 794' can be formed within a two-dimensional horizontal plane.

[0120] Referring to FIG. 5C An alternative state of the example structure shown can be derived from FIG. 5A With FIG. 5B the process steps described above. FIG. 4B This alternative state is derived from the alternative state of the example structure shown.

[0121] Referring to FIG. 6 A bonding layer 311 can be applied to the top surfaces of the semiconductor dies 700 and to the top surface of the layer of molding compound material 794'. A carrier wafer 310 can be attached to the bonding layer 311. In one embodiment, the bonding layer 311 can include an optional transparent substrate, such as a glass substrate or a sapphire substrate, or can include a semiconductor substrate, such as a silicon substrate. The diameter of the carrier wafer 310 can be the same as the diameter of the silicon wafer. The thickness of the carrier wafer 310 can be in the range of 500 microns to 2000 microns, although smaller or larger thicknesses can also be used. In one embodiment, the bonding layer 311 can be a light-to-heat conversion (LTHC) layer. Alternatively, the bonding layer 311 can include a thermally decomposable bonding material.

[0122] Referring to FIG. 7 ​A backside polish process can be performed to remove the backside of the silicon wafer. The silicon substrate 410 can be removed by lapping, polishing, an anisotropic etch process, an isotropic etch process, or a combination thereof. In one embodiment, a plurality of silicon removal processes can be subsequently performed to remove the backside of the silicon wafer until the bottom surface of the TSV structure 420 is exposed. The front insulating liner 412 and / or the TSV structure 420 can serve as a lapping stop structure and / or an etch stop structure. In one embodiment, the plurality of silicon removal processes can include a terminal process using a CMP process, after which the bottom surface of the TSV structure 420 can be exposed.

[0123] Referring to FIG. 8 For example, the backside silicon surface of the silicon substrate 410 can be vertically recessed by performing an isotropic etch process that selectively removes silicon with respect to the front insulating liner 412 and the TSV structure 420. In one illustrative example, a wet etch process using potassium hydroxide can be performed to vertically recess the backside silicon surface of the silicon substrate 410 by a vertical recess distance. The vertical recess distance can be in the range of 100 nm to 500 nm, although smaller or larger vertical recess distances can also be used.

[0124] An insulating material, such as silicon oxide, can be deposited over the recessed backside surface of the silicon substrate 410 to form a backside insulating layer 432. The thickness of the backside insulating layer 432 can be approximately the same as or greater than the vertical recess distance of the backside silicon surface of the silicon substrate 410. A planarization process, such as a polishing process, can be performed to remove portions of the backside insulating layer 432 that protrude downward below the horizontal plane that includes the bottom surface of the TSV structure 420. In this embodiment, the bottom surface of the TSV structure 420 can be coplanar with the physically exposed surface of the backside insulating layer 432.

[0125] Referring to FIG. 9 A backside metal bond pad 438 and a solder material portion 290 can be formed over the physically exposed bottom surface of the TSV structure 420. In one illustrative example, a metal material layer stack including an underbump metallurgy (UBM) material layer can be deposited over the TSV structure 420 and over the distal surface of the backside insulating layer 432. A solder material layer can be deposited over the metal material layer stack. A photoresist layer (not shown) can be applied and photo lithographically patterned over the solder material layer, and the pattern in the photoresist layer can be transferred through the solder material layer and the metal material layer stack to form an array of solder material portions 290 and an array of backside metal bond pads 438 over each silicon interposer 400. The photoresist layer can be subsequently removed by ashing, for example.

[0126] Referring to FIG. 10The carrier wafer 310 can be detached from the reconstituted wafer 800W. In some embodiments, the carrier wafer 310 can be removed by backside grinding to adhere the layer 311. Alternatively, the carrier wafer 310 comprises an optional transparent material and the adhesive layer 311 comprising a photothermal conversion material, and the carrier wafer 310 is detached using illumination through the carrier wafer 310. If the adhesive layer 311 comprises a thermally decomposable adhesive material, the carrier wafer 310 can be detached using an annealing process or laser illumination. A suitable cleaning process can be performed to remove residual portions of the adhesive layer 311. The reconstituted wafer 800W comprises a two-dimensional array of silicon intermediates 400, and further comprises a two-dimensional array of groups of at least one semiconductor die 700 bonded to a respective silicon intermediate 400.

[0127] Referring to FIG. 11A With FIG. 11B The reconstituted wafer 800W can be singulated along singulation channels by a singulation process. The singulation channels correspond to boundaries between adjacent pairs of unit areas UA. Each singulated unit from the reconstituted wafer 800W comprises a fan-out package 800. Each singulated portion of the layer of molding compound material 794’ constitutes a molding compound die frame portion 794. Each singulated portion of the in-process frame edge strengthening structure 792’ constitutes a frame edge strengthening structure 792. Each contiguous assembly of molding compound die frame portions 794 and the plurality of frame edge strengthening structures 792 constitutes a composite die frame 790. In general, each in-process frame edge strengthening structure 792’ can be divided into a plurality of frame edge strengthening structures 792 belonging to different fan-out packages 800. In one embodiment, the in-process frame edge strengthening structure 792’ can be divided into four frame edge strengthening structures 792, which are incorporated into four different fan-out packages. In one illustrative example, a cross-shaped in-process frame edge strengthening structure 792’ can be divided into four L-shaped frame edge strengthening structures 792.

[0128] The singulated portions of the reconstituted wafer comprise fan-out packages 800. Each fan-out package 800 comprises at least one semiconductor die 700, a silicon intermediate 400, and a composite die frame 790. In general, the composite die frame 790 can be formed around the at least one semiconductor die 700 located within each fan-out package 800. The composite die frame 790 comprises a molding compound die frame portion 794 comprising a molding compound material, and a frame edge strengthening structure 792 located at a corner of the composite die frame 790 and comprising a material having a CTE lower than the molding compound material at 20 degrees Celsius.

[0129] In an embodiment, the composite die frame 790 laterally surrounds at least half of the semiconductor dies 700 and contacts a horizontal surface of a topmost one of the interposer dielectric material layers 460. In an embodiment, each of the one or more and / or each frame edge reinforcement structure 792 within each fan-out package 800 includes at least one exterior sidewall that is physically exposed to a gaseous environment (e.g., air). In an embodiment, each of the one or more and / or each frame edge reinforcement structure 792 within each fan-out package 800 includes at least one interior sidewall that is in direct contact with one of the at least half of the semiconductor dies 700. In an embodiment, each of the one or more and / or each frame edge reinforcement structure 792 within each fan-out package 800 includes a proximal horizontal surface that is in direct contact with a horizontal surface of the interposer dielectric material layer 460. In an embodiment, each of the one or more and / or each frame edge reinforcement structure 792 within each fan-out package 800 includes a pair of vertically extending sidewalls that are in direct contact with a vertical surface of the molded die frame portion 794.

[0130] In an embodiment, each of the one or more and / or each frame edge reinforcement structure 792 within each fan-out package 800 includes a respective topmost die-internal dielectric material layer 760 that is bonded to a topmost one of the interposer dielectric material layers 460 by way of dielectric-to-dielectric bonding. In an embodiment, the at least half of the semiconductor dies 700 includes a plurality of semiconductor dies 700 that are laterally separated from one another by the molded die frame portion 794; and the frame edge reinforcement structure 792 is entirely located outside of a gap between a pair of the plurality of semiconductor dies 700 in a plan view perspective. In an embodiment, the frame edge reinforcement structure 792 has a height that is the same as a height of each of the at least half of the semiconductor dies 700.

[0131] In an embodiment, the frame edge reinforcement structure 792 includes a material selected from the group consisting of additional molded plastic material, die attach film, epoxy material, underfill material, and semiconductor material. In an embodiment, at least one of the frame edge reinforcement structures 792 has an L-shaped horizontal cross-sectional shape.

[0132] In general, the fan-out package 800 can have a rectangular shape and can have a pair of first sidewalls that extend laterally along a first horizontal direction hd1 and a pair of second sidewalls that extend laterally along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd2. The fan-out package 800 can have a first die lateral dimension LDD1 along the first horizontal direction hd1 and a second die lateral dimension LDD2 along the second horizontal direction hd2. The second die lateral dimension LDD2 can be less than, equal to, or greater than the first die lateral dimension LDD1.

[0133] The frame edge reinforcement structure 792 may have a first lateral dimension along a first horizontal direction hd1, referred to herein as a first reinforcement structure dimension RSD1; and may have a second lateral dimension along a second horizontal direction hd2, referred herein as a second reinforcement structure dimension RSD2. In one embodiment, the lateral extension region of the molding compound grain frame portion 794 extending laterally along the first horizontal direction hd1 may have a first thickness t1. In one embodiment, the lateral extension portion of the frame edge reinforcement structure 792 extending laterally along the second horizontal direction hd2 may have a second thickness t2. In one embodiment, the lateral extension region of the molding compound grain frame portion 794 extending laterally along the second horizontal direction hd2 may have a second thickness t2. In one embodiment, the lateral extension portion of the frame edge reinforcement structure 792 extending laterally along the first horizontal direction hd1 may have a first thickness t1.

[0134] In some embodiments, at least one semiconductor die 700 attached to the silicon interposer 400 may be a plurality of semiconductor dies 700. FIG. 11A and FIG. 11B In the illustrated state, at least one semiconductor die 700 includes three semiconductor dies 700.

[0135] Reference FIG. 11C The diagram shows a top view of a first alternative configuration of the fan-out package 800. In this first alternative configuration, at least one semiconductor die 700 comprises two semiconductor dies 700. Generally, at least one semiconductor die 700 bonded to the silicon interposer 400 may comprise any number of semiconductor dies 700.

[0136] Reference FIG. 11D This can be achieved by using a rectangular frame edge reinforcement structure 792 with a width equal to either the first thickness t1 or the second thickness t2. FIG. 11A to FIG. 11C The fan-out package derives a second alternative state of the fan-out package 800. In this embodiment, the first reinforcement structure dimension RSD1 may be equivalent to the first thickness t1, or the second reinforcement structure dimension RSD2 may be equivalent to the second thickness t2. In this embodiment, the frame edge reinforcement structure 792' in the process may have twice the length of the frame edge reinforcement structure 792 and twice the width of the frame edge reinforcement structure 792.

[0137] Reference FIG. 11E This can be achieved by using a rectangular frame edge reinforcement structure 792 to make the first reinforcement structure dimension RSD1 smaller than the first thickness t1, and / or to make the second reinforcement structure dimension RSD2 smaller than the second thickness t2. FIG. 11A to FIG. 11DThe fan-out package derives a third alternative state of the fan-out package 800. In this embodiment, the frame edge reinforcement structures 792 are laterally separated from each other by the thin sidewall portions of the molding die frame portion 794. In this embodiment, the frame edge reinforcement structure 792' in the process may have twice the length of the frame edge reinforcement structure 792 and twice the width of the frame edge reinforcement structure 792. Generally, at least one of the frame edge reinforcement structures 792 may have a rectangular horizontal cross-sectional shape.

[0138] Reference FIG. 11F This illustrates a fourth alternative state of the fan-out package 800, which can be achieved by replacing multiple semiconductor dies 700 with a single semiconductor die 700. FIG. 11A to FIG. 11D Any of the fan-out packages can derive a fourth replacement state.

[0139] Reference FIG. 11G This shows the replacement state of the fan-out package 800, which can be achieved by using, for example... FIG. 5C The diagram shows a frame edge reinforcement structure 792' with a height less than the semiconductor die height of 700. FIG. 11A to FIG. 11D This alternative configuration arises from the fan-out packaging. In this embodiment, the height of each frame edge reinforcement structure 792 is less than the height of at least one semiconductor die 700. In one embodiment, one, more, and / or each frame edge reinforcement structure 792 includes a distal horizontal surface (i.e., a horizontal surface away from the interface between the silicon interposer 400 and the semiconductor die 700) that is in direct contact with the horizontal surface of the molding die frame portion 794.

[0140] Generally, the height of each frame edge reinforcement structure 792 can range from 1 micrometer to 100% of the thickness of the semiconductor die 700. In some embodiments, the height of each frame edge reinforcement structure 792 can be less than 100% and / or 80% and / or 60% and / or 40% of the thickness of the semiconductor die 700. The first reinforcement structure size RSD1 can be greater than 1 micrometer and less than 50% of the first die lateral size LDD1. The second reinforcement structure size RSD2 can be greater than 1 micrometer and less than 50% of the second die lateral size LDD2.

[0141] Reference FIG. 12 The packaging substrate 200 can be bonded to the fan-out package 800, which can be a FIG. 11A to FIG. 11GAny of the fan-out packages 800 shown. The package substrate 200 can be a core package substrate that includes a core substrate, or can be a coreless package substrate that does not include a package core. Alternatively, the package substrate 200 can include a system-on-integrated packaging substrate (SoIS) that includes a redistribution layer, a dielectric interlayer, and / or at least one embedded interposer (e.g., a silicon interposer). Such a system-on-integrated packaging substrate can include layer-to-layer interconnections using solder material portions, micro-bumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. In some embodiments, the package substrate 200 can comprise a system-on-integrated packaging substrate that includes a glass epoxy plate having an array of through-plate holes. An array of core- through via structures (not shown) comprising a metal material can be provided in the through-plate holes. Each core-through via structure can or can not include a cylindrical hollow portion therein. Optionally, a dielectric liner (not shown) can be used to electrically isolate the core-through via structures from the core substrate.

[0142] The substrate bonding pads 268 can be provided on one side of the package substrate 200, and the board-side bonding pads 248 can be provided on the other side of the package substrate 200. The fan-out package 800 can be attached to the package substrate 200 using second solder material portions, which are referred to in this disclosure as interposer-substrate-bonding (ISB) solder material portions 290. Specifically, each ISB solder material portion 290 can be bonded to a respective one of the substrate bonding pads 268, and to a respective one of the backside metal bonding pads 438 located on the silicon interposer 400. A reflow process can be performed to reflow the ISB solder material portions 290 so that the ISB solder material portions 290 can be bonded to the respective ones of the substrate bonding pads 268, and to the respective ones of the backside metal bonding pads 438.

[0143] An underfill material can be applied into the gap between the silicon interposer 400 and the package substrate 200. The underfill material can comprise any underfill material known in the art. An underfill material portion can be formed around the ISB solder material portions 290 located in the gap between the interposer 400 and the package substrate 200. This underfill material portion is referred to in this disclosure as an interposer-substrate underfill material portion 292 or IP underfill material portion 292.

[0144] Referring to FIG. 13 , for example, the stiffener ring 220 can be attached to the peripheral portion of the top surface of the package substrate 200 by an adhesive layer 221.

[0145] Referring to FIG. 14 , a printed circuit board (PCB) 100 can be provided that includes a PCB substrate and PCB bond pads 168. The PCB 100 includes printed circuits (not shown) on at least one side of the PCB substrate. Solder joints 190 can be formed to bond an array of board-side bond pads 248 to an array of PCB bond pads 168. The solder joints 190 can be formed by disposing an array of solder balls between the array of board-side bond pads 248 and the array of PCB bond pads 168 and reflowing the array of solder balls. Additional underfill material portions, referred to in this disclosure as board-substrate underfill material portions 192 or BS underfill material portions 192, can be formed by applying and shaping underfill material. The package substrate 200 is attached to the PCB 100 by the array of solder joints 190.

[0146] Referring to FIG. 15 , a first alternative state of the example structure is shown according to an embodiment of the disclosure. This first alternative state can be derived from the example structure shown in FIG. 14 by using a frame edge-stiffened structure 792 having a height that is less than the height of the semiconductor die 700.

[0147] Referring to FIG. 16 , a second alternative state of the example structure is shown according to an embodiment of the disclosure. The second alternative state can be derived from the example structure shown in FIG. 14 by using a cap-like structure 230 in place of the stiffener ring 200. In this embodiment, thermally conductive paste 231 can be applied between the top surface of the semiconductor die 700 and the bottom surface of the horizontally extending portion of the cap-like structure 230.

[0148] Referring to FIG. 17 , a third alternative state of the example structure is shown according to an embodiment of the disclosure. The third alternative state can be derived from the first alternative state of the example structure shown in FIG. 15 by using a cap-like structure 230 in place of the stiffener ring 200. In this embodiment, thermally conductive paste 231 can be applied between the top surface of the semiconductor die 700 and the bottom surface of the horizontally extending portion of the cap-like structure 230.

[0149] Referring to FIG. 18According to an embodiment of the present disclosure, a flowchart illustrates steps for forming a semiconductor device structure.

[0150] Referring to step 1810, FIG. 1A and FIG. 1B a structure is provided including a silicon interposer 400, a TSV structure 420, and an interposer dielectric material layer 460, the silicon interposer 400 including a portion of a silicon substrate 410, the TSV structure 420 extending vertically through the silicon substrate 410, the interposer dielectric material layer 460 having an interposer metal interconnect structure 480 and a die side interposer bond pad 488 formed therein.

[0151] Referring to step 1820, FIG. 2A and FIG. 3B at least one semiconductor die 700 including a die-in bond pad 788 is bonded to the silicon interposer 400 to bond the die-in bond pad 788 to the die side interposer bond pad 488.

[0152] Referring to step 1830 and FIG. 3A to FIG. 17 a composite die frame 790 is formed around the at least one semiconductor die 700. The composite die frame 790 includes a mold compound die frame portion 794 including a mold compound material and a frame edge stiffening structure 792 located at a corner of the composite die frame 790 and including a material having a CTE at 20 degrees Celsius that is lower than the mold compound material.

[0153] Referring to all of the figures and according to various embodiments of the present disclosure, a semiconductor device structure is provided including an interposer 400 including an interposer dielectric material layer 460 having an interposer metal interconnect structure 480 and a die side interposer bond pad 488 formed therein, at least one semiconductor die 700 each including a respective set of semiconductor devices 720 and a respective die-in dielectric material layer 760 having a die-in metal interconnect structure 780 and a die-in bond pad 788 formed therein, wherein the die-in bond pad 788 is bonded to a respective one of the die side interposer bond pads 488 by a metal-to-metal bond, and a composite die frame 790 laterally surrounding the at least one semiconductor die 700 and contacting a horizontal surface of one of the interposer dielectric material layers 460, wherein the composite die frame 790 includes a mold compound die frame portion 794 including a mold compound material and a frame edge stiffening structure 792 located at a corner of the composite die frame 790 and including a material having a coefficient of thermal expansion at 20 degrees Celsius that is lower than the mold compound material.

[0154] In an embodiment, one of the frame edge reinforcement structures 792 includes at least one outer sidewall surface that is physically exposed to the vapor phase environment. In an embodiment, one of the frame edge reinforcement structures 792 includes at least one inner sidewall surface that is in direct contact with at least one of the semiconductor die. In an embodiment, one of the frame edge reinforcement structures 792 includes a proximal horizontal surface that is in direct contact with a horizontal surface of the interposer dielectric material layer 460. In an embodiment, one of the frame edge reinforcement structures 792 includes a distal horizontal surface that is in direct contact with a horizontal surface of the molded compound die frame portion 794. In an embodiment, one of the frame edge reinforcement structures 792 includes a pair of vertically extending sidewalls that are in direct contact with vertical surfaces of the molded compound die frame portion 794.

[0155] In an embodiment, each of the at least one semiconductor die 700 includes a respective topmost die-internal dielectric material layer 760 that is dielectrically bonded to a topmost interposer dielectric material layer 460 of the interposer dielectric material layers. In an embodiment, the at least one semiconductor die 700 includes a plurality of semiconductor dies that are laterally separated from one another by the molded compound die frame portion 794; and the frame edge reinforcement structures 792 are entirely located outside of the interstitial regions between pairs of semiconductor dies 700 in plan view. In an embodiment, the frame edge reinforcement structures 792 have a height that is the same as a height of each of the at least one semiconductor die 700. In an embodiment, the frame edge reinforcement structures 792 have a height that is less than a height of each of the at least one semiconductor die 700.

[0156] According to another embodiment of the present disclosure, a semiconductor device structure is provided, the semiconductor device structure comprising: a silicon interposer comprising a silicon substrate, a through-silicon via structure provided within the silicon substrate, and an interposer dielectric material layer having an interposer metal interconnect structure and a die-side interposer bonding pad formed therein; a silicon interposer 400 comprising a silicon substrate 410, a through-silicon via structure 420 provided within the silicon substrate, and an interposer dielectric material layer 460 having an interposer metal interconnect structure 480 and a die-side interposer bonding pad 488 formed therein; at least one semiconductor die 700 comprising a die-internal bonding pad 788 bonded to the die-side interposer bonding pad 488; and a composite die frame 790 laterally surrounding the at least one semiconductor die 700 and including a molding compound die frame portion 794 comprising a molding compound material and a frame edge reinforcement structure 792 located at a corner of the composite die frame 790 and comprising a material having a coefficient of thermal expansion at 20 degrees Celsius that is lower than that of the molding compound material.

[0157] In one embodiment, the frame edge reinforcement structure 792 comprises a material selected from the group consisting of additional molding compound material, die attach film, epoxy material, underfill material, and semiconductor material. In one embodiment, at least one of the frame edge reinforcement structures 792 has an L-shaped horizontal cross-sectional shape. In one embodiment, at least one of the frame edge reinforcement structures 792 has a rectangular horizontal cross-sectional shape. In one embodiment, each of the at least one semiconductor die 700 comprises a respective set of semiconductor devices 720 and a respective die-internal dielectric material layer 760 having a die-internal metal interconnect structure 780 and the die-internal bonding pad 788 formed therein, wherein the die-internal bonding pad 788 is bonded to a respective one of the die-side interposer bonding pads 488 by a metal-to-metal bond.

[0158] According to yet another embodiment of the present disclosure, a method of forming a semiconductor device structure is provided, comprising: providing a structure comprising a silicon interposer 400 including a portion of a silicon substrate 410, a through-silicon via structure 420 provided within the silicon substrate 410, and an interposer dielectric material layer 460 having an interposer metal interconnect structure 480 and a die-side interposer bonding pad 488 formed therein; bonding at least one semiconductor die 700 including a die-internal bonding pad 788 to the silicon interposer 400 to bond the die-internal bonding pad 788 to the die-side interposer bonding pad 488; and forming a composite die frame 790 surrounding the at least one semiconductor die 700, wherein the composite die frame 790 includes a mold compound die frame portion 794 comprising a mold compound material and a frame edge strengthening structure 792 located at a corner of the composite die frame 790 and comprising a material having a coefficient of thermal expansion at 20 degrees Celsius that is lower than the mold compound material.

[0159] In an embodiment, the structure includes a two-dimensional array of silicon interposers 400 including the silicon interposer 400; and the method of forming a semiconductor device structure includes disposing a frame edge strengthening structure 792' in a process surrounding the at least one semiconductor die 700, and singulating the frame edge strengthening structure 792' in the process with the silicon substrate 410, wherein the singulated portion of the frame edge strengthening structure 792 in the process comprises the frame edge strengthening structure 792. In an embodiment, the frame edge strengthening structure 792' in the process is disposed directly on a top surface of the interposer dielectric material layer 460. In an embodiment, the method of forming a semiconductor device structure further includes forming a mold compound material layer 794' comprising the mold compound material surrounding the at least one semiconductor die 700 and the frame edge strengthening structure 792' in the process, wherein the mold compound die frame portion 794 comprises the singulated portion of the mold compound material. In an embodiment, the die-internal bonding pad 788 is bonded to the die-side interposer bonding pad 488 by metal-to-metal bonding; and each of the at least one semiconductor die 700 includes a respective die-internal dielectric material layer 760 bonded to a topmost one of the interposer dielectric material layers 460 by dielectric-to-dielectric bonding.

[0160] Various embodiments of the present disclosure can be used to reduce the effective coefficient of thermal expansion of a die frame that laterally surrounds at least one semiconductor die 700. The coefficient of thermal expansion of the silicon interposer 400 is lower than the coefficient of thermal expansion of the molding compound material, and a mismatch in the coefficient of thermal expansion between the die frame and the silicon interposer 400 can cause cracking in the molding compound material. A composite die frame 790 that includes a molding compound die frame portion 794 and a frame edge stiffening structure 792 having a lower coefficient of thermal expansion can reduce the overall coefficient of thermal expansion at the corners of the composite die frame 790 and can thereby inhibit or reduce cracking in the composite die frame 790.

[0161] The components of the above summary of several embodiments are set forth in order to provide a thorough understanding of the concepts of the present disclosure to one skilled in the art. Unless otherwise expressly provided in the text, no combination of the described embodiments is essential to the practice of the present disclosure. Each of the described embodiments using the term "comprising" is also implicitly disclosed in the description using the term "consisting essentially of" or "consisting of" in order to provide a thorough and enabling disclosure of the present disclosure. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference. Each of the patent or application documents identified in the Description of Related Art is incorporated herein by reference.

Claims

1. A semiconductor device structure, characterized by, including: an interposer comprising a plurality of interposer dielectric material layers having a plurality of interposer metal interconnect structures and a plurality of die side interposer bonding pads formed therein; at least one semiconductor die, each of the at least one semiconductor die comprising a respective set of semiconductor devices and a respective intra-die dielectric material layer having a plurality of intra-die metal interconnect structures and a plurality of intra-die bonding pads formed therein, wherein the intra-die bonding pads are bonded to respective ones of the die side interposer bonding pads by metal-to-metal bonding; and a composite die frame laterally surrounding the at least one semiconductor die and contacting a horizontal surface of one of the interposer dielectric material layers, wherein the composite die frame comprises a mold compound die frame portion comprising a mold compound material and a plurality of frame edge reinforcement structures at corners of the composite die frame, the frame edge reinforcement structures comprising a material having a coefficient of thermal expansion at 20 degrees Celsius that is lower than the mold compound material.

2. The semiconductor device structure of claim 1, wherein, one of the frame edge reinforcement structures comprises at least one exterior sidewall surface that is physically exposed to a vapor phase environment.

3. The semiconductor device structure of claim 1 or 2, wherein, one of the frame edge reinforcement structures comprises at least one interior sidewall surface that is in direct contact with the at least one semiconductor die.

4. The semiconductor device structure of claim 1, wherein, one of the frame edge reinforcement structures comprises a proximal horizontal surface that is in direct contact with a horizontal surface of the interposer dielectric material layer.

5. The semiconductor device structure of claim 1, wherein, one of the frame edge reinforcement structures comprises a distal horizontal surface that is in direct contact with a horizontal surface of the mold compound die frame portion.

6. The semiconductor device structure of claim 1, wherein, one of the frame edge reinforcement structures comprises a pair of vertically extending sidewalls that are in direct contact with vertical surfaces of the mold compound die frame portion.

7. The semiconductor device structure of claim 1, wherein: the at least one semiconductor die comprises a plurality of semiconductor dies that are laterally separated from one another by the mold compound die frame portion; and the frame edge reinforcement structures are entirely located outside of a region of the gap between pairs of the semiconductor dies in a plan view perspective.

8. The semiconductor device structure of claim 1, wherein, a height of the frame edge reinforcement structures is less than a height of the at least one semiconductor die.

9. A semiconductor device structure, characterized by, including: a silicon interposer comprising a silicon substrate, a plurality of through-silicon via structures provided within the silicon substrate, and a plurality of interposer dielectric material layers having a plurality of interposer metal interconnect structures and a plurality of die side interposer bonding pads formed therein; at least one semiconductor die comprising a plurality of intra-die die bonding pads bonded to the die side interposer bonding pads; and a composite die frame laterally surrounding the at least one semiconductor die and contacting a horizontal surface of one of the interposer dielectric material layers, wherein the composite die frame comprises a mold compound die frame portion comprising a mold compound material and a plurality of frame edge reinforcement structures at corners of the composite die frame, the frame edge reinforcement structures comprising a material having a coefficient of thermal expansion at 20 degrees Celsius that is lower than the mold compound material. A composite die frame laterally surrounding the at least one semiconductor die and including a molded plastic die frame portion comprising a molded plastic material and a plurality of frame edge reinforcement structures located at corners of the composite die frame and comprising a material having a coefficient of thermal expansion at 20 degrees Celsius that is lower than the molded plastic material.

10. The semiconductor device structure of claim 9, wherein, At least one of the frame edge reinforcement structures has an L-shaped horizontal cross-sectional shape.

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