Integrated circuit package

Abstract

The utility model relates to an integrated circuit package. The lead frame includes a first lead and a second lead, wherein each of the first lead and the second lead has an upper surface. A first silver point and a second silver point are provided on an upper surface of each of the first lead and the second lead. The integrated circuit die has a front surface including a first interconnect pad and a second interconnect pad. A first pillar is mounted for each of the first interconnect pads, and a second pillar is mounted for each of the second interconnect pads. The integrated circuit die is mounted to the lead frame in a flip-chip orientation with the first pillar soldered to the first silver point and the second pillar soldered to the second silver point. The resin body encapsulates the integrated circuit die mounted to the lead frame.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to packaging for integrated circuit devices, and in particular to quad flat no-lead (QFN) packages that support integrated circuit dies in flip-chip orientation with different sizes of stud bumps mounted to a leadframe. BACKGROUND

[0002] Semiconductor fabrication technology is used to form multiple integrated circuits on a wafer of semiconductor material using well-known front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. Once the wafer of semiconductor material is processed, the processed wafer is singulated into individual integrated circuit devices (each such device is also referred to in the art as an integrated circuit (IC) die) using a singulation process. Each individual integrated circuit device is then packaged by attaching the IC die to a leadframe and then encapsulating the IC die and leadframe in a resin body.

[0003] Different types of packages are known in the art. Of particular interest is the quad flat no-lead (QFN) package, which is well suited for surface mount installation. A QFN package has a small square or rectangular resin body without leads. In this context, "no leads" means that the electrode contacts of the packaged device do not extend away from the resin body.

[0004] Figure 1 A cross-sectional view of a conventional QFN packaged integrated circuit device 10 is illustrated. A leadframe 12 includes a die pad 12a and a plurality of leads 12b arranged around the die pad. A back surface of an integrated circuit die 14 is mounted to an upper surface of the die pad 12a using a die attach material (e.g., a die attach film (DAF), other adhesive, or soldering - not explicitly shown). A front surface of the integrated circuit die 14 includes interconnect pads 16 that are generally arranged adjacent to a peripheral edge of the die. These interconnect pads 16 are electrically connected to circuitry integrated on a semiconductor substrate of the die through an interconnect network (including, for example, a redistribution layer (RDL) and metallization layers). Electrical connection of the interconnect pads 16 to the leads 12b is made through bond wires 18. The integrated circuit die 14 mounted to the die pad 12a and electrically connected to the leads 12b is then encapsulated in a resin body 20. A bottom surface of the die pad 12a is exposed at a bottom surface of the resin body (e.g., to act as a heat conductor or heat sink). In addition, bottom surfaces of the leads 12b are exposed at the bottom surface of the resin body, and side surfaces of the leads 12b are exposed at the sides of the resin body to support surface mounting of the packaged IC die to a support substrate such as a printed circuit board (PCB). SUMMARY

[0005] In an embodiment, an integrated circuit package comprises: a leadframe comprising a first plurality of leads and a second plurality of leads, wherein each lead of the first and second plurality of leads has an upper surface; at least one first silver dot on the upper surface of each lead of the first plurality of leads, wherein each first silver dot has a first size and a first shape in a plan view; at least one second silver dot on the upper surface of each lead of the second plurality of leads, wherein each second silver dot has a second size and a second shape in a plan view; an integrated circuit die having a front surface comprising a first plurality of interconnect pads and a second plurality of interconnect pads; a first stud mounted to each interconnect pad of the first plurality of interconnect pads, wherein the first stud has a third size and a third shape in a plan view; a second stud mounted to each interconnect pad of the second plurality of interconnect pads, wherein the second stud has a fourth size and a fourth shape in a plan view; wherein the integrated circuit die is mounted to the leadframe in a flip chip orientation, wherein the first stud is soldered to the first silver dot and the second stud is soldered to the second silver dot; and a resin body encapsulating the integrated circuit die mounted to the leadframe.

[0006] In an embodiment, a layer of non-solder wettable material (such as, for example, an oxide) is present on the upper surface of each lead of the first and second plurality of leads, the layer of non-solder wettable material surrounding the first and second silver dots.

[0007] In an embodiment, the first and second plurality of leads provide electrode contacts for a flat no-lead type package.

[0008] In an embodiment, the integrated circuit package further comprises a non-solder wetting layer on the upper surface of each lead of the first and second plurality of leads, the non-solder wetting layer surrounding the first and second silver dots.

[0009] In an embodiment, the non-solder wetting layer is an oxide layer.

[0010] In an embodiment, the oxide layer is a brown oxide layer.

[0011] In an embodiment, for a flat no-lead type package, the first plurality of leads provide electrode contacts on the sides and bottom of the resin body.

[0012] In an embodiment, for a flat no-lead type package, the second plurality of leads provide electrode contacts on the sides and bottom of the resin body.

[0013] In an embodiment, the first size is greater than the third size and the first shape is the same as the third shape.

[0014] In an embodiment, the first size is greater than the third size and the first shape is different than the third shape.

[0015] In an embodiment, the second size is greater than the fourth size and the second shape is the same as the fourth shape.

[0016] In an embodiment, the second size is greater than the fourth size and the second shape is different than the fourth shape.

[0017] In an embodiment, the second plurality of leads includes segmented leads extending longitudinally in a first direction between opposing first and second sides of the resin body, wherein the first and second sides extend in a second direction perpendicular to the first direction.

[0018] In an embodiment, the resin body further includes opposing third and fourth sides extending in the first direction, and wherein the first plurality of leads includes end leads arranged in two groups, a first group of the two groups arranged along the third side and a second group of the two groups arranged along the fourth side.

[0019] In an embodiment, end surfaces of the segmented leads are exposed from the resin body at the first and second sides, and wherein end surfaces of the end leads are exposed from the resin body at the third and fourth sides.

[0020] In an embodiment, end surfaces of some of the end leads are exposed from the resin body at the first and second sides.

[0021] In an embodiment, the integrated circuit die further includes a third plurality of interconnect pads on the front surface, and further includes a third post mounted to each of the third plurality of interconnect pads, wherein at least one of a size and a shape of the third post is different than a corresponding size and shape of each of the first and second posts. BRIEF DESCRIPTION OF DRAWINGS

[0022] The foregoing and other features and advantages will be discussed in greater detail in the following non-limiting description of specific embodiments in conjunction with the attached drawings, in which:

[0023] Figure 1 illustrates a cross-sectional view of an integrated circuit device of a conventional QFN package;

[0024] Figure 2 illustrates a cross-sectional view of an integrated circuit device of a QFN package having a flip chip die;

[0025] Figure 3A illustrates a perspective view of a die using non-uniform sized posts;

[0026] Figure 3B and Figure 3C shows a side view of posts having different sizes;

[0027] Figure 4 illustrates a perspective view of a leadframe;

[0028] Figure 5A and Figure 5B Comparison of pillar and silver plated dot size and shape is illustrated in plan view;

[0029] Figure 5C and Figure 5D Comparison of pillar and silver plated dot size and shape is illustrated in plan view;

[0030] Figure 6 Illustrates a phantom perspective view of an integrated circuit device in a QFN package using a die with Figure 3A soldered to a leadframe with Figure 4 ;

[0031] Figure 7 Illustrates a cross-section of the connection of the die pillars to the leads of the leadframe; and

[0032] Figure 8A , Figure 8B and Figure 8C show cross-sectional images of the integrated circuit device. DETAILED DESCRIPTION

[0033] In the different drawings, identical elements are designated with identical reference numerals. In particular, structural and / or functional elements common to different embodiments can be designated with identical reference numerals and can have identical structure, dimensions, and material properties.

[0034] Throughout this disclosure, the term "connected" is used to designate a direct electrical connection between circuit elements, without intermediate elements other than conductors, while the term "coupled" is used to designate an electrical connection between circuit elements, which can be direct, or can be via one or more intermediate elements.

[0035] The terms "about", "substantially", and "approximately" are used herein to designate a tolerance of plus or minus 10% of the value in question, preferably plus or minus 5% of the value in question.

[0036] Reference is now made to Figure 2 , Figure 2A cross-sectional view of an integrated circuit device 110 is illustrated that has a QFN package with flip-chip die. The leadframe 112 includes a plurality of first (finger or segment) leads 112a and a plurality of second (end) leads 112b. The front surface of the integrated circuit die 114 includes die pillars 116 (also referred to in the art as bumps) that are mounted to interconnect pads 16. The interconnect pads 16 are electrically connected to circuitry integrated on the semiconductor substrate of the die through an interconnect network including, for example, a redistribution layer (RDL) and a metallization layer. The integrated circuit die 114 is mounted to the leadframe in a "flip-chip" orientation with the front surface of the integrated circuit die 114 facing the upper surface of the leadframe 112. The distal ends of the die pillars 116 are soldered to the upper surface of the leadframe. In particular, the ends of the die pillars 116 disposed adjacent to the peripheral edge of the die are soldered to the second leads 112b and the die pillars 116 disposed closer to the center of the die are soldered to the first leads 112a. The integrated circuit die 114 mounted to the leadframe in a flip-chip orientation is then encapsulated in a resin body 120 to form a packaged IC die. The bottom surfaces of the leads 112a are exposed at the bottom surface of the resin body and the end surfaces of the leads 112a are exposed at the side surfaces of the resin body. In addition, the bottom surfaces of the leads 112b are exposed at the bottom surface of the resin body and the side surfaces of the leads 112b are exposed at the side surfaces of the resin body.

[0037] The integrated circuit die can be designed to use different sizes of die pillars. Figure 3A A perspective view of an integrated circuit die 214 is illustrated that uses non-uniform sized pillars 216. The pillars 216 can include, for example, pillars 216a having a first size and shape (here shown as a circular shape having a first surface area in a plan view (i.e., facing the top)) and pillars 216b having a second size and shape (here shown as a stadium or racetrack or oval shape having a second surface area greater than the first surface area in a plan view (i.e., facing the top)). The pillars 216a having the first size and shape are disposed adjacent to the peripheral edge of the die while the pillars 216b having the second size and shape are disposed closer to the center on the die. This arrangement is merely an example and is not limiting and a designer can provide pillars of different sizes and shapes at desired locations. In addition, while two different shaped pillars are shown in the die 214 in a plan view, it is understood that an integrated circuit die can be designed to use many different shaped and sized die pillars (e.g., can include three or more differently sized and shaped pillars). As an example, but not by way of limitation, a first pillar having a stadium or racetrack or oval shape in a plan view, a second pillar that is circular in a plan view having a first surface area, and a third pillar that is circular in a plan view having a second surface area less than the first surface area can be included on a single die 214.

[0038] Figure 3BA side view of column 216a is shown and Figure 3C A side view of pillar 216b is shown. Each pillar 216 includes a base 230 made of copper, which is mounted to the surface 232 of the interconnect pad 16 of the integrated circuit device. The top of the base 230 is covered with solder 234. A thin nickel layer may be provided between the solder 234 and the top of the base 230. Considering that pillar growth is performed through an electroplating process, pillars with different shapes mean that different electroplating areas will be covered. Coupled with process variations, this can lead to poor pillar coplanarity, which affects the soldering quality between the pillar and the lead frame. Note the topological differences in pillar height, indicated by dotted lines. This topological difference can be a problem when mounting the integrated circuit die 214 to the lead frame in a flip-chip manner, as it increases the risk of cold joints forming between pillars 216a, pillars 216b and the lead frame. To mitigate this risk, it is proposed to form silver dots surrounded by a non-wetting layer on the lead frame. Both will enhance the solder joints between posts 216a and 216b and the lead frame.

[0039] Now for reference Figure 4 , Figure 4 A perspective view of a lead frame 212 is illustrated. The lead frame 212 is made of, for example, a copper sheet or copper alloy sheet, and is shaped by manufacturing processes such as stamping and etching to define a plurality of leads 214. The leads 214 may include a plurality of segmented (or fingered) leads 220 and a plurality of end leads 222. The segmented leads 220 and end leads 222 may have a semi-etched configuration known in the art to form an undercut region 227. It will be noted that, for simplicity, Figure 4 The illustration shows the lead frame 212 in the context of a single package.

[0040] Each segmented lead 220 extends longitudinally in the first direction (i.e., in its longer or length direction), and as... Figure 6 As shown, it extends between opposing first and second sides of the package (those first sides being perpendicular to the first direction). The longitudinal end surface of each segment lead 220 is exposed from the package at the first and second sides of the package.

[0041] The end leads 222 are arranged in two groups. The first group is laterally (i.e., in the width direction) located on one side of the segmented leads 220, while the second group is laterally (i.e., in the width direction) located on the opposite side of the segmented leads 220. The end surfaces of some end leads 222 are exposed from the package at the first and second sides of the package. The end surfaces of other end leads 222 are exposed from the package at the third and fourth sides of the package, which extend perpendicular to the first and second sides of the package.

[0042] Silver dots 226 are plated at specific locations on the upper surfaces of the segment leads 220 and the end leads 222. A photomask can be deposited on the surfaces of the leadframe leads 220, 222 and patterned to include openings for the dots 226 at the desired locations. An electrolytic growth process is then performed to plate the surfaces of the leadframe leads 220, 222 at the openings in the photomask and form the dots 226. The silver dots 226 can have a thickness in the range of 2.5 to 7.25 pm, for example. The portions of the upper surfaces of the segment leads 220 and the end leads 222 not covered by the silver-plated dots 226 are coated with a non-solder wetting layer 228. As an example, the layer 228 can include a thin brown oxide layer. The oxide layer can have a thickness in the range of 10-100 nanometers, for example. The brown oxide layer can be formed by a thermal oxidation process, a chemical process, or an electrochemical process, for example. Prior to performing the process for forming the non-solder wetting layer 228, the leadframe can be subjected to a fine etching process to provide surface roughness to support improved adhesion of the molding material to the leadframe.

[0043] The oxidation process that forms the layer 228 as a brown oxide layer can include a chemical interaction, for example, in which the leadframe is placed in a chemical bath in which the chemicals react with copper but do not react with the silver-plated dots 226. Prior to performing the chemical interaction, the other surfaces of the leadframe that are not desired to have the oxide layer can be covered with a mask.

[0044] Other processes can also be used to passivate the leadframe to obtain the non-solder wetting layer 228. Such processes include a chemical process, a heating process, and a sputtering process, for example.

[0045] When the integrated circuit die 214 is oriented in a flip-chip configuration and mounted to the leadframe 212, the locations of the silver-plated dots 226 on the upper surfaces of the segment leads 220 and the end leads 222 correspond to (i.e., align with or coincide with) the locations of the posts 216a, 216b, as shown in Figure 6 and Figure 7 The size and shape of the silver-plated dots 226 generally correspond to the size and shape of the posts 216a, 216b, such that during solder reflow, the solder material (e.g., Ag+ tin alloy) melts and assumes the shape of the silver dots. In a preferred implementation, the area of the dots 226 is slightly larger than the corresponding posts, to account for manufacturing tolerances and assembly tolerances. In particular, the size and shape of the silver-plated dots 226 correspond to the size and shape of the posts 216a, 216b (e.g., the circular shapes 240a and 242a, and the oval shapes 244a and 246a) shown in Figure 5A and Figure 5B Alternatively, the size and shape of the silver-plated dots 226 can differ slightly from the size and shape of the posts 216a, 216b. For example, as shown in Figure 5CAs shown in FIG. 8A, the silver plated dots 226a have a square shape with rounded corners in plan view (reference numeral 240b), while the posts 216a have a circular shape in plan view (reference numeral 242b). As another example, as shown in FIG. 8B, the silver plated dots 226b have a rectangular shape with rounded corners in plan view (reference numeral 244b), while the posts 216b have a stadium or racetrack or oval shape in plan view (reference numeral 246b). Figure 5D

[0046] Figure 6 The general outline of the resin body 250, which encapsulates the integrated circuit die 214 mounted to the leadframe 212 in flip-chip fashion, is also shown in dotted lines. The bottom surfaces 260 of the segment leads 220 and end leads 222 are exposed at the bottom surface of the resin body. In addition, the side edges 262 of the segment leads 220 and end leads 222 are exposed at the side surfaces of the resin body.

[0047] Figure 7 Cross-sections through the connections of the posts 216 with the leads 220, 222 of the leadframe are illustrated. Each silver plated dot 226 surrounded by the non-solder wicking layer 228 reduces the flow penetration of the solder 234 during reflow. Each silver plated dot 226 further improves the formation of the solder joints between the posts 216 and the leadframe.

[0048] Figure 8A Figure 8B Figure 8C Figure 4 Cross-sectional views of the integrated circuit device taken along dotted lines 8A, 8B and 8C in FIG. 8 are shown in FIGS. 9A, 9B and 9C, respectively. As shown, the restriction on solder flow penetration provided by the use of the silver plated dots 226 and the non-solder wicking layer 228 enables the post pitch distance to be reduced, so that a greater number of posts can be accommodated in the die design without increasing the die or overall package size.

[0049] While the application has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the application is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed application, from a study of the drawings, the disclosure, and the appended claims.​​​​

Claims

1. An integrated circuit package, characterized in that, include: A lead frame including a first plurality of leads and a second plurality of leads, wherein each of the first plurality of leads and the second plurality of leads has a top surface; At least one first silver dot on the upper surface of each of the first plurality of leads, wherein each first silver dot has a first size and a first shape in a plan view; At least one second silver dot on the upper surface of each of the second plurality of leads, wherein each second silver dot has a second size and a second shape in a plan view; An integrated circuit die having a front surface including a first plurality of interconnect pads and a second plurality of interconnect pads; A first pillar is mounted to each of the first plurality of interconnect pads, wherein the first pillar has a third dimension and a third shape in a plan view; The second pillar is mounted to each interconnect pad in the second plurality of interconnect pads, wherein the second pillar has a fourth dimension and a fourth shape in the plan view; The integrated circuit die is mounted to the lead frame with the flip chip orientation, wherein the first post is soldered to the first silver point and the second post is soldered to the second silver point; as well as A resin body that encapsulates and mounts an integrated circuit die to a lead frame.

2. The integrated circuit package as described in claim 1, characterized in that, It also includes a non-solder wetting layer on the upper surface of each of the first plurality of leads and the second plurality of leads, the non-solder wetting layer surrounding the first silver point and the second silver point.

3. The integrated circuit package as described in claim 2, characterized in that, The non-solder wetting layer is an oxide layer.

4. The integrated circuit package as described in claim 3, characterized in that, The oxide layer therein is a brown oxide layer.

5. The integrated circuit package as described in claim 1, characterized in that, In the case of a flat, leadless package, the first plurality of leads provide electrode contacts on the sides and bottom of the resin body.

6. The integrated circuit package as described in claim 1, characterized in that, In the case of a flat, leadless package, the second plurality of leads provide electrode contacts on the sides and bottom of the resin body.

7. The integrated circuit package as described in claim 1, characterized in that, The first dimension is larger than the third dimension, and the first shape is the same as the third shape.

8. The integrated circuit package as described in claim 1, characterized in that, The first dimension is larger than the third dimension, and the first shape is different from the third shape.

9. The integrated circuit package as described in claim 1, characterized in that, The second dimension is larger than the fourth dimension, and the second shape is the same as the fourth shape.

10. The integrated circuit package as described in claim 1, characterized in that, The second dimension is larger than the fourth dimension, and the second shape is different from the fourth shape.

11. The integrated circuit package as described in claim 1, characterized in that, The second plurality of leads include segmented leads extending longitudinally in a first direction between opposing first and second sides of the resin body, wherein the first and second sides extend in a second direction perpendicular to the first direction.

12. The integrated circuit package as described in claim 11, characterized in that, The resin body further includes opposing third and fourth sides extending in a first direction, and the first plurality of leads include end leads arranged in two groups, the first group being arranged along the third side and the second group being arranged along the fourth side.

13. The integrated circuit package as described in claim 12, characterized in that, The end surfaces of the segmented leads are exposed from the resin body on the first and second sides, and the end surfaces of the end leads are exposed from the resin body on the third and fourth sides.

14. The integrated circuit package as described in claim 13, characterized in that, Some of the end leads have their end surfaces exposed from the resin body on the first and second sides.

15. The integrated circuit package as described in claim 1, characterized in that, The integrated circuit die also includes a third plurality of interconnect pads on the front surface, and further includes a third pillar mounted to each of the third plurality of interconnect pads, wherein at least one of the dimensions and shapes of the third pillar is different from the corresponding dimensions and shapes of each of the first pillar and the second pillar.

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