Driving clamping circuit and vehicle-mounted power supply

Abstract

The utility model provides a drive clamping circuit and a vehicle-mounted power supply, the circuit comprises a drive module, a first resistor R1, a clamping module and a field effect transistor Q1, the clamping module comprises a first capacitor C1, a second triode Q2 and a first diode D1, the first end of the driving module is connected with the first end of the R1, the second end of the R1 is connected with the grid electrode of the Q1, the first end of the C1 is connected with the second end of the R1, the second end of the C1 is connected with the first end of the Q2, the second end of the Q2 is connected with the second end of the driving module, the third end of the Q2 is connected with the third end of the driving module, and the cathode of the D1 is connected with the second end of the C1. The anode of the D1 is connected with the source electrode of the Q1 and the third end of the driving module. Therefore, by adding a small number of devices, the influence of line inductance on the driving speed is reduced, the clamping effect is improved, and the turn-off reliability of the field effect transistor is improved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of power electronics, and particularly relates to a driving clamping circuit and a vehicle-mounted power supply. BACKGROUND

[0002] With the development of power electronics technology, as the core power conversion device of a power electronic converter, the stability of a driving circuit directly affects the reliability of the power electronic device, however, the Miller effect generated in the process of turning on or turning off of an SIC MOS tube seriously affects the reliability of the circuit.

[0003] At present, negative voltage turn-off can be generally used to cope with the Miller effect, however, due to the large size of the switching device in a high-power power electronic device, the line layout between the driving circuit and the power device leads to a large distance between the driving circuit and the power device, and in the process of driving a large current, the line inductance causes the driving speed to slow down, thereby the clamping effect is poor, and the reliability of the driving circuit is low. CONTENT OF THE INVENTION

[0004] The application provides a driving clamping circuit and a vehicle-mounted power supply, the influence of line inductance on the driving speed is reduced by adding a small number of devices, the clamping effect is improved, and therefore the reliability of the turn-off of the field effect tube is improved.

[0005] In a first aspect, an embodiment of the application provides a driving clamping circuit, comprising a driving module, a first resistor R1, a clamping module, and a field effect tube Q1, the clamping module comprises a first capacitor C1, a second triode Q2, and a first diode D1, wherein;

[0006] A first end of the driving module is connected with a first end of the first resistor R1, a second end of the first resistor R1 is connected with a gate of the field effect tube Q1, a first end of the first capacitor C1 is connected with a second end of the first resistor R1, a second end of the first capacitor C1 is connected with a first end of the second triode Q2, a second end of the second triode Q2 is connected with a second end of the driving module, a third end of the second triode Q2 is connected with a third end of the driving module, a cathode of the first diode D1 is connected with the second end of the first capacitor C1, and an anode of the first diode D1 is connected with a source of the field effect tube Q1 and the third end of the driving module respectively.

[0007] In a possible embodiment, the first end of the second triode Q2 is an emitter, the second end of the second triode Q2 is a base, and the third end of the second triode Q2 is a collector, or the first end of the second triode Q2 is a collector, the second end of the second triode Q2 is a base, and the third end of the second triode Q2 is an emitter.

[0008] In one possible embodiment, the driving module includes an amplifier U1A, a first parasitic line inductance L1, a second parasitic line inductance L2, a third transistor Q3, a second resistor R2, and a third resistor R3. The output terminal of the amplifier U1A is connected to the first terminal of the parasitic line inductance L1. The second terminal of the first parasitic line inductance L1 is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the base of the third transistor Q3. The emitter of the third transistor Q3 is connected to the first terminal of the first resistor R1. The collector of the third transistor Q3 is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the base of the second transistor Q2. The collector of the second transistor Q2 is connected to the first terminal of the second parasitic line inductance L2. The second terminal of the second parasitic line inductance L2 is connected to the positive power input terminal V of the amplifier U1A. CC and the negative input terminal of the power supply V EE Connected and grounded.

[0009] In one possible embodiment, the driving module includes an amplifier U1A, a first parasitic line inductance L1, a second parasitic line inductance L2, a third transistor Q3, a second resistor R2, and a third resistor R3. The output terminal of the amplifier U1A is connected to the first terminal of the parasitic line inductance L1. The second terminal of the first parasitic line inductance L1 is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the emitter of the third transistor Q3. The base of the third transistor Q3 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the first terminal of the first resistor R1. The collector of the third transistor Q3 is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the base of the second transistor Q2. The emitter of the second transistor Q2 is connected to the first terminal of the second parasitic line inductance L2. The second terminal of the second parasitic line inductance L2 is connected to the positive power input terminal V of the amplifier U1A. CC and the negative input terminal of the power supply V EE Connected and grounded.

[0010] In one possible embodiment, the positive power input terminal V of the amplifier U1A CC The circuit formed by the fourth capacitor C4 and the fifth capacitor C5 connected in series is connected to the negative input terminal V of the power supply. EE The second terminal of the parasitic inductance L2 of the second line is connected between the fourth capacitor C4 and the fifth capacitor C5.

[0011] In a possible embodiment, the driving module comprises a driving chip, a third line parasitic inductor L3, a fourth line parasitic inductor L4, and a fifth line parasitic inductor L5, a first port of the driving chip is connected with a first end of the third line parasitic inductor L3, a second end of the third line parasitic inductor L3 is connected with a first end of the first resistor R1, a second port of the driving chip is connected with a first end of the fourth line parasitic inductor L4, a second end of the fourth line parasitic inductor L4 is connected with a second end of the second transistor Q2, a third port of the driving chip is connected with a first end of the fifth line parasitic inductor L5, and a second end of the fifth line parasitic inductor L5 is connected with a third end of the second transistor Q2.

[0012] In a possible embodiment, the field effect transistor Q1 has a parasitic capacitor, the parasitic capacitor comprises a gate-drain parasitic capacitor C2 and a gate-source parasitic capacitor C3, a first end of the gate-drain parasitic capacitor C2 is connected with a first end of the first capacitor C1, a second end of the gate-drain parasitic capacitor C2 is connected with a drain of the field effect transistor Q1, a first end of the gate-source parasitic capacitor C3 is connected with a first end of the first capacitor C1, and a second end of the gate-source parasitic capacitor C3 is connected with a third end of the second transistor Q2 and a source of the field effect transistor Q1.

[0013] In a possible embodiment, a capacitance of the first capacitor C1 is greater than a capacitance of the gate-source parasitic capacitor C3.

[0014] In a possible embodiment, the driving clamp circuit further comprises a second diode D2, an anode of the second diode D2 is connected with a first end of the first resistor R1, and a cathode of the second diode D2 is connected with a second end of the first resistor R1.

[0015] In a possible embodiment, the driving clamp circuit further comprises a second diode D2, an anode of the second diode D2 is connected with a first end of the first resistor R1, and a cathode of the second diode D2 is connected with a second end of the first resistor R1.

[0016] It can be seen that, in the present application, by designing a clamp module with a small number of components between the driving module and the power switching device, the power switching device can be quickly turned off through the clamp module, the influence of line inductance on driving speed is reduced, the clamp effect is improved, and the reliability of the field effect transistor turn-off is improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0018] Figure 1 is a first structure schematic diagram of a driving clamp circuit provided by an embodiment of the present application;

[0019] Figure 2 is a second structure schematic diagram of a driving clamp circuit provided by an embodiment of the present application;

[0020] Figure 3 is a third structure schematic diagram of a driving clamp circuit provided by an embodiment of the present application;

[0021] Figure 4 is a fourth structure schematic diagram of a driving clamp circuit provided by an embodiment of the present application;

[0022] Figure 5 is a fifth structure schematic diagram of a driving clamp circuit provided by an embodiment of the present application;

[0023] Figure 6 is a sixth structure schematic diagram of a driving clamp circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0025] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0026] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor does it necessarily refer to a particular alternative embodiment. It is explicitly and implicitly understood that the embodiments described herein can be combined with other embodiments.

[0027] In the embodiments of the present application, the "and / or" describes the association relationship of the associated objects, and indicates that there can be three relationships. For example, A and / or B can represent the following three cases: A exists alone; A and B exist simultaneously; and B exists alone. Wherein, A and B can be singular or plural.

[0028] In the embodiments of the present application, the symbol " / " can represent that the associated objects before and after the symbol are in an "or" relationship. In addition, the symbol " / " can also represent the division symbol, that is, performing division operation. For example, A / B can represent A divided by B.

[0029] In the embodiments of the present application, "equal to" can be used with greater than, which is applicable to the technical solutions adopted when greater than, and can also be used with less than, which is applicable to the technical solutions adopted when less than. When "equal to" is used with greater than, it is not used with less than; when "equal to" is used with less than, it is not used with greater than.

[0030] In order to facilitate understanding of the present application, some names need to be explained.

[0031] Field effect tube: the abbreviation of field effect transistor, which belongs to power switching device, also known as unipolar transistor, is a kind of semiconductor device which controls the output loop current by using the electric field effect of the control input loop. In the present application, it can be specifically represented as MOS type field effect tube, that is, MOSFET.

[0032] Miller effect: the effect that the parasitic capacitance (gate-drain parasitic capacitance) between the input and output of MOSFET is amplified under the action of inverting amplifier.

[0033] Line parasitic inductance: refers to the inductance produced on the conductor, that is, the conductor itself has a certain inductance, and when the length of the conductor increases and the diameter decreases, the inductance value will increase.

[0034] PWM: the abbreviation of Pulse Width Modulation, which is a very effective technology for using digital output of microprocessor to control analog circuit.

[0035] With the development of power electronic technology, the third generation semiconductor device as the core power conversion device of power electronic converter, the stability of the driving circuit directly affects the reliability of the power electronic device, however, due to the Miller effect generated in the process of SIC MOS tube conduction or turn-off seriously affects the reliability of the circuit.

[0036] At present, negative pressure shutdown can be generally used to cope with the Miller effect, however, due to the large size of the switching device in the high-power power electronic device, the distance between the driving circuit and the power device is large due to the line layout between the driving circuit and the power device, and in the large current driving process, the line inductance causes the driving speed to slow down, so that the clamping effect is poor, and the reliability of the driving circuit is low.

[0037] To solve the above problems, the application provides a driving clamping circuit, and the embodiments of the application will be described in detail below with reference to the drawings.

[0038] Please refer to Figure 1 , Figure 1 is a first structure schematic diagram of a driving clamping circuit provided by the embodiments of the application. As shown in Figure 1 , the driving clamping circuit includes a driving module 110, a first resistor R1, a clamping module 120, and a field effect tube Q1, the clamping module 120 includes a first capacitor C1, a second triode Q2, and a first diode D1, wherein; the first end of the driving module 110 is connected with the first end of the first resistor R1, the second end of the first resistor R1 is connected with the gate of the field effect tube Q1, the first end of the first capacitor C1 is connected with the second end of the first resistor R1, the second end of the first capacitor C1 is connected with the first end of the second triode Q2, the second end of the second triode Q2 is connected with the second end of the driving module 110, the third end of the second triode Q2 is connected with the third end of the driving module 110, the cathode of the first diode D1 is connected with the second end of the first capacitor C1, and the anode of the first diode D1 is connected with the source of the field effect tube Q1 and the third end of the driving module 110 respectively.

[0039] Among them, the field effect tube Q1 can be MOSFET.

[0040] Among them, the first diode D1 can be a unidirectional diode, the first diode D1 is connected in parallel with the second triode Q2, and the current conduction direction of the second triode Q2 is opposite to the current conduction direction of the first diode D1, so that when the second triode Q2 is turned on, the first capacitor C1 can be discharged through the second triode Q2.

[0041] It can be seen that in the present example, by designing a clamping module with few devices between the driving module and the power switching device, the power switching device can be quickly turned off through the clamping module, the influence of line inductance on driving speed is reduced, the clamping effect is improved, and the reliability of the field effect tube turn-off is improved.

[0042] In a possible embodiment, the first end of the second triode Q2 is an emitter, the second end of the second triode Q2 is a base, and the third end of the second triode Q2 is a collector; or the first end of the second triode Q2 is a collector, the second end of the second triode Q2 is a base, and the third end of the second triode Q2 is an emitter.

[0043] Referring to Figure 2 , Figure 2 is a second structure diagram of a driving clamp circuit provided in an embodiment of the present application. As shown in Figure 2 , the emitter of the second triode Q2 is connected with the cathode of the first diode D1, the base of the second triode Q2 is connected with the second end of the driving module 110, and the collector of the second triode Q2 is connected with the anode of the first diode D1. The second triode Q2 is connected in parallel with the first diode D1, and the current conduction direction of the second triode Q2 is opposite to the current conduction direction of the first diode D1, that is, the current conduction direction of the second triode Q2 is from the emitter to the collector, and the current conduction direction of the first diode D1 is from the anode to the cathode. In this way, when the second triode Q2 is cut off, the two-terminal voltage between the gate and the source of the field effect tube Q1 can flow to the two terminals of the first capacitor C1 through the first diode D1, and when the second triode Q2 is turned on, the first capacitor C1 can be discharged through the second triode Q2.

[0044] Referring to Figure 3 , Figure 3 is a third structure diagram of a driving clamp circuit provided in an embodiment of the present application. As shown in Figure 3 , the collector of the second triode Q2 is connected with the cathode of the first diode D1, the base of the second triode Q2 is connected with the second end of the driving module 110, and the emitter of the second triode Q2 is connected with the anode of the first diode D1. The second triode Q2 is connected in parallel with the first diode D1, and the current conduction direction of the second triode Q2 is opposite to the current conduction direction of the first diode D1, that is, the current conduction direction of the second triode Q2 is from the collector to the emitter, and the current conduction direction of the first diode D1 is from the anode to the cathode. In this way, when the second triode Q2 is cut off, the two-terminal voltage between the gate and the source of the field effect tube Q1 can flow to the two terminals of the first capacitor C1 through the first diode D1, and when the second triode Q2 is turned on, the first capacitor C1 can be discharged through the second triode Q2.

[0045] It can be seen that, in the present example, the clamp module composed of the first diode D1, the second triode Q2, and the first capacitor C1 is designed between the driving module and the field effect tube, so that the discharging speed of the field effect tube is accelerated, the influence of the line inductance on the driving speed is reduced, the clamp effect is improved, and thus the reliability of the field effect tube turn-off is improved.

[0046] In one possible embodiment, please refer to Figure 4 , Figure 4 is a fourth structure diagram of a driving clamp circuit provided by the embodiment of the present application. As shown in Figure 4 , the driving module 110 can include an amplifier U1A, a first line parasitic inductor L1, a second line parasitic inductor L2, a third transistor Q3, a second resistor R2, and a third resistor R3, the output end of the amplifier U1A is connected with the first end of the first line parasitic inductor L1, the second end of the first line parasitic inductor L1 is connected with the first end of the first resistor R1, the second end of the first resistor R1 is connected with the first end of the second resistor R2, the second end of the second resistor R2 is connected with the base of the third transistor Q3, the emitter of the third transistor Q3 is connected with the first end of the first resistor R1, the collector of the third transistor Q3 is connected with the first end of the third resistor R3, the second end of the third resistor R3 is connected with the base of the second transistor Q2, the collector of the second transistor Q2 is connected with the first end of the second line parasitic inductor L2, and the second end of the second line parasitic inductor L2 is connected with the positive power input end V CC and the negative power input end V EE of the amplifier U1A and grounded.

[0047] When the driving module 110 is turned on, i.e. the working period of the driving clamp circuit is negative voltage off, the BE junction of the third transistor Q3 is reverse biased, i.e. the base voltage is less than the emitter voltage, the third transistor Q3 is cut off, the second transistor Q2 is cut off, and there is a negative voltage between the gate and the source of the field effect transistor Q1, and the negative voltage can make the first capacitor C1 store a certain negative voltage through the first diode D1, and the voltage of the first capacitor C1 is negative on the top and positive on the bottom.

[0048] Further, when the field effect transistor Q1 is turned off, the output voltage of the output end of the amplifier U1A is reduced, the third transistor Q3 is turned on, and the second transistor Q2 is turned on, so as to accelerate the turn-off of the field effect transistor Q1.

[0049] When the driving module 110 is switched from on to off, the output voltage of the amplifier U1A starts to decrease, and the voltage across the first resistor R1 is left negative and right positive due to the off current, which causes the BE junction of the third transistor Q3 to be positively biased, i.e., the base voltage is greater than the emitter voltage, so that the third transistor Q3 enters the conducting state; the base of the second transistor Q2 is connected to the output terminal of the amplifier U1A through the third resistor R3 and the third transistor Q3, and the BE junction of the second transistor Q2 is reversely biased, i.e., the base voltage is less than the emitter voltage, so that the second transistor Q2 enters the conducting state; the voltage across the first capacitor C1 is opposite in polarity to the voltage across the gate-source parasitic capacitor C3, and the loop of the first capacitor C1 and the second transistor Q2 is very close to the loop between the gate and the source of the field effect transistor Q1, so that the field effect transistor Q1 can be quickly turned off by the clamping module, i.e., the gate-source parasitic capacitor C3 can be discharged through the first capacitor C1 and the second transistor Q2, which greatly speeds up the discharging speed of the gate-source parasitic capacitor C3, and further speeds up the turn-off speed of the field effect transistor Q1.

[0050] Further, after the field effect transistor Q1 is turned off, the third transistor Q3 is cut off, and the second transistor Q2 is cut off, and the amplifier U1A is used to charge the first capacitor C1.

[0051] When the field effect transistor Q1 is turned off, the third transistor Q3 and the second transistor Q2 successively exit the conducting state, and under the action of the first diode D1, the driving negative voltage can continue to charge the first capacitor C1, thereby ensuring the stable voltage across the first capacitor C1, and storing energy for the next quick turn-off.

[0052] It should be noted that, in a bridge application, when the opposite tube of the field effect transistor Q1 is turned on, the drain voltage of the field effect transistor Q1 rapidly rises, the gate-drain parasitic capacitor C2 of the field effect transistor Q1 is rapidly charged, and a Miller voltage will be generated between the gate and the source of the field effect transistor Q1, i.e., there is a Miller voltage across the gate-source parasitic capacitor C3, which causes the field effect transistor Q1 to be turned on again, increases the loss of the field effect transistor Q1, and brings the risk of common conduction. Figure 4 When the voltage across the gate-source parasitic capacitor C3 is increased due to the Miller effect, the left-negative and right-positive voltage across the first resistor R1 will be generated again due to the off current of the driving module 110, the third transistor Q3 is driven to enter the conducting state again, and the second transistor Q2 also enters the conducting state again, so that the Miller voltage across the gate-source parasitic capacitor C3 of the field effect transistor Q1 is clamped on the voltage across the first capacitor C1 again, thereby realizing the function of negative voltage clamping, avoiding the secondary turn-on caused by the Miller effect, reducing the loss and the risk of common conduction of the field effect transistor Q1, and improving the reliability of the driving clamping circuit.

[0053] It can be seen that in the present example, the drive clamping circuit enables the field effect tube Q1 to be quickly turned off under the joint action of the drive module and the clamping module, reduces the influence of the line inductance on the driving speed, improves the clamping effect, thereby improving the reliability of the field effect tube Q1 to be turned off, and does not need to connect the positive and negative power supply to the vicinity of the field effect tube Q1, simplifies the complexity of the circuit wiring, and improves the reliability and stability of the negative voltage turn-off.

[0054] In one possible embodiment, referring to Figure 5 , Figure 5 is a fifth structural schematic diagram of a drive clamping circuit provided by the present application. As shown in Figure 5 , the drive module 110 includes an amplifier U1A, a first line parasitic inductance L1, a second line parasitic inductance L2, a third triode Q3, a second resistor R2, and a third resistor R3, the output end of the amplifier U1A is connected with the first end of the line parasitic inductance L1, the second end of the first line parasitic inductance L1 is connected with the first end of the first resistor R1, the second end of the first resistor R1 is connected with the emitter of the third triode Q3, the base of the third triode Q3 is connected with the first end of the second resistor R2, the second end of the second resistor R2 is connected with the first end of the first resistor R1, the collector of the third triode Q3 is connected with the first end of the third resistor R3, the second end of the third resistor R3 is connected with the base of the second triode Q2, the emitter of the second triode Q2 is connected with the first end of the second line parasitic inductance L2, and the second end of the second line parasitic inductance L2 is respectively connected with the positive power supply input end V CC and the negative power supply input end V EE of the amplifier U1A and grounded.

[0055] When the drive module 110 is turned on, that is, the working period of the drive clamping circuit is negative voltage turn-off, the BE junction of the third triode Q3 is positively biased, that is, the base voltage is greater than the emitter voltage, the third triode Q3 is cut off, the second triode Q2 is cut off, and there is a negative voltage between the gate and the source of the field effect tube Q1, and the negative voltage can make the first capacitor C1 store a certain negative voltage through the first diode D1, and the voltage of the first capacitor C1 is positive at the top and negative at the bottom.

[0056] Further, when the field effect tube Q1 is turned off, the output voltage of the output end of the amplifier U1A is reduced, the third triode Q3 is turned on, and the second triode Q2 is turned on, so as to accelerate the turn-off of the field effect tube Q1.

[0057] When the driving module 110 is switched from on to off, the output voltage of the amplifier U1A starts to decrease, and the voltage across the first resistor R1 is left negative and right positive due to the off current, which reverses the BE junction of the third transistor Q3, i.e. the base voltage is less than the emitter voltage, so the third transistor Q3 enters the conducting state; the base of the second transistor Q2 is connected to the output of the amplifier U1A through the third resistor R3 and the third transistor Q3, and the BE junction of the second transistor Q2 is forward biased, i.e. the base voltage is greater than the emitter voltage, so the second transistor Q2 enters the conducting state; the voltage across the first capacitor C1 is opposite in polarity to the voltage across the gate-source parasitic capacitor C3, and the loop of the first capacitor C1 and the second transistor Q2 is very close to the loop between the gate and the source of the field effect transistor Q1, so the field effect transistor Q1 can be quickly turned off by the clamping module, i.e. the gate-source parasitic capacitor C3 can be discharged through the first capacitor C1 and the second transistor Q2, which greatly speeds up the discharging speed of the gate-source parasitic capacitor C3, and further speeds up the turn-off speed of the field effect transistor Q1.

[0058] Further, after the field effect transistor Q1 is turned off, the third transistor Q3 is turned off, the second transistor Q2 is turned off, and the amplifier U1A is used to charge the first capacitor C1.

[0059] When the field effect transistor Q1 is turned off, the third transistor Q3 and the second transistor Q2 successively exit the conducting state, and under the action of the first diode D1, the driving negative voltage can continue to charge the first capacitor C1, thereby ensuring the stable voltage across the first capacitor C1 to store energy for the next quick turn-off.

[0060] It should be noted that in a bridge application, when the opposite tube of the field effect transistor Q1 is turned on, the drain voltage of the field effect transistor Q1 rapidly rises, the gate-drain parasitic capacitor C2 of the field effect transistor Q1 is rapidly charged, and a Miller voltage will be generated between the gate and the source of the field effect transistor Q1, i.e. there is a Miller voltage across the gate-source parasitic capacitor C3, which causes the field effect transistor Q1 to be turned on again, increases the loss of the field effect transistor Q1, and brings the risk of common conduction. Figure 5 When the voltage across the gate-source parasitic capacitor C3 rises due to the Miller effect, the left negative and right positive voltage across the first resistor R1 will be generated again due to the off current of the driving module 110, the third transistor Q3 enters the conducting state again, and the second transistor Q2 also enters the conducting state again, so that the Miller voltage across the gate-source parasitic capacitor C3 of the field effect transistor Q1 is clamped to the voltage across the first capacitor C1 again, thereby achieving the function of negative voltage clamping, avoiding the secondary turn-on caused by the Miller effect, reducing the loss and the risk of common conduction of the field effect transistor Q1, and improving the reliability of the driving clamping circuit.

[0061] It can be seen that in the present example, the drive clamping circuit makes the field effect tube Q1 quickly turn off under the joint action of the drive module and the clamping module, reduces the influence of the line inductance on the driving speed, improves the clamping effect, thereby improving the reliability of the field effect tube Q1 turning off, and does not need to connect the positive and negative power supplies to the vicinity of the field effect tube Q1, simplifies the complexity of the circuit wiring, and improves the reliability and stability of the negative voltage turn-off.

[0062] In one possible embodiment, as shown in Figure 4 or Figure 5 , the power supply positive input end V CC of the amplifier U1A is connected to the power supply negative input end V EE , and the second end of the second line parasitic inductance L2 is connected between the fourth capacitor C4 and the fifth capacitor C5.

[0063] Among them, the fourth capacitor C4 and the fifth capacitor C5 can be capacitors with different capacitance values. Specifically, the capacitance values of the fourth capacitor C4 and the fifth capacitor C5 can be designed independently, which is used to achieve a specific frequency response and filtering effect, and in addition, it can improve the output stability of the amplifier U1A.

[0064] It can be seen that in the present example, the capacitors in series are arranged between the power supply positive input end and the power supply negative input end of the amplifier U1A, which achieves the frequency response and filtering effect and improves the output stability of the amplifier U1A, thereby helping the control module to control the clamping function of the clamping module.

[0065] In one possible embodiment, please refer to Figure 6 , Figure 6 is a sixth structural schematic diagram of a drive clamping circuit provided by the embodiment of the present application. As shown in Figure 6 , the drive module 110 includes a drive chip 1121, a third line parasitic inductance L3, a fourth line parasitic inductance L4, and a fifth line parasitic inductance L5, the first port of the drive chip 1121 is connected with the first end of the third line parasitic inductance L3, the second end of the third line parasitic inductance L3 is connected with the first end of the first resistor R1, the second port of the drive chip 1121 is connected with the first end of the fourth line parasitic inductance L4, the second end of the fourth line parasitic inductance L4 is connected with the second end of the second transistor Q2, the third port of the drive chip 1121 is connected with the first end of the fifth line parasitic inductance L5, and the second end of the fifth line parasitic inductance L5 is connected with the third end of the second transistor Q2.

[0066] Among them, the driver chip 1121 can be a chip with built-in clamping function. There are various models of driver chip 1121, such as BTD25350, UCC21750, SiLM8260ABCS-DG, etc.

[0067] The first port of the driver chip 1121 can be Figure 6 The Vo port in the circuit is used to output a signal to control the on or off state of the field-effect transistor Q1; the second port of the driver chip 1121 can be... Figure 6 The Clamp port in the driver chip 1121 is used to output a CLAMP signal to control the clamping function of the driver chip 1121; the third port of the driver chip 1121 can be... Figure 6 The GND2 port is used for grounding to ensure the safety of the driver chip 1121. It should be noted that the CLAMP signal can be the opposite of the input signal; that is, if the input signal is high, the CLAMP signal is low; and vice versa.

[0068] Among them, such as Figure 6 As shown, the driver chip 1121 may also include a VCC2 port, a VCC1 port, an IN port, a VEE port, and a GND1 port. The VCC1 and VCC2 ports can be positive power supply input terminals, used to provide positive voltage to the driver chip 1121. The IN port can be a pulse signal input terminal, used to receive control pulse signals from the main controller or other input sources. Specifically, it can be used to receive PWM signals. The duty cycle of each cycle in the PWM signal may be the same or different, and its setting method can be selected by the user's own preference. The VEE port can be a negative power supply input terminal, used to provide negative voltage to the driver chip 1121. The GND1 port can be a ground port, used to provide a common reference point or ground for the internal circuitry of the driver chip 1121.

[0069] Inside the driver chip 1121, the Vo port is connected to the VEE port to achieve negative pressure shutdown, and the Clamp port is connected to the VEE port.

[0070] The CLAMP signal can be divided into an action signal and a non-action signal, and the action signal can control the second triode Q2 to be turned off, and the non-action signal can control the second triode Q2 to be turned on. When the driving chip 1121 is in an off state, the inside of the driving chip 1121 connects the Vo port to the VEE port to realize negative voltage turn-off, that is, during the turn-off period, the CLAMP signal output by the Clamp port of the driving chip is the action signal, there is negative voltage between the gate and the source of the field effect tube Q1, and the negative voltage can make the first capacitor C1 store a certain negative voltage between the two ends of the first capacitor C1, and the voltage of the first capacitor C1 is positive at the top and negative at the bottom. After the field effect tube Q1 is turned off, the CLAMP signal output by the Clamp port of the driving chip 1121 is the non-action signal, and the inside of the driving chip 1121 connects the Clamp port to the VEE port. Since the inside of the driving chip 1121 connects the Vo port to the VEE port, it is equivalent to connecting the Clamp port to the Vo port. At this time, due to the voltage of the first capacitor C1 being positive at the top and negative at the bottom, a reverse bias voltage is applied to the BE junction of the second triode Q2, that is, the base voltage is less than the emitter voltage, the second triode Q2 is turned on, and the first capacitor C1 and the second triode Q2 are connected in series and then connected in parallel between the gate and the source of the field effect tube Q1. The polarities of the voltage between the two ends of the first capacitor C1 and the voltage between the two ends of the gate-source parasitic capacitor C3 are opposite, the gate-source parasitic capacitor C3 can be discharged through the first capacitor C1 and the second triode Q2, greatly accelerating the discharging speed of the gate-source parasitic capacitor C3, and further accelerating the turn-off speed of the field effect tube Q1.

[0071] The capacitance of the first capacitor C1 can be selected to be relatively large, so that the Miller effect can be inhibited, and the switching speed is not affected.

[0072] It should be noted that in the bridge application, when the field effect tube Q1 is turned on, the drain voltage of the field effect tube Q1 rises rapidly, the gate-drain parasitic capacitor C2 and the gate-source parasitic capacitor C3 of the field effect tube Q1 are rapidly charged, and the Miller voltage will be generated between the gate and the source of the field effect tube Q1, causing the field effect tube Q1 to be turned on again, increasing the loss of the field effect tube Q1, and increasing the risk of common. Figure 6 When the voltage between the two ends of the gate-source parasitic capacitor C3 rises due to the Miller effect, the CLAMP signal output by the Clamp port of the driving chip 1121 is the action signal, the voltage between the two ends of the first capacitor C1 is positive at the top and negative at the bottom, and the second triode Q2 is turned on again to clamp the GS voltage of the field effect tube Q1 on the first capacitor C1, realizing effective negative voltage clamping function, avoiding the second turn-on caused by the Miller effect, reducing the loss of the field effect tube Q1 and the risk of common, and improving the reliability of the driving clamping circuit.

[0073] It can be seen that in the present example, the drive clamping circuit enables the field effect tube Q1 to be quickly turned off under the joint action of the drive module and the clamping module, reduces the influence of the line inductance on the driving speed, improves the clamping effect, thereby improving the reliability of the field effect tube Q1 turning off, and does not need to connect the positive and negative power supply to the vicinity of the field effect tube Q1, simplifies the complexity of the circuit wiring, and improves the reliability and stability of the negative voltage turning off.

[0074] In a possible embodiment, the field effect tube Q1 has a parasitic capacitance, such as Figures 1-6 As shown, the parasitic capacitance includes a gate-drain parasitic capacitance C2 and a gate-source parasitic capacitance C3, a first end of the gate-drain parasitic capacitance C2 is connected with a first end of the first capacitor C1, a second end of the gate-drain parasitic capacitance C2 is connected with a drain of the field effect tube Q1, a first end of the gate-source parasitic capacitance C3 is connected with the first end of the first capacitor C1, and a second end of the gate-source parasitic capacitance C3 is connected with a third end of the second triode Q2 and a source of the field effect tube Q1.

[0075] Wherein, the gate-drain parasitic capacitance C2 can be a parasitic capacitance between the gate and the drain of the field effect tube Q1, the gate-source parasitic capacitance C3 can be a parasitic capacitance between the gate and the source of the field effect tube Q1, and the voltage across the gate-drain parasitic capacitance C2 and the gate-source parasitic capacitance C3 is the voltage for driving the turn-on, which is generally 15V-20V. When the field effect tube Q1 turns off, the drain voltage of the field effect tube Q1 begins to drop, the gate-source parasitic capacitance C3 discharges, and a Miller voltage will be generated between the gate and the source of the field effect tube Q1, causing the turn-off time of the field effect tube Q1 to be prolonged and the loss of the field effect tube Q1 to be increased. When the drive module 110 controls the second triode Q2 to be turned off, the voltage between the gate and the source of the field effect tube Q1 can be clamped on the voltage across the first capacitor C1. Since the loop distance between the drive module 110 and the gate and the source of the field effect tube Q1 is very short, when the drive module 110 controls the first diode D1 to be turned on, the discharging speed of the gate-source parasitic capacitance C3 is accelerated, and the turn-off process of the field effect tube Q1 is accelerated.

[0076] In this way, under the joint action of the drive module and the clamping module, the parasitic capacitance can be quickly discharged through the connection relationship between the parasitic capacitance and the clamping module, so that the field effect tube Q1 can be quickly turned off, the influence of the line inductance on the driving speed is reduced, the clamping effect is improved, and the reliability of the field effect tube turning off is improved.

[0077] In a possible embodiment, the capacitance of the first capacitor C1 is greater than the capacitance of the gate-source parasitic capacitance C3.

[0078] Wherein, during the process of turning off the field effect tube Q1, the voltage of the gate-source parasitic capacitor C3 drops rapidly until reverse bias, and since the capacitance of the first capacitor C1 can be much larger than that of the gate-source parasitic capacitor C3, the voltage across the first capacitor C1 can still be maintained at a certain negative voltage, thus ensuring the negative voltage turn-off of the field effect tube Q1.

[0079] As can be seen, in the present example, by setting the capacitance relationship between the first capacitor C1 and the gate-source parasitic capacitor C3, the gate-source parasitic capacitor C3 can be discharged stably through the first capacitor C1, thus improving the reliability of the turn-off of the field effect tube.

[0080] In one possible embodiment, as shown in FIG. 1, the driving clamp circuit can further include a first resistor R1, a first capacitor C1 and a second capacitor C2. Figure 5 The anode of the second diode D2 is connected with the first end of the first resistor R1, and the cathode of the second diode D2 is connected with the second end of the first resistor R1.

[0081] Wherein, when the driving module 110 controls the field effect tube Q1 to turn on, the current can flow to the field effect tube Q1 through the second diode D2, thus accelerating the driving speed of the field effect tube Q1.

[0082] In this way, by connecting the second diode D2 in parallel across the first resistor R1, the field effect tube Q1 can accelerate during the process of turning on, thus accelerating the driving speed of the field effect tube Q1.

[0083] The present application also provides a vehicle-mounted power supply, which includes the driving clamp circuit described in the above embodiments of the present application, and the specific structure of the driving clamp circuit is referred to the above embodiments. Since the vehicle-mounted power supply adopts all the technical solutions in the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0084] It should be noted that in the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0085] The above has introduced the embodiments of the present application in detail, and the specific examples have been applied to describe the principles and implementation manners of the present application; the above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range can be changed, and the above description of the present application should not be understood as a limitation.

[0086] Although the present application has been disclosed with reference to the above examples, it is not intended to limit the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, can easily think of changes or substitutions, and can make various changes and modifications, including combinations of different functions and implementation steps, including software and hardware implementations, all of which are within the scope of the present application.

Claims

1. A drive clamp circuit characterized by comprising: The drive module, the first resistor R1, the clamping module, and the field effect tube Q1, wherein the clamping module comprises the first capacitor C1, the second triode Q2, and the first diode D1, and wherein The first end of the drive module is connected with the first end of the first resistor R1, the second end of the first resistor R1 is connected with the gate of the field effect tube Q1, the first end of the first capacitor C1 is connected with the second end of the first resistor R1, the second end of the first capacitor C1 is connected with the first end of the second triode Q2, the second end of the second triode Q2 is connected with the second end of the drive module, the third end of the second triode Q2 is connected with the third end of the drive module, the cathode of the first diode D1 is connected with the second end of the first capacitor C1, and the anode of the first diode D1 is connected with the source of the field effect tube Q1 and the third end of the drive module respectively.

2. The driving clamp circuit according to claim 1, wherein The first end of the second triode Q2 is the emitter, the second end of the second triode Q2 is the base, and the third end of the second triode Q2 is the collector; or The first end of the second triode Q2 is the collector, the second end of the second triode Q2 is the base, and the third end of the second triode Q2 is the emitter.

3. The driving clamp circuit according to claim 2, wherein The driving module comprises an amplifier U1A, a first line parasitic inductor L1, a second line parasitic inductor L2, a third triode Q3, a second resistor R2, and a third resistor R3, an output end of the amplifier U1A is connected with a first end of the line parasitic inductor L1, a second end of the first line parasitic inductor L1 is connected with a first end of the first resistor R1, a second end of the first resistor R1 is connected with a first end of the second resistor R2, a second end of the second resistor R2 is connected with a base of the third triode Q3, an emitter of the third triode Q3 is connected with the first end of the first resistor R1, a collector of the third triode Q3 is connected with a first end of the third resistor R3, a second end of the third resistor R3 is connected with a base of the second triode Q2, a collector of the second triode Q2 is connected with a first end of the second line parasitic inductor L2, a second end of the second line parasitic inductor L2 is connected with a power supply positive input end V CC and a power supply negative input end V EE of the amplifier U1A and grounded respectively.

4. The driving clamp circuit according to claim 2, wherein The driving module comprises an amplifier U1A, a first line parasitic inductor L1, a second line parasitic inductor L2, a third triode Q3, a second resistor R2, and a third resistor R3, an output end of the amplifier U1A is connected with a first end of the line parasitic inductor L1, a second end of the first line parasitic inductor L1 is connected with a first end of the first resistor R1, a second end of the first resistor R1 is connected with an emitter of the third triode Q3, a base of the third triode Q3 is connected with a first end of the second resistor R2, a second end of the second resistor R2 is connected with a first end of the first resistor R1, a collector of the third triode Q3 is connected with a first end of the third resistor R3, a second end of the third resistor R3 is connected with a base of the second triode Q2, an emitter of the second triode Q2 is connected with a first end of the second line parasitic inductor L2, a second end of the second line parasitic inductor L2 is connected with a power supply positive input end V CC and a power supply negative input end V EE of the amplifier U1A and grounded respectively.

5. The drive clamp circuit according to claim 3 or 4, characterized in that The power supply positive input end V CC The loop formed by the fourth capacitor C4 and the fifth capacitor C5 in series is connected to the power supply negative input end V EE The second end of the second line parasitic inductor L2 is connected between the fourth capacitor C4 and the fifth capacitor C5.

6. The driving clamp circuit according to claim 2, wherein The drive module comprises the drive chip, the third line parasitic inductance L3, the fourth line parasitic inductance L4, and the fifth line parasitic inductance L5, the first port of the drive chip is connected with the first end of the third line parasitic inductance L3, the second end of the third line parasitic inductance L3 is connected with the first end of the first resistor R1, the second port of the drive chip is connected with the first end of the fourth line parasitic inductance L4, the second end of the fourth line parasitic inductance L4 is connected with the second end of the second triode Q2, the third port of the drive chip is connected with the first end of the fifth line parasitic inductance L5, and the second end of the fifth line parasitic inductance L5 is connected with the third end of the second triode Q2.

7. The driving clamp circuit according to claim 2, wherein The field effect tube Q1 has a parasitic capacitor, the parasitic capacitor comprises the gate-drain parasitic capacitor C2 and the gate-source parasitic capacitor C3, the first end of the gate-drain parasitic capacitor C2 is connected with the first end of the first capacitor C1, the second end of the gate-drain parasitic capacitor C2 is connected with the drain of the field effect tube Q1, the first end of the gate-source parasitic capacitor C3 is connected with the first end of the first capacitor C1, and the second end of the gate-source parasitic capacitor C3 is connected with the third end of the second triode Q2 and the source of the field effect tube Q1.

8. The driving clamp circuit according to claim 7, wherein The capacitance of the first capacitor C1 is greater than the capacitance of the gate-source parasitic capacitor C3.

9. The driving clamp circuit according to claim 8, wherein, The drive clamping circuit further comprises the second diode D2, the anode of the second diode D2 is connected with the first end of the first resistor R1, and the cathode of the second diode D2 is connected with the second end of the first resistor R1.

10. An on-board power supply, characterized by The drive clamping circuit comprises any one of claims 1-9. The drive clamping circuit comprises any one of claims 1-9.

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