Semiconductor device

Abstract

The utility model provides a semiconductor device, which is applied to the technical field of semiconductors. According to the utility model, a new semiconductor device structure is formed by arranging the extension part at the partial position of the contact structure.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technology field especially relates to a semiconductor device. BACKGROUND

[0002] Dynamic random access memory (DRAM) belongs to a kind of volatile memory, including the array area (array area) being formed by multiple memory cells and the peripheral area (peripheral area) being formed by control circuit.The each memory cell is formed by a transistor and an electric capacity (capacitor) being electrically connected with the transistor, the storage or release of the charge in the electric capacity is controlled by the transistor, to reach the purpose of storing data.Control circuit can be addressed to each memory cell by word line (WL) and bit line (BL) being electrically connected with each memory cell across array area, to control the access of the data of each memory cell.However, due to the limitation of process technology, there are still many defects in the existing dynamic random access memory, and the performance and reliability of related memory components need to be further improved and effectively improved. SUMMARY

[0003] The utility model aims at providing a kind of semiconductor device, it is under the premise of not increasing additional process technology and not affecting device performance, forms the novel device structure that second bit line plug and contact structure exist at least partial communication.

[0004] To solve the above technical problems, the utility model provides a kind of semiconductor device, at least can include:

[0005] Substrate, including active region and shallow trench isolation area adjacent to the active region;

[0006] Multiple bit lines are set on the substrate, and the bit line includes multiple first bit lines and at least one second bit line, and the at least one second bit line is set on the outside of all the first bit lines;

[0007] First recess, located in the substrate, the first recess is filled with first bit line plug, the bottom of the first bit line plug is in contact with the active region, and the top is in contact with the first bit line;

[0008] Second recess, located in the substrate, the second recess is filled with second bit line plug, and the top of the second bit line plug is in contact with the second bit line;

[0009] The width of the first wire plug in the horizontal direction is less than the width of the first groove in the horizontal direction, and the width of the second wire plug in the horizontal direction is equal to the width of the second groove in the horizontal direction.

[0010] Optionally, the bottom of the second bit line plug may not be higher than the bottom of the first bit line plug in the vertical direction.

[0011] Optionally, the bottom of the second bit line plug may be lower than the bottom of the first bit line plug in the vertical direction.

[0012] Optionally, the semiconductor device may further include:

[0013] Multiple gap wall structures are respectively disposed on both sides of the first position line and at least one side wall of the second position line.

[0014] Optionally, the semiconductor device may further include:

[0015] At least one contact structure, the contact structure comprising:

[0016] The first portion is located within the substrate;

[0017] The second part is located on the substrate and is situated between the adjacent first bit line and the second bit line.

[0018] Optionally, the width of the first portion in the horizontal direction is greater than the width of the second portion in the horizontal direction, and the first portion extends toward the second bit line plug and directly contacts the second bit line plug.

[0019] Optionally, the width of the first portion in the horizontal direction is equal to the width of the second portion in the horizontal direction, and the first portion and the second bit line plug are isolated from each other.

[0020] Optionally, the top surface of the extension of the first portion toward the second bit plug is isolated from the gap wall structure.

[0021] Optionally, the bottom surface of the extension portion of the first part toward the second bit line plug may be higher than the bottom surface of the second bit line plug.

[0022] Optionally, the width of the first bit line in the horizontal direction may be smaller than the width of the second bit line in the horizontal direction.

[0023] Optionally, the bottom surface of the contact structure may be higher than the bottom surface of the second bit plug.

[0024] To solve the above-mentioned technical problems, this utility model also provides another semiconductor device, comprising:

[0025] a substrate including an active region and a shallow trench isolation region adjacent to the active region;

[0026] a plurality of bit lines disposed on the substrate, the bit lines including a plurality of first bit lines and at least one second bit line, the at least one second bit line disposed outside of all of the first bit lines;

[0027] a first recess in the substrate, the first recess filled with a first bit line plug, a bottom of the first bit line plug in contact with the active region and a top of the first bit line plug in contact with the first bit line;

[0028] a second recess in the substrate, the second recess filled with a second bit line plug, the second bit line plug filling the second recess and a top of the second bit line plug in direct contact with the second bit line.

[0029] To solve the above technical problems, the utility model also provides another kind of semiconductor device, comprising:

[0030] a substrate including an active region and a shallow trench isolation region adjacent to the active region;

[0031] a plurality of bit lines disposed on the substrate, the bit lines including a plurality of first bit lines and at least one second bit line, the at least one second bit line disposed outside of all of the first bit lines;

[0032] a first bit line plug in the substrate, a top of the first bit line plug in direct contact with the first bit line;

[0033] a second bit line plug in the substrate, a top of the second bit line plug in direct contact with the second bit line, wherein sidewalls of the second bit line plug are between sidewalls of the second bit line in a horizontal direction.

[0034] As described above, the utility model provides a kind of semiconductor device, including second bit line plug below second bit line and contact structure between second bit line and first bit line, wherein contact structure can include first part in substrate and second part on first part, and the first part of the contact structure has the extension of the direction to the second bit line plug, and the contact structure and the second bit line plug are communicated by the extension;Wherein the extension of the first part of the contact structure is formed simultaneously in the process of forming the trench of contact structure in corresponding position, so the utility model can form the new device structure that second bit line plug and contact structure exist at least partial communication without additional process technology and without affecting the performance of semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and serve to explain the principles of the present application, but are not intended to limit the present application. In the drawings:

[0036] Figures 1-15 The structure schematic diagram of the semiconductor device provided in an embodiment of the present application in a preparation process.

[0037] In the drawings, the same components are designated by the same reference numerals, and the drawings are not drawn to scale.

[0038] 100 - substrate, 110 - shallow trench isolation region, ACT - active region, 120 - insulating layer, 101 - first recess, 102 - second recess, 130 - bit line material layer, 131 - semiconductor layer, 132 - barrier layer, 133 - metal layer, 134 - cap layer, BL1 - first bit line, BL2 - second bit line, 131a - first bit line plug, 131b - second bit line plug, H1 - height difference between the bottom of the first bit line plug and the bottom of the second bit line plug, 140 - spacer structure, 141 - first spacer layer, 142 - second spacer layer, 143 - third spacer layer, 140a - first spacer structure, 140b - second spacer structure, 150 - contact structure, 151 - first contact structure, 152 - second contact structure, 153 - third contact.

[0039] In the drawings, the same components are designated by the same reference numerals, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0040] In order to make the technical scheme and advantages of the embodiments of the present application more clear, the technical scheme of the present application will be further described in detail below with reference to the drawings and embodiments. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0041] The utility model is described in more detail in the following paragraphs with reference to the drawings. The advantages and features of the utility model will become more apparent from the following description and claims. It is to be understood that the drawings are simplified and are not drawn to scale, and are used merely to facilitate and clarify the description of the embodiments of the utility model. It is to be understood that the meanings of "on", "above" and "above" in the utility model should be interpreted in the broadest way, so that "on" not only means "on" with no intervening features or layers (i.e. directly on) but also means "on" with intervening features or layers. In the embodiments of the utility model, the terms "first", "second" and the like are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the utility model can be combined arbitrarily without conflict.

[0042] Please refer to Figures 8 to 11 , the drawing is the schematic diagram of the semiconductor device in the first embodiment of the utility model, wherein, Figure 8 is the schematic diagram of the bottom of the contact structure in the semiconductor device contacting the active region and the shallow trench isolation region, Figure 9 is the schematic diagram of the bottom of the contact structure in the semiconductor device contacting only the active region, Figure 10 is the schematic diagram of the bottom of the contact structure in the semiconductor device contacting only the shallow trench isolation region, Figure 11 is the evolution schematic diagram of the bottom of the contact structure in the semiconductor device contacting the active region and the shallow trench isolation region. As Figures 8 to 11 shown, the semiconductor device in the first embodiment of the utility model includes a substrate 100, such as a silicon substrate, a silicon-containing substrate or a silicon-on-insulator substrate or a substrate composed of other suitable materials, but is not limited thereto. A plurality of shallow trench isolation regions 110 are provided in the substrate 100 to define a plurality of active regions ACT on the substrate 100, in other words, the shallow trench isolation regions 110 surround all the active regions ACT. It should be understood that the spacing between adjacent shallow trench isolation regions 110 and the width of part of the shallow trench isolation regions 110 in the direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction) can be the same or different, and the specific arrangement can be changed based on the relative positional relationship between the subsequently formed components and / or parts, such as the contact structure, the bit line, etc.

[0043] In one embodiment, the shallow trench isolation region 110 is formed by, for example, etching a plurality of trenches (not shown) in the substrate 100, and filling the trenches with an insulating material (e.g., silicon oxide or silicon oxynitride, etc.), but not limited thereto. The substrate 100 can further be provided with an insulating layer 120, which can be a single layer structure, such as a silicon oxide layer or a silicon oxynitride layer, or a composite structure, such as an ONO stack structure of an oxide layer (e.g., silicon dioxide), a nitride layer (e.g., silicon nitride), and an oxide layer (e.g., silicon dioxide), as shown, but not limited thereto. In one embodiment, the insulating layer 120 is formed by, for example, at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., on the substrate 100, as shown. Figures 8 to 11 but not limited thereto. In one embodiment, the insulating layer 120 is formed by, for example, at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., on the substrate 100, as shown. Figure 1 In one embodiment, the insulating layer 120 is formed by, for example, at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., on the substrate 100, as shown.

[0044] Further, the semiconductor device in the first embodiment of the present application further includes a plurality of bit lines arranged to be separated from each other, which can be specifically divided into first bit lines BL1 having a first width and second bit lines BL2 having a second width based on the width thereof in the direction parallel to the surface of the substrate 100, wherein the first width is different from the second width, for example, the first width is smaller than the second width, and the second bit lines BL2 are arranged outside all of the first bit lines BL1, for example, as shown. Figures 8 to 11 but not limited thereto. Some of the bit lines are further provided with bit line plugs extending into the substrate 100, such as a first bit line plug 131a located below the first bit line BL1 and directly contacting the bottom of the first bit line BL1, and a second bit line plug 131b located below the second bit line BL2 and directly contacting the top of the second bit line BL2.

[0045] In one embodiment, the bit line plugs (including the first bit line plug 131a and the second bit line plug 131b) are formed by, for example, etching a plurality of grooves in the insulating layer 120 and the substrate 100, such as a plurality of first grooves 101 (same position as the first bit line plug 131a) and a second groove 102 (same position as the second bit line plug 131b), as shown. Figure 2 or Figure 3As shown, then a semiconductor layer 131 (bottom layer material layer of the bit line material layer 130) is formed on the insulating layer 120, and the semiconductor layer 131 fills the recesses and extends laterally to cover the insulating layer 120 between adjacent recesses, and then a blocking layer 132, a metal layer 133 and a cap layer 134 are sequentially formed from bottom to top, thereby forming the bit line material layer 130, and then at least one of etching processes such as wet etching or dry etching is used to etch the bit line material layer 130, so as to form the second bit line BL2 and the plurality of first bit lines BL1 arranged in sequence in the horizontal direction from left to right on the substrate 100, and the semiconductor layer 131 filled in the first recess 101 is defined as the first bit line plug 131a, and the semiconductor layer 131 filled in the second recess 102 is defined as the second bit line plug 131b, as shown. Figure 4 or Figure 5 As shown. The material of the semiconductor layer 131 can include crystalline silicon, polysilicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The material of the blocking layer 132 can include metal, metal silicide or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The material of the metal layer 133 can include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys and / or composite layers of the aforementioned metal materials, but is not limited thereto. The material of the cap layer 134 can include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combinations of the above materials, but is not limited thereto. For example, the material of the semiconductor layer 131 is polysilicon, the material of the blocking layer 132 is titanium nitride (TiN), the material of the metal layer 133 is tungsten (W), and the material of the cap layer 134 is silicon nitride (SiN).

[0046] It should be particularly pointed out that the bottom surfaces (also referred to as bottoms) of the first recess 101 and the second recess 102 in the first embodiment of the utility model can be flush, for example Figure 2 As shown, the bottom surface of the first recess 101 is at the same horizontal level as the bottom surface of the second recess 102 in the direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction); or the bottom surfaces of the first recess 101 and the second recess 102 can also not be flush, for example Figure 3The bottom surface of the first groove 101 is higher than the bottom surface of the second groove 102 in the vertical direction, so that the bottom surfaces of the two have a height difference H1 in the vertical direction, where H1>0. In this arrangement, the bottom surfaces of the first bit line plug 131a and the second bit line plug 131b in the first embodiment of the present application can also be flush or not flush in the vertical direction, for example Figure 4 The bottom surfaces of the first bit line plug 131a and the second bit line plug 131b are flush, or for example Figure 5 The bottom surface of the first bit line plug 131a is higher than the bottom surface of the second bit line plug 131b in the vertical direction, that is, there is also a height difference H1 between the bottom surfaces of the first bit line plug 131a and the second bit line plug 131b.

[0047] Also, the widths of the first groove 101 and the second groove 102 in the horizontal direction in the first embodiment of the present application can be the same (for example Figure 14 or Figure 15 different (for example Figures 2 to 15 ), where the width of the second groove 102 in the horizontal direction should not be greater than the width of the second bit line BL2 in the horizontal direction directly contacting the top surface thereof, so that the two side walls of the second bit line plug 131b are located between the two side walls of the second bit line BL2 above it in the horizontal direction. Because the subsequent protective spacer wall structure 140 formed on the two side walls of the first bit line BL1 will also be filled in the first groove 101 below it, while the subsequent spacer wall structure 140 formed on the two side walls of the second bit line BL1 will not, so that the width of the first bit line plug 131a in the horizontal direction is less than the width of the first groove 101 in the horizontal direction, and the width of the second bit line plug 131b in the horizontal direction is the same as the width of the second groove 102 in the horizontal direction.

[0048] It should be understood that the width of the first bit line plug 131a or the second bit line plug 131b or the first groove 101 or the second groove 102 in the horizontal direction can also be the average width in the horizontal direction, but is not limited thereto.

[0049] Further, the semiconductor device in the first embodiment of the utility model still includes multiple spacer structures 140. Among them, the spacer structure 140 is arranged on the two side walls of each first bit line BL1 and at least one side wall of the second bit line BL2. Specifically, the spacer structure 140 can be a single-layer structure, such as an oxide layer (material such as silicon dioxide) or a nitride layer (material such as silicon nitride), and can also be a composite structure, such as including a first spacer layer 141, a second spacer layer 142 and a third spacer layer 143 arranged in sequence along the horizontal direction. Among them, the first spacer layer 141 is in direct contact with the side wall of the first bit line BL1 or the second bit line BL2.

[0050] It needs to be specially pointed out that, in the first embodiment of the utility model, as shown in the figure, Figures 8 to 11 The shape of the spacer structure 140 formed on the two side walls of the first bit line BL1 and the two side walls of the second bit line BL2 is the same, for example, Figure 6 As shown in the figure. And in other embodiments, the spacer structure on at least one side wall of the second bit line BL2 can be different from the shape of the spacer structure 140 on the other side wall and the two side walls of the other first bit line BL1, for example, Figure 7 As shown in the figure, the spacer structures on the two side walls of the second bit line BL2 are different. In order to distinguish, the spacer structure on the side wall of the second bit line BL2 away from the rest of the first bit line BL1 is marked with reference numeral 140b, and the spacer structure on the side wall adjacent to the rest of the first bit line BL1 is marked with reference numeral 140a.

[0051] In an embodiment, the spacer structure 140a is formed, for example, by sequentially forming a co-typed covering first spacer layer 141 (material such as silicon oxide), a second spacer layer 142 (material such as silicon nitride) and a third spacer layer 143 (material such as silicon oxide) on the inner surface of the gap between adjacent bit lines (including all first bit lines BL1 and second bit lines BL2), and then etching to remove the first spacer layer 141, the second spacer layer 142 and the third spacer layer 143 on the bottom of the gap between adjacent bit lines, and exposing the top surface of the insulating layer 120 at the bottom of the gap between adjacent spacer structures 140a. And in another embodiment, the spacer structure 140b is formed, for example, after forming the bit line material layer 130 of the multiple bit lines as shown in the figure, Figure 4 Or Figure 5 After forming the bit line material layer 130 of the multiple bit lines as shown in the figure, Figure 4 Or Figure 5The photoresist layer (not shown) of the left part of the bit line material layer 130 is shown, and then the bit line material layer 130 not covered by the photoresist layer is removed to form the bit line BL2 as shown. Figure 4 Or Figure 5 The bit line material layer 130 and the insulating layer 120 below it to the left of the second bit line BL2 are shown, and then a deposition process is used to form the bit line BL2 as shown in the left part of the second bit line BL2. Figure 7 The spacer wall structure 140b containing three layers of spacer walls is shown, and the three layers of spacer walls contained in the spacer wall structure 140b are arranged in a vertical direction in sequence, but are not limited to this.

[0052] Further, the semiconductor device in the first embodiment of the present application further includes a plurality of contact structures 150, which are located between adjacent bit lines, such as between the adjacent first bit line BL1 and the second bit line BL2, and between any two adjacent first bit lines BL1. In detail, the contact structure 150 can include a first part (not shown) located in the substrate 100 and a second part (not shown) located on the substrate 100 and between the adjacent first bit line BL1 and the second bit line BL2.

[0053] In an embodiment, the formation of the contact structure 150 can use an etching process such as a dry etching process to etch and remove a portion of the height of the substrate 100 between adjacent bit lines to form a plurality of trenches (not shown), and then fill the trenches and the gap between adjacent bit lines with a conductive material such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), etc., until the top surface of the filled conductive material is flush with the top surface of the bit lines on both sides; and the contact structure 150 can be a single-layer structure with conductive material, or can have a multi-layer structure such as a composite structure of conductive material on both sides, or the contact structure 150 can be a stacked structure with conductive material and insulating material stacked from bottom to top, but is not limited to this.

[0054] It should be noted that the first part and the second part of the contact structure 150 shown in the first embodiment of the present application have the same width in the horizontal direction, that is, the first part of the contact structure 150 (the part located in the substrate 100) does not have an extension part extending towards the second bit line BL2. However, the bottom (also referred to as the bottom surface) of the contact structure 150 shown in the first embodiment of the present application (which is also the bottom of the first part of the contact structure 150) has various combinations of contact with the active region ACT and the shallow trench isolation region 110, and in order to facilitate differentiation, the contact structure in various different cases of direct contact with the active region ACT and the shallow trench isolation region 110 in the embodiments of the present application is respectively identified by a first contact structure, a second contact structure, a third contact structure, and different reference numerals. For example, as shown in Figure 8 , in an embodiment, the first contact structure whose bottom directly contacts the active region ACT and the shallow trench isolation region 110 is identified by reference numeral 151; for example, as shown in Figure 9 , in another embodiment, the second contact structure whose bottom only directly contacts the active region ACT is identified by reference numeral 152; for example, as shown in Figure 10 , in other embodiments, the third contact structure whose bottom only directly contacts the shallow trench isolation region 110 is identified by reference numeral 153, but is not limited thereto.

[0055] It should be understood that in the first embodiment of the present application, Figures 8 to 10 only shows the case where one side of the second bit line BL2 is provided with the contact structure 150, and in other embodiments, both sides of the second bit line BL2 can be provided with the contact structure 150, that is, the structure shown in Figure 11 , and other parts and / or components are the same as the structure shown in Figures 8 to 10 , but are not limited thereto.

[0056] Those skilled in the art to which the present application belongs should easily understand that, under the premise of being able to meet the actual product requirements, the semiconductor device of the present application can also have other forms and is not limited to the foregoing. In the following, other embodiments or variations of the semiconductor device of the present application will be further described. In order to simplify the description, the following description mainly details the differences between the embodiments, and the same parts are not repeated. In addition, the same components in the embodiments of the present application are identified by the same reference numerals for the purpose of mutual comparison between the embodiments.

[0057] Please refer to Figures 12 to 15 , which is a schematic diagram of a semiconductor device in the second embodiment of the present application, wherein Figure 12This is a schematic diagram showing an extension of the first part of a contact structure in a semiconductor device in direct contact with a second bit line plug. Figure 13 This is another schematic diagram showing the extension of the first part of the contact structure in a semiconductor device directly contacting the second bit line plug. Figure 14 Another schematic diagram showing the extension of the first part of the contact structure in a semiconductor device in direct contact with the second bit line plug. Figure 15 This is another schematic diagram showing the extension of the first part of the contact structure in a semiconductor device directly contacting the second bit line plug. For example... Figures 12 to 15 As shown, the structure of the semiconductor device in this embodiment is largely the same as that of the semiconductor device in the first embodiment described above. For example, the semiconductor device also includes multiple bit lines. The multiple bit lines include a second bit line BL2 and multiple first bit lines BL1 arranged sequentially from left to right in the horizontal direction and having different widths in the horizontal direction. Bit line plugs extending into the substrate 100 are also provided below some of the bit lines. For example, a first bit plug 131a located below the first bit line BL1 and in direct contact with the bottom of the first bit line BL1, and a bit line plug 131a located below the second bit line BL2. The second bit line plug 131b directly contacts the bottom of the second bit line BL2. The bottom (or bottom surface) of the first bit line plug 131a and the bottom (or bottom surface) of the second bit line plug 131b can be flush or at different horizontal heights. The width of the first bit line plug 131a in the horizontal direction is smaller than the width of the first groove 101 in the horizontal direction, and the width of the second bit line plug 131b in the horizontal direction is equal to the width of the second groove 102 in the horizontal direction, etc. Similarities will not be repeated here. The main difference between the semiconductor device of this embodiment and the aforementioned first embodiment is that the first portion of the contact structure 150 extends towards the second bit line plug 131b, and this extension extends horizontally until it directly contacts the adjacent second bit line plug 131b. Figures 12 to 15 The position outlined in the black dashed box is the first part extending towards the second position line plug 131b. For ease of distinction, this utility model refers to the part formed by the extension of the first part of the contact structure 150 towards the second position line plug 131b as the extension part.

[0058] In one embodiment, such as Figure 12As shown, the entire sidewall of the first portion of the contact structure 150 extending towards the second bit line plug 131b is in direct contact with the second bit line plug 131b, and the top surface of the extended portion of the first portion of the contact structure 150 extending towards the second bit line plug 131b is in direct contact with the bottom of the spacer structure 140a between the contact structure and the second bit line BL2, but not limited thereto. Also, based on the various settings of the width of the second recess 102 in the horizontal direction in the first embodiment, the width of the second bit line plug 131b filled in the second recess 102 in the horizontal direction in the present embodiment also has the various cases in the first embodiment, Figure 12 Only the case where the two sidewalls of the second bit line plug 131b are respectively aligned with the two sidewalls of the second bit line BL2 in direct contact with the top surface of the second bit line plug 131b in the vertical direction is shown, but not limited thereto. In this setting, the overall width of the first portion of the contact structure 150 in the horizontal direction in the present embodiment is greater than the width of the second portion contained therein in the horizontal direction.

[0059] In another embodiment, as Figure 13 shown, part of the sidewall of the first portion of the contact structure 150 extending towards the second bit line plug 131b is in direct contact with the second bit line plug 131b, and the top surface of the extended portion of the first portion of the contact structure 150 extending towards the second bit line plug 131b is isolated from each other, i.e. not in direct contact with the bottom of the spacer structure 140a between the contact structure 150 and the second bit line BL2, but not limited thereto. Also, based on the various settings of the width of the second recess 102 in the horizontal direction in the first embodiment, the width of the second bit line plug 131b filled in the second recess 102 in the horizontal direction in the present embodiment also has the various cases in the first embodiment, Figure 13 Only the case where the two sidewalls of the second bit line plug 131b are respectively aligned with the two sidewalls of the second bit line BL2 in direct contact with the top surface of the second bit line plug 131b in the vertical direction is shown, but not limited thereto. In this setting, the overall width of the first portion of the contact structure 150 in the horizontal direction in the present embodiment is greater than the width of the second portion contained therein in the horizontal direction.

[0060] In other embodiments, as Figure 14As shown, the part of the first part of the contact structure 150, which extends towards the second bit line plug 131b, has its part of the sidewall directly in contact with the second bit line plug 131b, and the top surface of the extension of the first part of the contact structure 150, which extends towards the second bit line plug 131b, is isolated from the bottom of the spacer structure 140a between the contact structure 150 and the second bit line BL2, i.e. not directly in contact, but not limited thereto. And based on the different settings of the width of the second recess 102 in the horizontal direction in the first embodiment, the width of the second bit line plug 131b filled in the second recess 102 in the horizontal direction in the present embodiment also has the above-mentioned cases in the first embodiment, Figure 14 Only the case where the two sidewalls of the second bit line plug 131b are located between the two sidewalls of the second bit line BL2, whose top surfaces are directly in contact, is shown, but not limited thereto. In this setting, the overall width of the first part of the contact structure 150 in the horizontal direction in the present embodiment is greater than the width of the second part contained therein in the horizontal direction.

[0061] Similarly, the first part of the contact structure 150 in the second embodiment of the utility model Figures 12 to 14 Only the case where one side of the second bit line BL2 is provided with the contact structure 150 is shown, and in other embodiments, both sides of the second bit line BL2 can be provided with the contact structure 150, i.e. as Figure 15 The structure shown, but other parts and / or components are the same as the structure shown in the Figures 12 to 14 The structure shown, but not limited thereto.

[0062] It should be understood that the "co-molded" in the embodiments of the utility model refers to the similarity and correlation between two or more shapes, and the continuous structure shape is obtained by construction.

[0063] In summary, the semiconductor device provided by the utility model comprises a second bit line plug below the second bit line and a contact structure between the second bit line and the first bit line, wherein the contact structure can comprise a first part in the substrate and a second part on the first part, and the first part of the contact structure has an extension part towards the second bit line plug, and the contact structure and the second bit line plug are communicated through the extension part; wherein the corresponding position of the extension part of the first part of the contact structure is formed synchronously in the process of forming the trench of the contact structure, so that the utility model can form a novel device structure with at least partial communication between the second bit line plug and the contact structure without increasing additional process and affecting the performance of the semiconductor device.

[0064] The above merely describes preferred embodiments of the present application, and is not intended to limit the scope of protection of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes an active region and a shallow trench isolation region adjacent to the active region; Multiple bit lines are disposed on the substrate, the bit lines including multiple first bit lines and at least one second bit line, the at least one second bit line being disposed outside all the first bit lines; A first groove is located within the substrate, and a first bit line plug is filled in the first groove. The bottom of the first bit line plug contacts the active region, and the top of the first bit line contacts the first bit line. A second groove is located within the substrate, and a second bit line plug is filled in the second groove, with the top of the second bit line plug contacting the second bit line. The width of the first wire plug in the horizontal direction is less than the width of the first groove in the horizontal direction, and the width of the second wire plug in the horizontal direction is equal to the width of the second groove in the horizontal direction.

2. The semiconductor device as claimed in claim 1, characterized in that, The bottom of the second bit line plug is not higher than the bottom of the first bit line plug in the vertical direction.

3. The semiconductor device as described in claim 1, characterized in that, The bottom of the second bit line plug is lower than the bottom of the first bit line plug in the vertical direction.

4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Multiple gap wall structures are respectively disposed on both sides of the first position line and at least one side wall of the second position line.

5. The semiconductor device as claimed in claim 4, characterized in that, Also includes: At least one contact structure, the contact structure comprising: The first portion is located within the substrate; The second part is located on the substrate and is situated between the adjacent first bit line and the second bit line.

6. The semiconductor device as claimed in claim 5, characterized in that, The width of the first part in the horizontal direction is greater than the width of the second part in the horizontal direction, and the first part extends toward the second bit line plug and directly contacts the second bit line plug.

7. The semiconductor device as claimed in claim 5, characterized in that, The width of the first portion in the horizontal direction is equal to the width of the second portion in the horizontal direction, and the first portion is isolated from the second bit line plug.

8. The semiconductor device as claimed in claim 6, characterized in that, The top surface of the extension of the first part toward the second position line plug is isolated from the gap wall structure.

9. The semiconductor device as claimed in claim 6, characterized in that, The bottom surface of the extension portion of the first part toward the second bit line plug is higher than the bottom surface of the second bit line plug.

10. The semiconductor device as claimed in claim 1, characterized in that, The width of the first bit line in the horizontal direction is smaller than the width of the second bit line in the horizontal direction.

11. The semiconductor device as claimed in claim 5, characterized in that, The bottom surface of the contact structure is higher than the bottom surface of the second bit plug.

12. A semiconductor device, characterized in that, include: The substrate includes an active region and a shallow trench isolation region adjacent to the active region; Multiple bit lines are disposed on the substrate, the bit lines including multiple first bit lines and at least one second bit line, the at least one second bit line being disposed outside all the first bit lines; A first groove is located within the substrate, and a first bit line plug is filled in the first groove. The bottom of the first bit line plug contacts the active region, and the top of the first bit line contacts the first bit line. The second groove is located within the substrate, and the second groove is filled with a second bit line plug. The second bit line plug fills the second groove and its top is in direct contact with the second bit line.

13. A semiconductor device, characterized in that, include: The substrate includes an active region and a shallow trench isolation region adjacent to the active region; Multiple bit lines are disposed on the substrate, the bit lines including multiple first bit lines and at least one second bit line, the at least one second bit line being disposed outside all the first bit lines; The first bit line plug is located within the substrate, and the top of the first bit line plug is in direct contact with the first bit line. The second bit line plug is located within the substrate, with its top directly contacting the second bit line, wherein the two side walls of the second bit line plug are located between the two side walls of the second bit line in the horizontal direction.

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