Semiconductor device

Abstract

The utility model provides a semiconductor device, which comprises a substrate, a first active structure, a plurality of first inner spacers, a conductive part and a first cap part, the first active structure is formed on the substrate and comprises a plurality of first active channel sheets and a plurality of first metal gate structures which are vertically stacked with each other. Each first inner spacer is formed on a side surface of a corresponding first metal gate structure. And the conductive part is connected with the topmost first active channel sheet. A first cap portion is formed over the topmost first inner spacer and covers a side surface of the conductive portion.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] A semiconductor device usually includes at least one active structure, which includes a plurality of active channel pieces. However, the topmost active channel piece is easily damaged during etching of dummy gates above the active structure. SUMMARY

[0003] One embodiment of the present application provides a semiconductor device. The semiconductor device includes a substrate, a first active structure, a plurality of first inner spacers, a conductive portion, and a first helmet. The first active structure is formed on the substrate and includes a plurality of first active channel pieces and a plurality of first metal gate structures vertically stacked with each other. Each first inner spacer is formed on a side surface of a corresponding first metal gate structure. The conductive portion is connected to a topmost first active channel piece. The first helmet is formed above a topmost first inner spacer and covers a side surface of the conductive portion.

[0004] Another embodiment of the present application provides a semiconductor device. The semiconductor device includes a substrate, an active structure, a plurality of inner spacers, and a helmet. The active structure is formed on the substrate and includes a plurality of active channel pieces and a plurality of metal gate structures vertically stacked with each other. Each inner spacer is formed on a side surface of a corresponding metal gate structure. The helmet covers a side surface of a topmost inner spacer and a conductive portion.

[0005] Another embodiment of the present application provides a method of manufacturing a semiconductor device. The method includes the following steps: forming a first active structure on a substrate, wherein the first active structure includes a plurality of first active channel pieces and a plurality of first metal gate structures vertically stacked with each other; forming a plurality of first inner spacers, wherein each first inner spacer is formed on a side surface of a corresponding first metal gate structure; forming a first helmet above the first inner spacers; and forming a conductive portion connected to a topmost first active channel piece, wherein the first helmet covers a side surface of the conductive portion.

[0006] For better understanding of the above objects and other aspects of the present application, a more detailed description is provided with reference to the following embodiments and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A cross-sectional view of a semiconductor device according to one embodiment of the present application is shown.

[0008] Figures 2A-2L A process flow of a semiconductor device according to one embodiment of the present application is shown. Figure 1

[0009] In the drawings:​

[0010] 100: semiconductor device

[0011] 105: substrate

[0012] 107: silicon layer

[0013] 110, 110': first active structure

[0014] 111, 111t: first active fin

[0015] 111': fin layer

[0016] 112, 112t: first metal gate structure

[0017] 112': first silicon germanium layer

[0018] 112a, 182a, DGa: space

[0019] 112r': first recess

[0020] 112A: first metal portion

[0021] 112B: first high-k dielectric portion

[0022] 112Au, 112Bu: upper surface

[0023] 112C: first inner spacer

[0024] 113: first spacer layer

[0025] 114: second spacer layer

[0026] 120: conductive portion

[0027] 120a: aperture

[0028] 120s: side surface

[0029] 120w: sidewall

[0030] 125: liner

[0031] 125w: second sidewall

[0032] 130: first cap portion

[0033] 130g: gap

[0034] 130r: space

[0035] 140: epitaxial layer

[0036] 145: conductive portion

[0037] 1451, 1452: portion

[0038] 150: contact etch stop layer

[0039] 160: oxide layer

[0040] 170A: first dielectric layer

[0041] 170B: second dielectric layer

[0042] 170C: third dielectric layer

[0043] 170D: fourth dielectric layer

[0044] 170E: fifth dielectric layer

[0045] 180, 180': second active structure

[0046] 181, 181t: second active channel sheet

[0047] 182, 182t: second metal gate structure

[0048] 182': second silicon germanium layer

[0049] 182r': second recess

[0050] 182A: second metal portion

[0051] 182B: second high-k dielectric portion

[0052] 182B1: upper portion

[0053] 182C: second inner spacer

[0054] 190: second cap portion

[0055] DG: dummy gate structure

[0056] DG1: oxide layer

[0057] DG2: dummy gate layer

[0058] DG3: shield layer

[0059] H1: height

[0060] HK: high-k dielectric portion

[0061] MG: metal portion

[0062] SL: silicon germanium layer

[0063] SP: spacer layer

[0064] T1: trench

[0065] t1: first thickness

[0066] t2: second thickness. DETAILED DESCRIPTION

[0067] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and configurations are described below to provide a thorough understanding of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features are formed between the first and second features such that the first and second features can not be in direct contact. Additionally, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0068] Furthermore, spatially relative terms (for example, "beneath", "below", "lower", "above", "upper", and the like) are used herein for ease of description to describe the elements and / or features as they are depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0069] Reference will now be made to Figure 1The diagram illustrates a cross-sectional view of a semiconductor device 100 according to an embodiment of this application. The semiconductor device 100 may include a substrate 105, at least one silicon layer 107, at least one first active structure 110, a plurality of first inner spacers 112C, at least one conductive portion (or conductive via) 120, at least one liner 125, at least one first cap 130, at least one epitaxial layer 140, at least one conductive portion 145, at least one contact etch stop layer (CESL) 150, at least one oxide layer 160, a plurality of dielectric layers (e.g., a first dielectric layer 170A, a second dielectric layer 170B, a third dielectric layer 170C, and a fourth dielectric layer 170D), at least one second active structure 180, a plurality of second inner spacers 182C, and at least one second cap 190. A first active structure 110 is formed on a substrate 105 and includes several first active channel sheets 111 and several first metal gate structures 112 stacked perpendicularly to each other. A first cap 130 is formed above the topmost first inner spacer 112C and covers the side surface 120s of the conductive portion 120 (or the side surface of the pad 125). Thus, the first cap 130 and / or the topmost first metal gate structure 112t can protect the topmost first active channel sheet 111t, thereby preventing the topmost first active channel sheet 111t from being damaged during the etching process of the dummy gate structure.

[0070] like Figure 1 As shown, the substrate 105 is, for example, a silicon wafer. A silicon layer 107 is formed in a trench T1 between two adjacent first active structures 110 and is located between the substrate 105 and the epitaxial layer 140. Each epitaxial layer 140 can be the source or drain of a transistor.

[0071] like Figure 1 As shown, the first active channel sheet 111 can be formed of a material such as silicon. A first metal gate structure 112 is formed between two adjacent first active channel sheets 111. Each first metal gate structure 112 includes a first metal portion 112A and a first high-k dielectric portion 112B, wherein the first metal portion 112A can be surrounded by the first high-k dielectric portion 112B, the first high-k dielectric portion 112B covers a portion of the first active channel sheet 111, and a first inner spacer 112C is formed on the side of the first high-k dielectric portion 112B or on the first active channel sheet 111, where k is the dielectric constant.

[0072] like Figure 1 As shown, the conductive portion 120 and the pad 125 extend to the topmost first metal gate structure 112t. Furthermore, the conductive portion 120 and the pad 125 extend to the topmost first metal gate structure 112t through the fourth dielectric layer 170D, the third dielectric layer 170C, the second dielectric layer 170B, the first dielectric layer 170A, and the first cap portion 130. Additionally, the first inner spacer 112C of the topmost first metal gate structure 112t protrudes beyond the upper surface 112Bu of the first high-k dielectric portion 112B and the upper surface 112Au of the first metal portion 112A. In one embodiment, the conductive portion 120 is, for example, a gate via (also called a "VG").

[0073] like Figure 1 As shown, the pad 125 is formed on or covers the sidewall 120w, which includes a first sidewall of the first dielectric layer 170A, a first sidewall of the second dielectric layer 170B, a first sidewall of the third dielectric layer 170C, a first sidewall of the third dielectric layer 170D, a first sidewall of the first cap 130, and a first sidewall of the topmost first inner spacer 112C. Furthermore, the sidewall 120w has a first flatness, and the second sidewall 125w of the pad 125 has a second flatness, wherein the second flatness is less than the first flatness. Thus, the conductive portion 120 is formed on or in contact with a simple (or single) material (e.g., the material of the pad 125) and the flat sidewall of the pad 125, thereby increasing the bonding strength between the pad 125 and the conductive portion 120. Furthermore, the pad 125 can be formed of materials including, for example, silicon carbide (SiC), silicon nitride (SiN), silicon nitride carbon oxide (SiOCN), silicon carbon oxide (SiOC), silicon carbonitride (SiCN), and silicon oxide (SiO). Additionally, the thickness of the pad 125 can be between 0.1 nanometers (nm) and 10 nm.

[0074] Furthermore, the first cap 130 may be formed of the same material as the first inner spacer 112C. In one embodiment, the first cap 130 and the first inner spacer 112C may be formed of, for example, a dielectric material, including, for example, SiC, SiN, SiOCN, SiOC, SiCN, SiO, etc.

[0075] like Figure 1As shown, depending on the height H1 of the space 130r formed within the first cap 130, at least one gap 130g may be formed in the first cap 130 during the deposition of the first cap material. Furthermore, during the deposition of the first cap material, if the height H1 is large, the first cap material may not be able to fill the space 130r, thus forming the gap 130g. However, if the height H1 of the space 130r is sufficiently small, the gap 130g may not be formed. Additionally, the height H1 (or the thickness of the first cap 130) is, for example, between 1 nm and 20 nm.

[0076] like Figure 1 As shown, a trench T1 is formed between two adjacent first active structures 110. A silicon layer 107 is formed in the bottom of the trench T1, and an epitaxial layer 140 is formed on or above the silicon layer 107, and is located between the silicon layer 107 and the contact etch stop layer 150. A conductive portion 145 is electrically connected to the epitaxial layer 140 through an oxide layer 160 and at least one of a first dielectric layer 170A, a second dielectric layer 170B, a third dielectric layer 170C, and a fourth dielectric layer 170D. In this embodiment, the conductive portion 145 may be referred to as "metal over diffusion (MD)". Furthermore, the conductive portion 145 may be formed of a material including, for example, tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), molybdenum (Mo), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0077] like Figure 1 As shown, a contact etch stop layer 150 is formed above the epitaxial layer 140. The contact etch stop layer 150 is formed between the epitaxial layer 140 and the oxide layer 160. The oxide layer 160 is formed on the contact etch stop layer 150. In an embodiment, the contact etch stop layer 150 may be formed of a material including SiO, SiN, SiOC, SiON, or SiOCN.

[0078] like Figure 1As shown, the second active structure 180 includes a plurality of second active channel pieces 181 and a plurality of second metal gate structures 182 stacked vertically to each other. Each second metal gate structure 182 includes a second metal portion 182A and a second high-k dielectric portion 182B, where the second high-k dielectric portion 182B covers the second metal portion 182A, and a second inner spacer 182C covers the side of the second high-k dielectric portion 182B or the second metal portion 182A. In this embodiment, the second high-k dielectric portion 182B includes an upper portion 182B1 covering the upper surface of the second metal portion 182A. In addition, a second cap portion 190 covers the topmost second metal gate structure 182t and the topmost second inner spacer 182C. Further, the second cap portion 190 covers or contacts the upper surface of the second high-k dielectric portion 182B and the upper surface of the second inner spacer 182C. In this embodiment, there is no hole through the second cap portion 190, so the topmost second metal gate structure 182t is not exposed from the second cap portion 190. Further, the second cap portion 190 can have the same or similar gap as the gap 130g of the first cap portion 130. The second cap portion 190 can include the same or similar features (e.g., size, material, and / or structure) as the first cap portion 130.

[0079] In addition, the second metal portion 182A can be formed of the same or similar material as the first metal portion 112A, the second high-k dielectric portion 182B can be formed of the same or similar material as the second metal portion 112B, and the second inner spacer 182C can be formed of the same or similar material as the first inner spacer 112C. In addition, the second metal portion 182A can be formed in the same process as the first metal portion 112A, the second high-k dielectric portion 182B can be formed in the same process as the first high-k dielectric portion 112B, and the second inner spacer 182C can be formed in the same process as the first inner spacer 112C.

[0080] The high-k dielectric portion can be formed of a material including (i) high dielectric constant materials such as hafnium oxide (Hf02), titanium oxide (Ti02), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta203), hafnium silicate (HfSi04), zirconium oxide (Zr02), and zirconium silicate (ZrSi02); and (ii) high dielectric constant materials having oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu); (iii) other suitable high dielectric constant materials; or (iv) combinations thereof. As used herein, the term "high-k" refers to a high dielectric constant. In semiconductor device structures and processes, "high-k" refers to a dielectric constant greater than that of Si02(e.g., greater than 3.9).

[0081] See Figure 2A-2L , which illustrates Figure 1 a process flow for a semiconductor device 100.

[0082] As shown in Figure 2A , a superlattice structure including, for example, sheet layers 111', silicon germanium layers SL, a first spacer layer 113, and a second spacer layer 114 is formed on a substrate 105 using, for example, deposition, where one silicon germanium layer SL is formed between adjacent sheet layers 111' and the first spacer layer 113 is formed between the topmost silicon germanium layer SL and the second spacer layer 114. The sheet layers 111' and the first spacer layer 113 can be formed of a material including, for example, silicon. The sheet layers 111' have a first thickness ti and the first spacer layer 113 has a second thickness t2, where the second thickness t2 is less than the first thickness ti. In one embodiment, the first thickness ti can be, for example, between 5 nanometers (nm) and 15 nm, and the second thickness t2 can be, for example, between 1 nm and 4 nm. Because the first spacer layer 113 is sufficiently thin, it can be removed at the same time as the second spacer layer 114. Further, the second spacer layer 114 can be formed of the same or similar material as the silicon germanium layers SL, such as silicon germanium. In one embodiment, the second spacer layer 114 has a first concentration and the silicon germanium layers SL have a second concentration, where the second concentration is greater than the first concentration to achieve etch selectivity.

[0083] As shown in Figure 2AAs shown, a portion of each sheet layer 111', a portion of each silicon germanium layer SL, a portion of the first spacer layer 113, and a portion of the second spacer layer 114 can be removed to form at least one spacer (not shown) using, for example, etching. The remaining portion of each sheet layer 111', the remaining portion of each silicon germanium layer SL, the remaining portion of the first spacer layer 113, and the remaining portion of the second spacer layer 114 form at least one fin structure along the first direction (e.g., X-axis). The area of one fin structure defines one OD (oxide diffusion) region. The patterned pad oxide layer and the hard mask are then removed by, for example, etching or CMP (chemical mechanical planarization).

[0084] As shown, at least one dummy gate structure DG is formed on the fin structure. The dummy gate structure DG includes an oxide layer DG1, a dummy gate layer DG2, and a shield layer DG3, where the oxide layer DG1 is formed on the fin structure, the dummy gate layer DG2 is formed over the oxide layer DG1, and the shield layer DG3 is formed over the dummy gate layer DG2. In an embodiment, the dummy gate layer DG2 can be deposited over the oxide layer DG1, then planarized, for example, by CMP, and then the shield layer DG3 can be deposited over the dummy gate layer DG2. Figure 2B Figure 2A Additionally, the dummy gate layer can be a conductive or non-conductive material and can be selected from a group including amorphous silicon, polycrystalline-silicon, poly-crystalline silicon-germanium, metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputter deposition, or other deposition techniques for depositing the selected material. The dummy gate layer can be formed of other materials that have a high etch selectivity to the etching of the isolation region. The shield layer can include, for example, silicon nitride, silicon oxynitride, or the like.

[0085] As shown, at least one dummy gate structure DG is formed on the fin structure. The dummy gate structure DG includes an oxide layer DG1, a dummy gate layer DG2, and a shield layer DG3, where the oxide layer DG1 is formed on the fin structure, the dummy gate layer DG2 is formed over the oxide layer DG1, and the shield layer DG3 is formed over the dummy gate layer DG2. In an embodiment, the dummy gate layer DG2 can be deposited over the oxide layer DG1, then planarized, for example, by CMP, and then the shield layer DG3 can be deposited over the dummy gate layer DG2.

[0086] As shown, at least one dummy gate structure DG is formed on the fin structure. The dummy gate structure DG includes an oxide layer DG1, a dummy gate layer DG2, and a shield layer DG3, where the oxide layer DG1 is formed on the fin structure, the dummy gate layer DG2 is formed over the oxide layer DG1, and the shield layer DG3 is formed over the dummy gate layer DG2. In an embodiment, the dummy gate layer DG2 can be deposited over the oxide layer DG1, then planarized, for example, by CMP, and then the shield layer DG3 can be deposited over the dummy gate layer DG2. Figure 2B ​As shown, a spacer layer SP is formed above the side of the dummy gate structure DG using techniques such as deposition.

[0087] Then, as Figure 2B As shown, at least one trench T1 is formed through the dummy gate structure DG, passing through the fin structure and part of the substrate 105, thereby forming at least one first active structure 110' and at least one second active structure 180'. Each first active structure 110' includes a plurality of first active channel sheets 111, a plurality of first silicon-germanium layers 112', a portion of a first spacer layer 113, and a portion of a second spacer layer 114, wherein the first active channel sheets 111 and the first silicon-germanium layers 112' are stacked on top of each other. Similarly, each second active structure 180' includes a plurality of second active channel sheets 181, a plurality of second silicon-germanium layers 182', a portion of a first spacer layer 113, and a portion of a second spacer layer 114, wherein the second active channel sheets 181 and the second silicon-germanium layers 182' are stacked on top of each other.

[0088] Then, as Figure 2C As shown, etching is used to remove... Figure 2B The structure comprises a second spacer layer 114, a first spacer layer 113, a portion of a first silicon-germanium layer 112', and a portion of a second silicon-germanium layer 182'. After removing portions of the first silicon-germanium layer 112' and the second silicon-germanium layer 182', the remaining portion of the first silicon-germanium layer 112' forms a first recess 112r', and the remaining portion of the second silicon-germanium layer 182' forms a second recess 182r'. After removing the second spacer layer 114 and the first spacer layer 113, at least one space 130r is formed, and the space 130r has a height H1. Since the first spacer layer 113 is sufficiently thin, at least a portion of the first spacer layer 113 can be removed simultaneously with the removal of the second spacer layer 114. Furthermore, since the second spacer layer 114 and the silicon-germanium layer SL have different concentrations, the etching rate of the second spacer layer 114 is greater than that of the silicon-germanium layer SL. Therefore, the second spacer layer 114 can be completely removed, but only a portion of the silicon-germanium layer SL is removed.

[0089] Then, as Figure 2DAs shown, the first inner spacer 112C formed in the first recess 112r', the second inner spacer 182C formed in the second recess 182r', the first cap 130 formed in the space 130r, and the second cap 190 formed in the space 130r are formed by, for example, a deposition technique. Depending on the height H1 of the space 130r in which the first cap 130 is formed, the first cap 130 may form at least one gap 130g. Furthermore, during the deposition of the first cap material, if the height H1 is large, the first cap material may not be able to fill the space 130r, thus forming a gap 130g. However, if the height H1 of the space 130r is small enough, the gap 130g may not be formed. In addition, the second cap 190 may also have the same or similar gap as the gap 130g of the first cap 130. The second cap 190 includes the same or similar features (e.g., size, material, and / or structure) as the gap 130g of the first cap 130.

[0090] Then, as Figure 2E As shown, at least one silicon layer 107 is formed at the bottom of the trench T1, and then at least one epitaxial layer 140 is formed on the silicon layer 107 using, for example, epitaxial technology.

[0091] Then, as Figure 2F As shown, etching techniques can be used to remove [the material]. Figure 2E The second silicon-germanium layer 182' and the first silicon-germanium layer 112' are formed to create a plurality of spaces 182a and a plurality of spaces 112a. Alternatively, an etching technique can be used to remove them. Figure 2E The dummy gate structure (DG) shown forms several spatial DGas. The first cap 130 and the first inner spacer 112C protect the topmost first active channel sheet 111t from damage during etching. Similarly, the second cap 190 and the second inner spacer 182C protect the topmost second active channel sheet 181t from damage during etching.

[0092] Then, as Figure 2G As shown, deposition techniques, for example, can be used to form Figure 2F The first high-k dielectric section 112B is formed within space 112a. Figure 2F The second high-k dielectric portion 182B is located within space 182a and forms Figure 2FA high-k dielectric portion HK is formed within the space DGa. Then, for example, a deposition technique can be used to form a first metal portion 112A on the first high-k dielectric portion 112B, a second metal portion 182A on the second high-k dielectric portion 182B, and a metal portion MG on the high-k dielectric portion HK. For example, a deposition technique can be used to form a contact etch stop layer 150 within the trench T1 and above the epitaxial layer 140, and for example, a deposition technique can be used to form an oxide layer 160 above the contact etch stop layer 150. In one embodiment, the contact etch stop layer 150 may be formed before the metal portion MG.

[0093] Then, as Figure 2H As shown, flattening can be achieved using techniques such as CMP. Figure 2G The metal portion MG, the high-k dielectric portion HK, the partial contact etch stop layer 150, and the partial oxide layer 160 are formed. After CMP, the first cap 130 and the second cap 190 are exposed. In another embodiment, the gap 130g can be removed by CMP.

[0094] Then, as Figure 2I As shown, a first dielectric layer 170A can be formed over the first cap 130, the contact etch stop layer 150, the oxide layer 160, and the second cap 190 using, for example, deposition techniques. Then, a second dielectric layer 170B can be formed over the first dielectric layer 170A using, for example, deposition techniques. Then, the second dielectric layer 170B can be formed over the first dielectric layer 170A using, for example, lithography and deposition techniques. Then, a portion 1451 of the conductive portion 145 can be formed through the second dielectric layer 170B, the first dielectric layer 170A, and the oxide layer 160 using, for example, lithography and deposition techniques.

[0095] Then, as Figure 2J As shown, a third dielectric layer 170C can be formed above the second dielectric layer 170B and a fourth dielectric layer 170D can be formed above the third dielectric layer 170C using, for example, deposition techniques. Then, another portion 1452 of the conductive portion 145 can be formed through the third dielectric layer 170C and the fourth dielectric layer 170D using, for example, photolithography techniques. Then, a fifth dielectric layer 170E can be formed above the fourth dielectric layer 170D and the conductive portion 145 using, for example, deposition techniques. A hole 120a can be formed through the fifth dielectric layer 170E, the fourth dielectric layer 170D, the third dielectric layer 170C, the second dielectric layer 170B, the first dielectric layer 170A, the first cap portion 130, and a portion of the first high-k dielectric portion 112B using, for example, photolithography techniques, to expose the topmost first metal gate structure 112t.

[0096] Then, as Figure 2KAs shown, a deposition technique can be used to form a pad 125 covering the sidewalls 120w, wherein the sidewalls 120w include the first sidewalls of the first dielectric layer 170A, the first sidewalls of the second dielectric layer 170B, the first sidewalls of the third dielectric layer 170C, the first sidewalls of the fourth dielectric layer 170D, the first sidewall of the first cap 130, and the first sidewall of the topmost first inner spacer 112C. The sidewalls 120w have a first flatness, and the second sidewalls 125w of the pad 125 have a second flatness, wherein the second flatness is less than the first flatness. Thus, the subsequent conductive portion 120 is formed on or in contact with the simple material (e.g., a single material, or a small variety of materials) and the relatively flat sidewalls of the pad 125, thereby increasing the bonding between the pad 125 and the conductive portion 120.

[0097] Then, as Figure 2L As shown, a deposition technique can be used, for example, to form the conductive portion 120 covering the pad 125, filling the hole 120a and covering the sidewall 120w.

[0098] Then, CMP can be used, for example, to remove a portion of the fifth dielectric layer 170E, a portion of the conductive portion 120, and a portion of the pad 125 to form the semiconductor device 100.

[0099] According to this application, a semiconductor device includes a first active structure formed on a substrate. The first active structure includes a plurality of first active channel wafers and a plurality of first metal gate structures stacked perpendicularly to each other, wherein the topmost first metal gate structure covers the topmost active channel wafer. Thus, the topmost first metal gate structure protects the topmost first active channel wafer, thereby preventing the topmost first active channel wafer from being damaged during the etching process of the dummy gate structure.

[0100] In Embodiment 1, a semiconductor device includes a substrate, a first active structure, a plurality of first inner spacers, a conductive portion, and a first cap. The first active structure is formed on the substrate and includes a plurality of first active channel sheets and a plurality of first metal gate structures stacked perpendicularly to each other. Each first inner spacer is formed on the side of a corresponding first metal gate structure. The conductive portion is connected to the topmost first active channel sheet. The first cap is formed above the topmost first inner spacer and covers the side of the conductive portion.

[0101] In the semiconductor device of Embodiment 2, the semiconductor device further includes a plurality of dielectric layers formed on the first active structure. Conductive portions pass through the dielectric layers and the first cap portion, and the semiconductor device further includes a pad covering the first sidewall of each dielectric layer.

[0102] In the semiconductor device of Embodiment 3, the first sidewall has a first flatness, and the second sidewall of the spacer has a second flatness, the second flatness being less than the first flatness.

[0103] In the semiconductor device of Embodiment 4, the topmost first metal gate structure further includes a first metal portion and a first high-k dielectric portion, the first high-k dielectric portion covering the first metal portion, and the spacer extends to the first metal portion through the first high-k dielectric portion.

[0104] In the semiconductor device of Embodiment 5, the topmost first metal gate structure further includes a first metal portion and a first high-k dielectric portion, the first high-k dielectric portion covering the first metal portion, and the conductive portion extends to the first metal portion through the first high-k dielectric portion.

[0105] In the semiconductor device of Embodiment 6, the first inner spacer protrudes beyond an upper surface of the first metal portion and an upper surface of the first high-k dielectric portion.

[0106] In the semiconductor device of Embodiment 7, the semiconductor device further includes a second active structure, second inner spacers, and a second cap portion. The second active structure is formed on the substrate and includes second active channel pieces and second metal gate structures vertically stacked with each other. Each second inner spacer is formed on a side surface of a corresponding second metal gate structure. The second cap portion covers the topmost second metal gate structure and the topmost second inner spacer.

[0107] In the semiconductor device of Embodiment 8, the topmost second metal gate structure further includes a second metal portion and a second high-k dielectric portion, the second high-k dielectric portion including an upper portion, wherein the upper portion covers an upper surface of the second metal portion.

[0108] In the semiconductor device of Embodiment 9, the first inner spacer is formed of the same material as the first cap portion.

[0109] In the semiconductor device of Embodiment 10, the first cap portion has a thickness between 1 nm and 20 nm.

[0110] In the semiconductor device of Embodiment 11, a semiconductor device includes a substrate, an active structure, inner spacers, and a cap portion. The active structure is formed on the substrate and includes active channel pieces and metal gate structures vertically stacked with each other. Each inner spacer is formed on a side surface of a corresponding metal gate structure. The cap portion covers the topmost inner spacer and a side surface of the conductive portion.

[0111] In the semiconductor device of Embodiment 12, the topmost metal gate structure further includes a high-k dielectric portion and a metal portion surrounding the high-k dielectric portion, and the cap portion further covers the high-k dielectric portion.

[0112] In the semiconductor device of Embodiment 13, the cap portion is in contact with the high-k dielectric portion.

[0113] In the semiconductor device of Embodiment 14, the high-k dielectric portion includes an upper portion, wherein the upper portion covers an upper surface of the second metal portion.

[0114] In the semiconductor device of Embodiment 15, the inner spacer is formed of the same material as the cap portion.

[0115] In the semiconductor device of Embodiment 16, the cap portion has a thickness between 1 nm and 20 nm.

[0116] In the method of manufacturing the semiconductor device of Embodiment 17, the method includes the following steps: forming a first active structure on a substrate, wherein the first active structure includes a plurality of first active channel pieces and a plurality of first metal gate structures stacked vertically to each other; forming a plurality of first inner spacers, wherein each first inner spacer is formed on a side surface of a corresponding first metal gate structure; forming a first cap portion above the first inner spacers; and forming a conductive portion connecting the topmost first active channel piece, wherein the first cap portion covers a side surface of the conductive portion.

[0117] In the method of manufacturing the semiconductor device of Embodiment 18, before forming the conductive portion, the method further includes: forming a plurality of dielectric layers covering the first active structure; forming a hole through the dielectric layers; and forming a liner covering a side wall of the hole.

[0118] In the method of manufacturing the semiconductor device of Embodiment 19, the first cap portion and the first inner spacer can be formed in the same process.

[0119] In the method of manufacturing the semiconductor device of Embodiment 20, the method further includes: forming a superlattice structure on the substrate, wherein the superlattice structure includes a plurality of slice layers, a plurality of silicon germanium layers, a first spacer layer, and a second spacer layer, one of the silicon germanium layers is formed between two adjacent silicon germanium layers, and the first spacer layer is formed between the topmost silicon germanium layer and the second spacer layer; removing the first spacer layer and the second spacer layer to form a space; and forming the first cap portion in the space.

[0120] In summary, although the present application has been disclosed with embodiments as above, it is not intended to limit the present application. Those skilled in the art to which the present application pertains, without departing from the spirit and scope of the present application, can make various modifications and decorations. Therefore, the protection scope of the present application is defined by the patent scope.

Claims

1. A semiconductor device, characterized in that, include: One substrate; A first active structure is formed on the substrate and includes a plurality of first active channel sheets and a plurality of first metal gate structures stacked perpendicularly to each other; Several first inner spacers are each formed on one side of the corresponding first metal gate structure; A conductive part is connected to the topmost first active channel plate; as well as A first cap is formed above the topmost first inner spacer and covers one side of the conductive portion.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Several dielectric layers are formed on the first active structure; The conductive portion passes through the plurality of dielectric layers and the first cap portion, and the semiconductor device further includes: A pad covers a first sidewall of each of the dielectric layers.

3. The semiconductor device as claimed in claim 2, characterized in that, The plurality of first sidewalls have a first flatness, and a second sidewall of the pad has a second flatness, the second flatness being less than the first flatness.

4. The semiconductor device as claimed in claim 2, characterized in that, The topmost first metal gate structure also includes: A first metal part; and A first high-k dielectric portion covers the first metal portion; The pad extends from the first high-k dielectric portion to the first metal portion, where k is the dielectric constant.

5. The semiconductor device as claimed in claim 1, characterized in that, The topmost first metal gate structure also includes: A first metal part; and A first high-k dielectric portion covers the first metal portion; The conductive portion extends to the first metal portion through the first high-k dielectric portion, where k is the dielectric constant.

6. The semiconductor device as claimed in claim 5, characterized in that, The first inner spacer protrudes beyond an upper surface of the first metal portion and an upper surface of the first high-k dielectric portion.

7. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A second active structure is formed on the substrate and includes several second active channel sheets and several second metal gate structures stacked perpendicularly to each other; Several second inner spacers are each formed on one side of the corresponding second metal gate structure; as well as A second cap covers the topmost second metal gate structure and the topmost second inner spacer.

8. The semiconductor device as claimed in claim 7, characterized in that, The topmost second metal gate structure also includes: A second metal part; and A second high-k dielectric portion includes an upper portion, characterized in that the upper portion covers an upper surface of the second metal portion.

9. The semiconductor device as claimed in claim 1, characterized in that, The first inner spacer is formed of the same material as the first cap.

10. The semiconductor device as claimed in claim 1, characterized in that, The first cap has a thickness between 1 nanometer and 20 nanometers.

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