Layout structure of semiconductor device
By designing the second portion of the second gate in the LDMOS device layout to be located on the semiconductor substrate on one side of the sidewall structure, and placing the first gate plug outside the area of the sidewall structure, the problem of etching through the second gate is solved, thus improving product yield.
Patent Information
- Application Number
- CN202423116446.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-12-17
AI Technical Summary
In the manufacturing process of LDMOS devices, the etching of the gate electrical connection hole can easily penetrate the second gate, leading to a decrease in the yield of semiconductor device products.
Design a semiconductor device layout structure in which the second gate includes a first part and a second part, and the first gate plug is located on the second part and outside the area of the sidewall structure to avoid penetration of the second gate during etching.
By controlling the etching process, the product yield of semiconductor devices has been improved.
Smart Images
Figure CN223567993U_ABST
Abstract
Description
Technical Field
[0005]
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a layout structure of a semiconductor device. Background Art
[0002] In the manufacturing process of a lateral diffused metal oxide semiconductor field effect transistor (LDMOS) in a power management integrated circuit (PMIC), there is a gate electrical connection hole located on a slope, which easily causes etching to penetrate the gate, affecting the product yield of semiconductor devices. Figure 1 For a schematic diagram of the layout structure of an LDMOS device in the prior art, please refer to Figure 1 , Figure 1 Only the structures related to the background art are marked in
[0003] Figure 2 ; the other structures are not described here. The first gate 200 is located on a semiconductor substrate 100, and a sidewall structure 300 covers the side surface of the first gate 200. The surface of the sidewall structure 200 is inclined. The second gate 400 is at least located on a part of the first gate 200 and the sidewall structure 300. Since the surface of the sidewall structure 200 is inclined, the surface of the second gate 400 above the sidewall structure 300 is inclined (showing a slope morphology). When preparing an interconnect structure, a gate plug 500 needs to be formed above the sidewall structure 300. Specifically, the dielectric layer covering the second gate 400 is etched to form a gate electrical connection hole exposing the second gate 400 above the sidewall structure 300, and then metal is filled in the gate electrical connection hole to obtain the gate plug 500. However, due to the inclined surface of the second gate 400 above the sidewall structure 300, it is difficult to control the etching process during the manufacturing process to ensure that the bottom of the gate electrical connection hole located on the slope can stop well on the second gate 400, resulting in easy etching through the second gate 400 when forming the gate electrical connection hole, affecting the product yield of semiconductor devices. <In order to achieve the above object, the utility model provides a kind of semiconductor device layout structure, comprising:
[0006] Semiconductor substrate;
[0007] First gate, on the semiconductor substrate;
[0008] Side wall structure, on the semiconductor substrate and on the side of the first gate;
[0009] Second gate, including first part and second part, the first part is on part the first gate and part the side wall structure, the second part is connected with the side of one end of the first part, and the second part is on the semiconductor substrate on one side of the side wall structure;
[0010] First gate plug, on the second part and on the area outside the side wall structure.
[0011] Optionally, the first gate plug and the side wall structure adjacent one side are aligned or have gap.
[0012] Optionally, the second gate further includes third part, the third part is connected with one side of the first part and is connected with the second part, and the third part is on the semiconductor substrate on one side of the side wall structure.
[0013] Optionally, the size of the third part along X direction is less than the size of the second part along X direction.
[0014] Optionally, the first gate, the side wall structure and the second gate all extend along Y direction, and the size of the second gate along Y direction is less than the size of the first gate and the side wall structure along Y direction.
[0015] Optionally, the second part has first protruding repair block and second protruding repair block respectively at two ends away from one side of the first part.
[0016] Optionally, the semiconductor substrate includes active region extending along X direction, and the first gate, the side wall structure and the second gate all cross the active region along Y direction, and the size of the active region along Y direction is less than the size of the second gate along Y direction.
[0017] Optionally, the second part is located in the area outside the active region, the first protruding repair block is close to the active region, and the second protruding repair block is away from the active region.
[0018] Optionally, the first protruding repair block and the active region adjacent one side are aligned or have gap.
[0019] Optionally, the area of the second protruding repair block is 1.5 to 3 times the area of the first protruding repair block.
[0020] In the semiconductor device layout structure, the first gate is located on the semiconductor substrate, and the side wall structure is located on the semiconductor substrate and at the side of the first gate; the second gate comprises a first part and a second part, the first part is located on part of the first gate and part of the side wall structure, the second part is connected with the side of one end of the first part, and the second part is located on the semiconductor substrate on one side of the side wall structure; the first gate plug is located on the second part and outside the area of the side wall structure. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 It is a layout structure schematic diagram of an LDMOS device in the prior art.
[0022] Figure 2 It is a partial electron microscope diagram of an LDMOS device in the prior art.
[0023] Figure 3 It is a layout structure schematic diagram of a semiconductor device provided by an embodiment of the utility model.
[0024] Figure 4 It is a partial electron microscope diagram of a semiconductor device prepared by a layout structure of a semiconductor device provided by an embodiment of the utility model.
[0025] Wherein, Figure 1 The reference signs in the drawings are as follows:
[0026] 100-semiconductor substrate; 200-first gate; 300-side wall structure; 400-second gate; 500-gate plug.
[0027] Figure 3 The reference signs in the drawings are as follows:
[0028] 10-semiconductor substrate; 12-active region; 20-first gate; 30-side wall structure; 40-second gate; 41-first part; 42-second part; 43-third part; 42a-first protruding repair block; 42b-second protruding repair block; 51-first gate plug; 52-second gate plug; 53-doped region plug. DETAILED DESCRIPTION
[0029] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.
[0030] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.
[0031] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly understood by those skilled in the art, and are only for the convenience of describing the present application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0032] In addition, the relational terms such as "first" and "second" and the like are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the article or device including the element. The specific meaning of the above terms in the present application can be understood by the person of ordinary skill in the art on a case-by-case basis.
[0033] Figure 3 A schematic diagram of a semiconductor device layout structure is provided for the embodiments. Please refer to Figure 3 The present embodiment provides a semiconductor device layout structure, and the semiconductor device of the present embodiment is preferably an LDMOS device, Figure 3Two LDMOS devices are exemplified in the following examples, which are symmetrically arranged, and the number of LDMOS devices is not limited. The semiconductor device layout structure comprises a semiconductor substrate 10, a first gate 20, a side wall structure 30, a second gate 40 and a first gate plug 51, wherein the semiconductor substrate 10 comprises an active region 12 therein, and the active region 12 extends along the X direction.
[0034] The first gate 20 is located on the semiconductor substrate 10, and the first gate 20 extends along the Y direction. A plurality of first gates 20 are arranged along the X direction, and the plurality of first gates 20 span the active region 12. The size (extension length) of the first gate 20 along the Y direction is greater than the size of the active region 12 along the Y direction, and the first gate 20 is in the shape of a rectangular strip. In addition, there is a gate oxide layer (not shown in the figure) between the first gate 20 and the semiconductor substrate 10.
[0035] The side wall structure 30 is located on the semiconductor substrate 10 and on the side of the extension direction (Y direction) of the first gate 20 (covering both sides of the first gate 20), and the size of the side wall structure 30 along the Y direction is the same as the size of the first gate 20 along the Y direction.
[0036] The second gate 40 comprises a first part 41 and a second part 42. The first part 41 extends along the Y direction, and the size (extension length) of the first part 41 along the Y direction is less than the size (extension length) of the first gate 20 and the side wall structure 30 along the Y direction. The first part 41 is located on part of the first gate 20 and part of the side wall structure 30. Specifically, along the X direction, the first part 41 is located on the side wall structure 30 on one side of the first gate 20 and extends on part of the first gate 20, and the first part 41 is in the shape of a rectangular strip.
[0037] The second part 42 is connected to the side (the side away from the first gate 20) of one end of the first part 41, and the second part 42 is located on the semiconductor substrate 10 on one side of the side wall structure 30. The second gate 40 further comprises a third part 43, which is connected to one side (the side away from the first gate 20) of the first part 41 and connected to the second part 42. The third part 43 is located on the semiconductor substrate 10 on one side of the side wall structure 20. The size of the third part 43 along the X direction is less than the size of the second part 42 along the X direction. In this embodiment, the first gate 20, the side wall structure 30 and the second gate 40 all extend along the Y direction, and the size of the second gate 40 along the Y direction is less than the size of the first gate 20 and the side wall structure 30 along the Y direction. In addition, the first gate 20, the side wall structure 30 and the second gate 40 all span the active region 12 along the Y direction, and the size of the active region 12 along the Y direction is less than the size of the second gate 40 along the Y direction.
[0038] In this embodiment, since after forming polysilicon when preparing the second gate 40, part of the polysilicon needs to be blocked by photoresist and then patterned, there may be a situation of inner shrinkage fillets caused by yellow light behavior, resulting in insufficient size of the second part 42 of the second gate 40, making it difficult to fabricate the first gate plug 51 on the second part 42. Therefore, optical correction (i.e., OPC compensation) needs to be performed according to the size of the second part 42, so that both ends of the second part 42 far from the first part 41 respectively have a first protruding repair block 42a and a second protruding repair block 42b. In this embodiment, the second part 42 is located outside the region of the active region 12, that is, when viewed from above ( Figure 3 ), the second part 42 and the active region 12 are arranged in a misaligned manner. The first protruding repair block 42a is close to the active region 12, and the second protruding repair block 42b is far from the active region 1. One side of the first protruding repair block 42a adjacent to the active region 12 is aligned or has a gap. Specifically, one side of the first protruding repair block 42a close to the active region 12 is aligned or has a gap with one side of the active region 12 close to the first protruding repair block 42a. As shown in Figure 2 , there is a gap between one side of the first protruding repair block 42a adjacent to the active region 12; and in order to meet the requirements of optical correction, the area of the second protruding repair block 42b is 1.5 to 3 times the area of the first protruding repair block 42a, preferably 2 times.
[0039] The first gate plug 51 is located on the second part 42 and is electrically connected to the second gate 40, and the first gate plug 51 is located outside the region of the sidewall structure 30, that is, when viewed from above ( Figure 3 ), the first gate plug 51 and the sidewall structure 30 are arranged in a misaligned manner; one side of the first gate plug 51 adjacent to the sidewall structure 30 is aligned or has a gap. Specifically, one side of the first gate plug 51 close to the sidewall structure 30 is aligned or has a gap with one side of the sidewall structure 30 close to the first gate plug 51. As shown in Figure 3 , there is a gap between one side of the first gate plug 51 adjacent to the sidewall structure 30, and the number of the first gate plugs 51 is not limited.
[0040] Furthermore, it further includes a second gate plug 52 and a doping region plug 53. The second gate plug 52 is located on the first gate 20 and is electrically connected to the first gate 20; several doping regions (not shown in the figure), such as source regions and drain regions, are formed in the active region 12, and the doping region plug 53 is located on the doping region and is electrically connected to the doping region.
[0041] Figure 4 This is a partial electron microscope image of the semiconductor device obtained by fabricating the semiconductor device layout structure provided in this embodiment. Please refer to Figure 4 , Figure 4The middle slope position corresponds to the side wall structure and part of the second gate electrode, the surface of the side wall structure is inclined, which causes the surface of the second gate electrode above the side wall structure to be inclined (in a slope morphology), the light-colored vertical part on one side of the slope is a first gate electrode electric connection hole, the bottom of the first gate electrode electric connection hole is the second gate electrode (a dark layer), Figure 4 The middle has not been filled with metal, and the first gate electrode plug is obtained after the metal is filled in the first gate electrode electric connection hole. Figure 4 As shown in the circular dashed box, it can be seen that the bottom of the first gate electrode electric connection hole is misaligned with the side wall structure (not falling on the slope), the bottom of the first gate electrode electric connection hole is located on the plane of the semiconductor substrate, the etching process is easier to control when the first gate electrode electric connection hole is etched, and the second gate electrode is not easily etched through, thereby improving the product yield of the semiconductor device.
[0042] In summary, in the semiconductor device layout structure provided by the utility model, including semiconductor substrate, first gate electrode, side wall structure, second gate electrode and first gate electrode plug, the first gate electrode is located on the semiconductor substrate, the side wall structure is located on the semiconductor substrate and the side of the first gate electrode; the second gate electrode includes a first part and a second part, the first part is located on part of the first gate electrode and part of the side wall structure, the second part is connected with the side of one end of the first part, and the second part is located on the semiconductor substrate on one side of the side wall structure; the first gate electrode plug is located on the second part and outside the area of the side wall structure. The utility model discloses a second part of the second gate electrode is located on the semiconductor substrate on one side of the side wall structure, and the first gate electrode plug is located on the second part and outside the area of the side wall structure, which can make the bottom of the first gate electrode plug located on the plane of the semiconductor substrate, avoid the bottom of the first gate electrode plug located on the side wall structure, and more easily control the etching process when the first gate electrode plug is prepared, and the second gate electrode is not easily etched through, thereby improving the product yield of the semiconductor device.
[0043] The above is only the preferred embodiment of the utility model, and does not have any limiting effect on the utility model. Any person skilled in the art, without departing from the technical scheme of the utility model, makes any form of equivalent replacement or modification of the technical scheme and technical content disclosed by the utility model, and the like, which all belong to the content of the technical scheme of the utility model, and still belong to the protection scope of the utility model.
Claims
1. A semiconductor device layout structure, characterized in that, include: Semiconductor substrate; A first gate is located on the semiconductor substrate; A sidewall structure is located on the semiconductor substrate and on the side of the first gate; The second gate includes a first portion and a second portion, the first portion being located on a portion of the first gate and a portion of the sidewall structure, the second portion being connected to a side of one end of the first portion, and the second portion being located on the semiconductor substrate on one side of the sidewall structure; The first gate plug is located on the second portion and outside the area of the sidewall structure.
2. The semiconductor device layout structure as described in claim 1, characterized in that, The first gate plug and the sidewall structure adjacent to each other are aligned or have a gap.
3. The semiconductor device layout structure as described in claim 1, characterized in that, The second gate further includes a third portion connected to one side of the first portion and connected to the second portion, the third portion being located on the semiconductor substrate on one side of the sidewall structure.
4. The semiconductor device layout structure as described in claim 3, characterized in that, The dimension of the third part along the X direction is smaller than the dimension of the second part along the X direction.
5. The semiconductor device layout structure as described in claim 1, characterized in that, The first gate, the sidewall structure, and the second gate all extend along the Y direction, and the dimension of the second gate along the Y direction is smaller than the dimensions of the first gate and the sidewall structure along the Y direction.
6. The semiconductor device layout structure as described in claim 1, characterized in that, The second part has a first protruding repair block and a second protruding repair block at its two ends on the side away from the first part.
7. The semiconductor device layout structure as described in claim 6, characterized in that, The semiconductor substrate includes an active region extending along the X direction, and the first gate, the sidewall structure, and the second gate all cross the active region along the Y direction. The dimension of the active region along the Y direction is smaller than the dimension of the second gate along the Y direction.
8. The semiconductor device layout structure as described in claim 7, characterized in that, The second part is located outside the active region, the first protruding repair block is close to the active region, and the second protruding repair block is far from the active region.
9. The semiconductor device layout structure as described in claim 8, characterized in that, The first protruding repair block is aligned with or has a gap on the side adjacent to the active region.
10. The semiconductor device layout structure as described in claim 8, characterized in that, The area of the second protruding repair block is 1.5 to 3 times the area of the first protruding repair block.