Heterojunction epitaxial chip for wafer thinning
By setting a buffer layer in the epitaxial structure to form reverse stress, the problem of epitaxial layer warpage is solved, and the flatness of the epitaxial chip and the convenience of wafer bonding are achieved.
Patent Information
- Application Number
- CN202422867553.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-11-22
AI Technical Summary
In existing heterojunction epitaxial structures, the difference in thermal expansion coefficients between the epitaxial wafer and the substrate material causes the epitaxial layer to warp when the temperature changes, affecting the stability of the epitaxial chip and increasing the wafer thickness.
A buffer layer is provided between the substrate and the epitaxial functional layer. The buffer layer consists of multiple composite buffer layers. Each composite buffer layer includes at least two sub-buffer layers with different lattice constants. The sub-buffer layers are arranged along a predetermined direction to form a reverse stress to counteract the warping stress of the epitaxial layer.
By reducing or eliminating the warpage of the epitaxial layer through reverse stress, the overall thickness of the wafer is reduced, the flatness of the epitaxial functional layer is improved, and the bonding and matching during wafer bonding is facilitated.
Smart Images
Figure CN223568006U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of semiconductor, especially a kind of for wafer thinning heterojunction epitaxial chip. BACKGROUND
[0002] In the existing heterojunction epitaxial structure, due to the difference in thermal expansion coefficient between the epitaxial wafer and the substrate material, after high-temperature preparation, as the temperature decreases, the epitaxial layer is strained in the in-plane stretching direction or the compression direction, while the substrate near the surface is strained in the opposite in-plane compression direction or stretching direction. The epitaxial layer with stress tries to return to its inherent crystal under the action of restoring force, resulting in the formation of a surface concave or convex structure in the epitaxial layer, which affects the stability of the epitaxial chip and increases the thickness of the overall wafer.
[0003] Therefore, how to provide an epitaxial chip with improved warping of the formed surface, and avoid the problem of not being able to fit when bonding two wafers, is a problem that needs to be solved by those skilled in the art. SUMMARY
[0004] Therefore, the utility model provides a kind of for wafer thinning heterojunction epitaxial chip, solves the problem of the epitaxial layer in the prior art forming a surface concave or convex structure, affecting the stability of the epitaxial chip, and increasing the thickness of the overall wafer.
[0005] To solve the above technical problems, the utility model provides a kind of for wafer thinning heterojunction epitaxial chip, comprising:
[0006] a substrate, a buffer layer and an epitaxial functional layer, the buffer layer is located between the substrate and the epitaxial functional layer;
[0007] The buffer layer includes a plurality of composite buffer layers arranged in a predetermined direction, each composite buffer layer includes at least two sub-buffer layers with different lattice constants; the predetermined direction is the direction of the substrate pointing to the epitaxial functional layer;
[0008] In each composite buffer layer, the lattice constants of the plurality of sub-buffer layers increase or decrease along the predetermined direction, forming a reverse stress, and the direction of the reverse stress is opposite to the direction of the stress that causes the epitaxial functional layer to warp.
[0009] Optionally, each composite buffer layer is the same.
[0010] Optionally, the substrate is a silicon substrate;
[0011] The epitaxial functional layer is a gallium nitride epitaxial functional layer.
[0012] Optionally, each of the composite buffer layers is formed by aluminum nitride layers and gallium nitride layers arranged along the preset direction.
[0013] Optionally, the thickness of the aluminum nitride layer in each of the composite buffer layers is 3-10 nm.
[0014] The thickness of the gallium nitride layer in each of the composite buffer layers is 10-30 nm.
[0015] Optionally, the total thickness of the buffer layer formed by the aluminum nitride layers and the gallium nitride layers alternately arranged along the preset direction is 2.5-5 μm.
[0016] Optionally, the thickness of the aluminum nitride layer is 5 nm, and the thickness of the gallium nitride layer is 20 nm.
[0017] Optionally, each of the composite buffer layers comprises at least two of an aluminum nitride layer, an aluminum gallium nitride layer and a gallium nitride layer.
[0018] Optionally, each of the composite buffer layers is formed by aluminum nitride layers, aluminum gallium nitride layers and gallium nitride layers arranged along the preset direction.
[0019] Optionally, in each of the composite buffer layers, the lattice constants of the plurality of sub-buffer layers increase or decrease along the preset direction, forming the reverse stress, and the resultant force of the reverse stress and the stress causing the warping of the epitaxial functional layer is zero.
[0020] It can be seen that the heterojunction epitaxial chip for wafer thinning provided by the utility model comprises a substrate, a buffer layer and an epitaxial functional layer, the buffer layer is located between the substrate and the epitaxial functional layer, the buffer layer comprises a plurality of composite buffer layers arranged along a preset direction, each of the composite buffer layers comprises at least two sub-buffer layers with different lattice constants, the preset direction is the direction in which the substrate points to the epitaxial functional layer, in each of the composite buffer layers, the lattice constants of the plurality of sub-buffer layers gradually increase or decrease along the preset direction, forming a reverse stress, and the direction of the reverse stress is opposite to the direction of the stress causing the warping of the epitaxial functional layer. The utility model gradually increases or decreases the lattice constants of the plurality of sub-buffer layers in each of the composite buffer layers along the preset direction, so that the resultant force of the reverse stress formed by the buffer layer and the stress causing the warping of the epitaxial functional layer is smaller than the stress causing the warping of the epitaxial functional layer, thereby weakening or eliminating the warping between the epitaxial functional layer and the substrate caused by the different thermal expansion coefficients of materials, reducing the overall thickness of the wafer, improving the flatness of the epitaxial functional layer, and facilitating the matching degree of wafer bonding. BRIEF DESCRIPTION OF DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only the embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.
[0022] Figure 1 A structure schematic diagram of a heterojunction epitaxial chip for wafer thinning is provided for the embodiments of the present application.
[0023] Figure 2 A before-and-after comparison example diagram of the existing heterojunction epitaxial chip changing with temperature is provided for the embodiments of the present application.
[0024] Figure 3 A before-and-after comparison example diagram of the heterojunction epitaxial chip for wafer thinning changing with temperature is provided for the embodiments of the present application.
[0025] Figure 4 A micro example diagram of the buffer layer in the heterojunction epitaxial chip for wafer thinning is provided for the embodiments of the present application.
[0026] Figure 5 A structure schematic diagram of the heterojunction epitaxial chip in the existing LED device is provided for the embodiments of the present application.
[0027] Figure 6 A structure schematic diagram of the heterojunction epitaxial chip for wafer thinning in the LED device is provided for the embodiments of the present application.
[0028] Figures 1 to 3 , and Figure 5 and Figure 6 The reference signs in the drawings are as follows:
[0029] 1-silicon substrate, 2-buffer layer in the existing epitaxial chip, 3-gallium nitride epitaxial layer with existing tensile stress, 4-light emitting quantum well, 5-P-type gallium nitride layer;
[0030] 10-substrate, 20-buffer layer, 21-composite buffer layer, 211-aluminum nitride layer, 212-gallium nitride layer, 30-epitaxial functional layer;
[0031] h-bending degree of the silicon wafer. DETAILED DESCRIPTION
[0032] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0033] Embodiment 1
[0034] Please refer to Figure 1 , Figure 1 A structure schematic diagram of a heterojunction epitaxial chip for wafer thinning is provided in the embodiments of the present application. The heterojunction epitaxial chip can include:
[0035] a substrate 10, a buffer layer 20 and an epitaxial functional layer 30, the buffer layer 20 being located between the substrate 10 and the epitaxial functional layer 30;
[0036] The buffer layer 20 includes a plurality of composite buffer layers 21 arranged along a preset direction, each composite buffer layer 21 including at least two sub-buffer layers with different lattice constants; the preset direction is a direction in which the substrate 10 points to the epitaxial functional layer 30;
[0037] In each composite buffer layer 21, the lattice constants of the plurality of sub-buffer layers increase or decrease along the preset direction, forming a reverse stress, and the direction of the reverse stress is opposite to the direction of the stress that causes the epitaxial functional layer 30 to warp.
[0038] It needs to be explained that the embodiment is applicable to a heterojunction epitaxial chip, since in the heterojunction epitaxial chip, the epitaxial functional layer 30 is grown from the substrate 10, and since the thermal expansion coefficients between the epitaxial functional layer 30 and the substrate 10 material are different, and the epitaxial chip is prepared and grown at high temperature, after the epitaxial functional layer 30 is prepared and grown, as the temperature decreases, the epitaxial functional layer 30 is strained due to the stress existing in the plane, and then warping is generated, therefore in the present application, a plurality of composite buffer layers 21 arranged in the direction of the substrate 10 pointing to the epitaxial functional layer 30 are provided, and each composite buffer layer 21 includes at least two sub-buffer layers with different lattice constants, and in each composite buffer layer 21, the lattice constants of the plurality of sub-buffer layers gradually increase or decrease in the direction of the substrate 10 pointing to the epitaxial functional layer 30, forming a reverse stress, and the direction of the reverse stress is opposite to the direction of the stress causing the epitaxial functional layer 30 to warp, so as to weaken the warping of part of the epitaxial functional layer 30, or make the epitaxial functional layer 30 flat. It needs to be further explained that in the embodiment, the lattice constants of the plurality of sub-buffer layers gradually increase or decrease in the preset direction, forming a reverse stress, which causes the buffer layer 20 to warp on the surface, and then the epitaxial functional layer 30 is grown, at this time, the epitaxial functional layer 30 grown has the same direction of warping as the buffer layer 20, and when the temperature decreases after the growth is completed, the epitaxial functional layer 30 generates stress due to the difference in thermal expansion coefficient with the substrate 10 material, and shows a deformation opposite to the direction of the warping caused by the buffer layer 20, thereby reducing the warping degree of the finally formed epitaxial functional layer 30, that is, the present application generates a reverse warping deformation by setting the buffer layer 20, which offsets at least part of the warping deformation of the epitaxial functional layer 30 itself due to the difference in thermal expansion coefficient with the substrate 10 material, improves the flatness of the epitaxial functional layer 30 prepared finally, and then reduces the total thickness of the wafer, and improves the convenience of wafer bonding.
[0039] In the embodiment, generally, the epitaxial functional layer 30 prepared on the substrate 10 will be strained in the in-plane tensile direction when the temperature decreases due to the difference in thermal expansion coefficient between the epitaxial functional layer 30 and the substrate 10 material, and the near-surface of the substrate 10 is strained in the in-plane compression direction, and the epitaxial functional layer 30 with stress generates a restoring force in the in-plane shrinkage direction to try to restore its inherent crystal, thus forming a concave structure at room temperature, and correspondingly, the buffer layer 20 in the present application can be set as a convex structure to ensure that the concave degree of the epitaxial functional layer 30 is finally weakened or eliminated.
[0040] It should be noted that when the lattice constants of the plurality of sub-buffer layers are set to increase in the direction in which the substrate 10 points to the epitaxial functional layer 30 in the embodiment, the sub-buffer layer grown in pseudo-crystal form on the upper layer is strained in the in-plane compression direction, thereby generating a restoring force in the in-plane expansion direction, and the plurality of sub-buffer layers finally form a warped structure that is convex upward. Correspondingly, when the lattice constants of the plurality of sub-buffer layers are set to decrease in the direction in which the substrate 10 points to the epitaxial functional layer 30 in the embodiment, the sub-buffer layer grown in pseudo-crystal form on the upper layer is strained in the in-plane expansion direction, thereby generating a restoring force in the in-plane compression direction, and the plurality of sub-buffer layers finally form a warped structure that is concave downward.
[0041] It should be noted that the embodiment needs to ensure that each composite buffer layer 21 includes two or more sub-buffer layers with different lattice constants, for example, to ensure the preparation efficiency, each composite buffer layer 21 can be set to include only two sub-buffer layers with different lattice constants, or each composite buffer layer 21 can be set to include only three sub-buffer layers with different lattice constants. In addition, the number of composite buffer layers 21 included in the buffer layer 20 in the embodiment can also be set according to the degree of warping required, that is, by controlling the number of composite buffer layers 21 in the buffer layer 20, the flatness of the finally formed epitaxial functional layer 30 can be controlled.
[0042] Further, in a feasible implementation, in order to ensure the adaptability of the heterojunction epitaxial wafer for wafer thinning, the substrate 10 can be set as a silicon substrate.
[0043] The epitaxial functional layer 30 is a gallium nitride epitaxial functional layer.
[0044] It should be noted that the substrate 10 is set as a silicon substrate and the epitaxial functional layer 30 is set as a gallium nitride epitaxial functional layer in the embodiment, which is suitable for a conventional heterojunction epitaxial wafer. In addition, the wafer warping in the conventional heterostructure epitaxial wafer in the embodiment is mainly caused by the difference in the coefficient of thermal expansion (CTE) between the epitaxial functional layer 30 and the substrate 10. The CTE value of GaN (gallium nitride) at high temperature (Tg) is more than 1.5 times that of Si (silicon). Therefore, when the GaN epitaxial layer is grown at high temperature and small strain on the Si substrate, as the temperature decreases, the GaN epitaxial layer is strained in the in-plane stretching direction, and the near-surface of the Si substrate is strained in the in-plane compression direction. Then, the epitaxial layer with stress generates a restoring force in the in-plane contraction direction to try to return to its inherent crystal. Therefore, the GaN-on-Si epitaxial wafer forms a concave shape at about room temperature (RT). In addition, if the residual in-plane strain in the epitaxial layer exceeds the elastic limit of gallium nitride, the epitaxial layer will crack. That is, the buffer layer in the present application is suitable for optimizing the surface flatness of the GaN-on-Si epitaxial wafer. Please refer to Figure 2 andFigure 3 , Figure 2 is a front and back comparison example graph of a heterojunction epitaxial chip changing with temperature for an existing epitaxial wafer; Figure 3 is a front and back comparison example graph of a heterojunction epitaxial chip changing with temperature for an existing epitaxial wafer provided by the embodiment of the utility model. Wherein the GaN layer is a gallium nitride layer, the Si layer is a silicon substrate, at Tg is at high temperature, at RT is at room temperature, the bending degree of the silicon wafer is marked at h in the figure, and the arrow indicates the direction to indicate the in-plane stress direction in the corresponding layer. Figure 2
[0045] Further, in order to ensure the convenience of preparation of the composite buffer layer 21, and at the same time be compatible with the epitaxial wafer grown on the silicon as described above, it can be provided that each composite buffer layer 21 is formed by an aluminum nitride layer 211 and a gallium nitride layer 212 arranged in a predetermined direction.
[0046] It should be noted that each composite buffer layer 21 is formed by an aluminum nitride layer 211 and a gallium nitride layer 212 arranged in a predetermined direction, and the buffer layer 20 formed by the composite buffer layer 21 grows under in-plane compressive stress at high temperature (Tg), which will generate a force in the in-plane expansion direction, thereby offsetting the wafer warpage. Specifically, when the GaN layer 212 is grown pseudomorphically on the AlN (aluminum nitride) layer 211, and the AlN layer 211 is partially relaxed on the GaN layer 212, some misfit dislocations are introduced. Essentially, the in-plane lattice constant of the GaN layer 212 is greater than that of the AlN layer 211. Therefore, in this case, the pseudomorphically grown GaN layer 212 should be strained in the in-plane compression direction, thereby generating a restoring force in the in-plane expansion direction, and the buffer layer 20 formed by the multilayer composite buffer layer 21 can achieve sufficient restoring force to reduce epitaxial warpage. Reference can be made to Figure 4 , Figure 4 is a micro example graph of a buffer layer in a heterojunction epitaxial chip for wafer thinning provided by the embodiment of the utility model.
[0047] Further, in order to ensure the stability and functionality of each composite buffer layer 21, the thickness of the aluminum nitride layer 211 in each composite buffer layer 21 can be set to 3-10 nanometers.
[0048] The thickness of the gallium nitride layer 212 in each composite buffer layer 21 is 10-30 nanometers.
[0049] In the embodiment, the thickness of the aluminum nitride layer 211 in each composite buffer layer 21 is set to 3-10 nanometers, and the thickness of the gallium nitride layer 212 is set to 10-30 nanometers, which can ensure the stability of each composite buffer layer 21, and at the same time, ensure that each composite buffer layer 21 will not crack and be damaged when warping occurs, and facilitate control of the flatness of the epitaxial wafer formed by the buffer layer 20 and the epitaxial functional layer 30.
[0050] Further, in order to improve the flatness of the final formed epitaxial chip, the total thickness of the buffer layer 20 formed by the alternating arrangement of the aluminum nitride layer 211 and the gallium nitride layer 212 in the preset direction can be set to 2.5 microns to 5 microns.
[0051] It should be noted that the total thickness of the buffer layer 20 in the embodiment is set to 2.5 microns to 5 microns, which can ensure the degree of warping of the formed buffer layer 20, and further ensure the flatness of the final formed epitaxial chip. In addition, it should be noted that the deformation stress generated in a single composite buffer layer 21 is not very large, however, the deformation stress in the buffer layer 20 formed by stacking hundreds of pairs of GaN layers 212 and AlN layers 211 can reduce the epitaxial warping, and can ensure the flatness of the formed epitaxial chip.
[0052] Further, in order to ensure the functionality of the composite buffer layer 21, the thickness of the aluminum nitride layer 211 can be set to 5 nanometers, and the thickness of the gallium nitride layer 212 can be set to 20 nanometers.
[0053] Further, in order to ensure the yield of the final formed epitaxial chip and improve the yield of wafer bonding, the lattice constant of each of the plurality of sub-buffer layers in the composite buffer layer 21 can be gradually increased or decreased in the preset direction, forming a reverse stress, and the resultant force of the reverse stress and the stress causing the epitaxial functional layer 30 to warp is zero.
[0054] In the embodiment, by precisely controlling the thickness and type of the plurality of sub-buffer layers in each composite buffer layer 21, and simultaneously precisely controlling the number or thickness of the composite buffer layer 21 in the buffer layer 20, the resultant force of the reverse stress formed in the final buffer layer 20 and the stress causing the epitaxial functional layer 30 to warp is zero, so that the final formed epitaxial functional layer 30 forms a flat surface without considering errors.
[0055] Further, in a feasible embodiment, each composite buffer layer 21 can include at least two of an aluminum nitride layer, an aluminum gallium nitride layer, and a gallium nitride layer.
[0056] It should be noted that each sub-buffer layer in the composite buffer layer 21 in the embodiment can be sequentially arranged as an aluminum nitride layer, an aluminum gallium nitride layer, or sequentially arranged as an aluminum gallium nitride layer, a gallium nitride layer, or sequentially arranged as an aluminum nitride layer, a gallium nitride layer, or sequentially arranged as an aluminum nitride layer, an aluminum gallium nitride layer, a gallium nitride layer, that is, the lattice constant of each sub-buffer layer in the composite buffer layer 21 increases along the upward direction; each sub-buffer layer in the composite buffer layer 21 in the embodiment can also be sequentially arranged as an aluminum gallium nitride layer, an aluminum nitride layer, or sequentially arranged as a gallium nitride layer, an aluminum gallium nitride layer, or sequentially arranged as a gallium nitride layer, an aluminum nitride layer, or sequentially arranged as a gallium nitride layer, an aluminum gallium nitride layer, an aluminum nitride layer, that is, the lattice constant of each sub-buffer layer in the composite buffer layer 21 decreases along the upward direction.
[0057] Further, in order to ensure the structural stability of the composite buffer layer 21, each composite buffer layer 21 can be formed by an aluminum nitride layer, an aluminum gallium nitride layer and a gallium nitride layer arranged along a preset direction.
[0058] The heterojunction epitaxial wafer provided by the embodiment of the utility model is applied to wafer thinning, and comprises a substrate 10, a buffer layer 20 and an epitaxial functional layer 30, the buffer layer 20 is located between the substrate 10 and the epitaxial functional layer 30, the buffer layer 20 comprises a plurality of composite buffer layers 21 arranged along a preset direction, each composite buffer layer 21 comprises at least two sub-buffer layers with different lattice constants, the preset direction is the direction in which the substrate 10 points to the epitaxial functional layer 30, in each composite buffer layer 21, the lattice constant of the plurality of sub-buffer layers increases or decreases along the preset direction, forming a reverse stress, and the direction of the reverse stress is opposite to the direction of the stress that causes the epitaxial functional layer 30 to warp. The utility model gradually increases or decreases the lattice constant of the plurality of sub-buffer layers in each composite buffer layer 21 along the preset direction, so that the resultant force of the reverse stress formed by the buffer layer 20 and the stress that causes the epitaxial functional layer 30 to warp is smaller than the stress that causes the epitaxial functional layer 30 to warp, thereby weakening or eliminating the warping between the epitaxial functional layer 30 and the substrate 10 caused by the different thermal expansion coefficients of the materials, reducing the overall thickness of the wafer, improving the flatness of the epitaxial functional layer 30, and facilitating the matching degree of wafer bonding.
[0059] Furthermore, the substrate 10 is provided as a silicon substrate, and the epitaxial functional layer 30 is provided as a gallium nitride epitaxial functional layer, which is suitable for a conventional heterojunction epitaxial chip; each composite buffer layer 21 is formed by an aluminum nitride layer 211 and a gallium nitride layer 212 arranged along a preset direction, which ensures the convenience of preparation of the composite buffer layer 21 and is suitable for the epitaxial wafer grown on the silicon; the thickness of the aluminum nitride layer 211 in each composite buffer layer 21 is set to 3-10 nanometers, and the thickness of the gallium nitride layer 212 is set to 10-30 nanometers, preferably, the thickness of the aluminum nitride layer 211 is 5 nanometers, and the thickness of the gallium nitride layer 212 is 20 nanometers, which can ensure the stability of each composite buffer layer 21 and prevent each composite buffer layer 21 from cracking and damaging when warping, so as to facilitate the control of the flatness of the epitaxial chip formed by the buffer layer 20 and the epitaxial functional layer 30; the total thickness of the buffer layer 20 is set to 2.5-5 micrometers, which can ensure the warping degree of the formed buffer layer 20 and the flatness of the finally formed epitaxial chip; the resultant force of the reverse stress and the stress causing the warping of the epitaxial functional layer 30 is zero, which ensures the yield of the finally formed epitaxial chip and improves the yield of wafer bonding; each composite buffer layer 21 includes at least two of the aluminum nitride layer, the aluminum gallium nitride layer and the gallium nitride layer, and preferably, each composite buffer layer 21 is formed by the aluminum nitride layer, the aluminum gallium nitride layer and the gallium nitride layer arranged along a preset direction, which ensures the structural stability of the composite buffer layer 21.
[0060] Embodiment 2:
[0061] Compared with the epitaxial chip for wafer thinning provided in Embodiment 1, the epitaxial chip for wafer thinning provided in the embodiment has the following difference:
[0062] Each composite buffer layer 21 is the same.
[0063] In the embodiment, each composite buffer layer 21 in the buffer layer 20 is the same, that is, the type, arrangement mode, number and thickness of the sub-buffer layers in each composite buffer layer 21 are the same, and only the lattice constant of the multiple sub-buffer layers in each composite buffer layer 21 needs to be increased or decreased along a preset direction to form a reverse stress, and the direction of the reverse stress is opposite to the direction of the stress causing the warping of the epitaxial functional layer 30, so as to facilitate the preparation of the buffer layer 20 and improve the simplicity of the preparation of the buffer layer 20.
[0064] The epitaxial chip for wafer thinning provided in the embodiment facilitates the preparation of the buffer layer 20 and improves the simplicity of the preparation of the buffer layer 20.
[0065] In an embodiment, the wafer thinning heterojunction epitaxial chip can refer to the following structure:
[0066] The silicon substrate, the buffer layer and the gallium nitride epitaxial functional layer, the buffer layer is between the silicon substrate and the gallium nitride epitaxial functional layer;
[0067] The buffer layer comprises a plurality of composite buffer layers arranged along a preset direction, each composite buffer layer is formed by aluminum nitride and gallium nitride arranged along the preset direction, a reverse stress is formed, and a direction of the reverse stress is opposite to a direction of a stress causing the gallium nitride epitaxial functional layer to be warped, or a resultant force of the reverse stress and the stress causing the epitaxial functional layer to be warped is zero; the preset direction is a direction in which the silicon substrate points to the gallium nitride epitaxial functional layer; and each composite buffer layer is identical.
[0068] The thickness of the aluminum nitride is 5 nanometers, the thickness of the gallium nitride is 20 nanometers, and the total thickness of the buffer layer formed by the aluminum nitride and the gallium nitride arranged alternately along the preset direction is 2.5 micrometers to 5 micrometers.
[0069] It should be noted that the embodiment can refer to Figure 5 and Figure 6 , Figure 5 a structure diagram of a heterojunction epitaxial chip in an existing LED device provided by the embodiment of the utility model; Figure 6 a structure diagram of a heterojunction epitaxial chip for wafer thinning in an LED device provided by the embodiment of the utility model. Wherein Figure 6 In the embodiment, although the gallium nitride epitaxial layer 3 exists and has a tensile stress, in the buffer layer composed of the plurality of composite buffer layers 21, a direction of a reverse stress is opposite to a direction of a stress causing the gallium nitride epitaxial functional layer to be warped, or a resultant force of the reverse stress and the stress causing the epitaxial functional layer to be warped is zero, so that the surface of the epitaxial chip finally formed in the embodiment is more close to flat compared with the surface of a conventional epitaxial chip.
[0070] In the embodiment, the laminated aluminum nitride and gallium nitride are selected to realize warping along the preset direction, so as to offset the warping of the subsequent epitaxial functional layer, and the starting point is that the lattice constants of the gallium nitride and the aluminum nitride are different, the gallium nitride layer is pseudo-crystalline grown on the aluminum nitride layer, the aluminum nitride layer is partially relaxed on the gallium nitride layer, and a misfit dislocation is introduced. The in-plane lattice constant of the gallium nitride layer is greater than that of the aluminum nitride layer. Therefore, in this case, the pseudo-crystalline grown gallium nitride layer should be strained in the in-plane compression direction, so as to generate a restoring force in the in-plane expansion direction. Therefore, the gallium nitride has a tendency to expand outward, which offsets the subsequent epitaxial layer to the inward compression trend, so as to realize force balance, the surface of the epitaxial wafer is more flat, and the epitaxial warping is reduced.
[0071] Various embodiments are described herein with reference to a sequence, or sequences, of acts but the order of the acts can differ in other embodiments. Also, some acts can only be performed in a certain order in other embodiments.
[0072] Also, it should be understood that, although the terms "first", "second", etc. can be used herein to describe various elements or acts, these elements or acts should not be limited by these terms since such terms are only used to distinguish one element or act from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. The terms "and", "or", and "exclusively-or" are used herein to join independent events and do not have a logical "NOR" operation.
[0073] The above describes in detail the heterojunction epitaxial chip for wafer thinning provided by the present application, the principle and implementation mode of the present application are described herein by applying specific examples, the above embodiment description is only for helping to understand the structure of the present application and its core idea; meanwhile, for the general technical personnel in the art, according to the idea of the present application, the specific implementation mode and application range will have changes, and according to the above, the content of the specification should not be understood as the limitation of the present application.
Claims
1. A heterojunction epitaxial chip for wafer thinning, comprising: The application relates to a substrate, a buffer layer and an epitaxial functional layer, wherein the buffer layer is located between the substrate and the epitaxial functional layer. The buffer layer comprises a plurality of composite buffer layers arranged along a preset direction, each of the composite buffer layers comprises at least two sub-buffer layers with different lattice constants, and the preset direction is the direction from the substrate to the epitaxial functional layer. In each of the composite buffer layers, the lattice constants of the plurality of sub-buffer layers increase or decrease along the preset direction, thereby forming a reverse stress, and the direction of the reverse stress is opposite to the direction of the stress that causes the epitaxial functional layer to warp. Each of the composite buffer layers is identical.
2. The heteroepitaxial die for wafer thinning of claim 1, wherein, The substrate is a silicon substrate.
3. The heteroepitaxial die for wafer thinning of claim 1, wherein, The epitaxial functional layer is a gallium nitride epitaxial functional layer. Each of the composite buffer layers is formed by an aluminum nitride layer and a gallium nitride layer arranged along the preset direction.
4. The heteroepitaxial die for wafer thinning of claim 3, wherein, The thickness of the aluminum nitride layer in each of the composite buffer layers is 3-10 nm.
5. The heteroepitaxial die for wafer thinning of claim 4, wherein, The thickness of the gallium nitride layer in each of the composite buffer layers is 10-30 nm. The total thickness of the buffer layer formed by the aluminum nitride layer and the gallium nitride layer arranged along the preset direction is 2.5-5 microns.
6. The heteroepitaxial die for wafer thinning of claim 5, wherein, The thickness of the aluminum nitride layer is 5 nm, and the thickness of the gallium nitride layer is 20 nm.
7. The heteroepitaxial die for wafer thinning of claim 5, wherein, Each of the composite buffer layers comprises at least two of an aluminum nitride layer, an aluminum gallium nitride layer and a gallium nitride layer.
8. The heteroepitaxial die for wafer thinning of claim 3, wherein, Each of the composite buffer layers is formed by an aluminum nitride layer, an aluminum gallium nitride layer and a gallium nitride layer arranged along the preset direction.
9. The heteroepitaxial wafer for wafer thinning of claim 8, wherein, In each of the composite buffer layers, the lattice constants of the plurality of sub-buffer layers increase or decrease along the preset direction, thereby forming the reverse stress, and the resultant force of the reverse stress and the stress that causes the epitaxial functional layer to warp is zero.
10. The heteroepitaxial die for wafer thinning of claim 1, wherein,