Electronic device

Abstract

The utility model relates to an electronic device. The electronic device comprises a display panel, a display panel including a first region, a bending region at which the display panel is bent, a second region overlapping the first region, a first electrode arranged in a first direction in the first region, a second electrode arranged in a second direction in the first region and intersecting the first electrode, and a third electrode in the first region and overlapping the first electrode; a circuit board coupled to the display panel at the second area and including connecting lines arranged in the first direction and electrically connected to the third electrodes, respectively; the metal lower plate is arranged between the display panel and the circuit board; a first magnetic field shielding layer between the third electrode and the metal lower plate; and the second magnetic field shielding layer is arranged between the connecting line of the circuit board and the metal lower plate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0167244, filed on November 27, 2023, Korean Patent Application No. 10-2023-0192905, filed on December 27, 2023, and Korean Patent Application No. 10-2024-0098453, filed on July 25, 2024, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to an electronic device capable of sensing an input of a pen. BACKGROUND

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, laptop computers, navigators, game consoles, etc., include a display device for displaying images. In addition to a general input method such as a button, a keyboard, a mouse, etc., such an electronic device can include a sensor layer (or an input sensor) capable of providing a touch-based input method, which also allows a user to easily intuitively and conveniently input information or commands. The sensor layer can sense a touch or a pressure of a user. For a user familiar with inputting information using a writing tool or a specific application (e.g., an application for drawing or sketching), the demand for fine touch input using a pen is increasing. SUMMARY

[0005] The present disclosure provides an electronic device capable of sensing an input of a pen.

[0006] One or more embodiments of the present disclosure provide an electronic device including a display panel including a first area, a bending area at which the display panel is bent, a second area overlapping the first area, a first electrode arranged in a first direction in the first area, a second electrode arranged in a second direction crossing the first direction and crossing the first electrode in the first area, and a third electrode overlapping the first electrode in the first area; a circuit board coupled to the display panel at the second area and including connection lines arranged in the first direction and respectively electrically connected to the third electrode; a metal back plate between the display panel and the circuit board; a first magnetic field shielding layer between the third electrode of the display panel and the metal back plate; and a second magnetic field shielding layer between the connection lines of the circuit board and the metal back plate.

[0007] The connection lines can be respectively electrically connected to the third electrode at the first area, at the bending area, or at the second area.

[0008] The display panel can further include a display layer and a sensor layer, the sensor layer including a first loop-shaped trace electrically connected to a first end of the third electrode and arranged in the first direction, and a second loop-shaped trace electrically connected to a second end of the third electrode.

[0009] The first loop-shaped trace can be spaced apart from the connection lines electrically connected thereto in the first direction.

[0010] The second loop-shaped trace can include a first line portion electrically connected to the third electrode, a second line portion extending from a first end of the first line portion in the second direction, and a third line portion extending from a second end of the first line portion in the second direction, wherein the second line portion, the first loop-shaped trace, and the third line portion are sequentially arranged in the first direction.

[0011] At least one of the display panel and the circuit board can further include a bridge line electrically connecting the connection lines and the third electrode, respectively.

[0012] The bridge line can extend in the first direction.

[0013] The bridge line can be in the first area.

[0014] The first area can include a sensing area for sensing an external input and a peripheral area adjacent to the sensing area, wherein at least some of the bridge lines are in the peripheral area.

[0015] The bridge line can be separated from the curved area.

[0016] Some of the bridge lines can be in the first area, wherein other ones of the bridge lines are in the circuit board.

[0017] One or more embodiments of the disclosure provide an electronic device including a display panel including a first area, a curved area at which the display panel is curved, a second area overlapping the first area, a first electrode portion arranged in a first direction in the first area, a second electrode portion arranged in the first direction in the curved area and electrically connected to the first electrode portion, and a third electrode portion arranged in the first direction in the second area and electrically connected to the second electrode portion; a circuit board coupled to the display panel at the second area and including a connection line arranged in the first direction and electrically connected to the third electrode portion; a metal back plate between the first electrode portion and the connection line; a first magnetic field shielding layer between the first electrode portion and the metal back plate; and a second magnetic field shielding layer between the connection line and the metal back plate.

[0018] The connection line can have an arrangement order in the first direction different from an arrangement order of the third electrode portions connected thereto in the first direction, respectively.

[0019] The arrangement order of the third electrode part can be opposite to the arrangement order of the connection line.

[0020] One or more embodiments of the disclosure provide an electronic device including a display panel including a first area, a bending area at which the display panel is bent, a second area overlapping the first area, a first electrode part arranged in the first area in a first direction, a second electrode part arranged in the bending area in the first direction and electrically connected to the first electrode part, and a third electrode part arranged in the second area in the first direction and electrically connected to the second electrode part; a circuit board coupled to the display panel at the second area and including a connection line electrically connected to the third electrode part at a first layer, an extension connection line connected to the connection line at a second layer different from the first layer, a first conductive shielding layer between the first electrode part and the connection line, and a second conductive shielding layer between the connection line and the extension connection line; a metal back plate between the display panel and the circuit board; and a magnetic field shielding layer between the display panel and the metal back plate.

[0021] The first conductive shielding layer or the second conductive shielding layer can be grounded.

[0022] The first conductive shielding layer or the second conductive shielding layer can be configured to receive a constant voltage.

[0023] The circuit board can be under the display panel at the first area, and can further include a first conductive layer having the connection line and a second conductive layer having the extension connection line, and the first conductive layer is between the second conductive layer and the first area of the display panel.

[0024] The first conductive layer can be under the first conductive shielding layer, and can partially overlap the second area of the display panel.

[0025] The second conductive layer can be under the second conductive shielding layer, and can partially overlap the second area of the display panel.

[0026] One or more embodiments of the disclosure provide an electronic device including a substrate including a first area, a bending area at which the substrate is bent, a second area overlapping the first area; a circuit layer over the substrate and including a transistor; a light emitting element layer over the circuit layer and including a light emitting element electrically connected to the transistor; a sensor layer over the light emitting element layer and including an electrode arranged in the first area in a first direction; a sensor driver configured to generate a magnetic field for charging a pen including an RLC resonance circuit using the electrode; a circuit board coupled to the substrate at the second area and including a connection line electrically connected to the electrode; a metal back plate between the electrode and the connection line; a first magnetic field shielding layer between the electrode and the metal back plate; and a second magnetic field shielding layer between the connection line and the metal back plate.

[0027] The sensor driver can be configured to selectively operate in a first mode in which the sensor layer is driven to sense a touch input or a second mode in which the sensor layer is driven to sense a pen input, the second mode including a charging driving mode.

[0028] The sensor layer can be configured to sense the pen input by applying a first signal to at least one of the electrodes and by applying a second signal to at least another one of the electrodes.

[0029] The sensor layer can further include a first mesh line having a first width, a second mesh line above the first mesh line and having a second width equal to or greater than the first width, and an intermediate insulating layer between the first mesh line and the second mesh line.

[0030] The connection line can have an arrangement order in the first direction different from an arrangement order of the electrodes connected thereto, respectively, in the first direction.

[0031] The electronic device can further include a bridge line in the first area of the substrate and / or in the circuit board, the bridge line electrically connecting the electrodes to the connection line, respectively.

[0032] The bridge line can be within a limited distance from a curved edge defined in the curved area.

[0033] The electronic device can further include a display driver in the second area and configured to control the circuit layer, wherein the circuit board overlaps the first area.

[0034] The second magnetic field shielding layer can overlap the circuit board and the second area of the substrate.

[0035] A surface area of the first magnetic field shielding layer can be equal to or greater than a surface area of the second magnetic field shielding layer. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. In the drawings:

[0037] FIG. 1A is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0038] FIG. 1B is a rear perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0039] FIG. 2 is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0040] FIG. 3 is a perspective view of an electronic device according to one or more embodiments of the disclosure;

[0041] FIG. 4 is a schematic cross-sectional view of a display panel according to one or more embodiments of the disclosure;

[0042] FIG. 5 is a view for explaining an operation of an electronic device according to one or more embodiments of the disclosure;

[0043] FIG. 6A is a cross-sectional view of a display panel according to one or more embodiments of the disclosure;

[0044] FIG. 6B is a cross-sectional view of a sensor layer according to one or more embodiments of the disclosure;

[0045] FIG. 7 is a plan view of a display panel and a circuit board according to one or more embodiments of the disclosure;

[0046] FIG. 8A is a plan view illustrating a first conductive layer of a sensing unit according to one or more embodiments of the disclosure;

[0047] FIG. 8B is a plan view illustrating a second conductive layer of a sensing unit according to one or more embodiments of the disclosure;

[0048] FIG. 9 is a cross-sectional view of a sensor layer according to one or more embodiments of the disclosure, taken along a line I-I' of FIG. 8A and FIG. 8B ;

[0049] FIG. 10A is an enlarged plan view of a region AA' of FIG. 8A ;

[0050] FIG. 10B is an enlarged plan view of a region BB' of FIG. 8B ;

[0051] FIG. 11 is a view illustrating an operation of a sensor driver according to one or more embodiments of the disclosure;

[0052] FIG. 12 is a view illustrating an operation of a sensor driver according to one or more embodiments of the disclosure;

[0053] FIG. 13 is a plan view for explaining a first mode according to one or more embodiments of the disclosure;

[0054] FIG. 14 is a plan view for explaining a second mode according to one or more embodiments of the present disclosure;

[0055] FIG. 15A is a graph showing a waveform of a first signal according to one or more embodiments of the present disclosure;

[0056] FIG. 15B is a graph showing a waveform of a second signal according to one or more embodiments of the present disclosure;

[0057] FIG. 16 is a view of a pen according to one or more embodiments of the present disclosure;

[0058] FIG. 17A is a view for explaining an operation of a pen according to one or more embodiments of the present disclosure;

[0059] FIG. 17B is a view for explaining an operation of a sensor layer according to one or more embodiments of the present disclosure;

[0060] FIG. 18A is a plan view for explaining a second mode according to one or more embodiments of the present disclosure;

[0061] FIG. 18B is a view for explaining a second mode based on one sensing unit according to one or more embodiments of the present disclosure;

[0062] FIG. 19 is a plan view showing a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0063] FIG. 20 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0064] FIG. 21 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0065] FIG. 22 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0066] FIG. 23 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0067] FIG. 24 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0068] FIG. 25Ais a view showing a result of simulation of a magnetic field on a surface of a display panel according to a comparative example of the present disclosure;

[0069] FIG. 25B is a view showing a result of simulation of a magnetic field on a surface of a display panel according to an embodiment of the present disclosure;

[0070] FIG. 26 is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure taken along line II-II' of FIG. 19 ;

[0071] FIG. 27 is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure taken along line II-II' of FIG. 19 ;

[0072] FIG. 28 is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure taken along line II-II' of FIG. 19 ;

[0073] FIG. 29 is a cross-sectional view of a circuit board according to one or more embodiments of the present disclosure;

[0074] FIG. 30A is a cross-sectional view of a circuit board according to one or more embodiments of the present disclosure;

[0075] FIG. 30B is a plan view of a circuit board according to one or more embodiments of the present disclosure;

[0076] FIG. 31 is a cross-sectional view of a circuit board according to one or more embodiments of the present disclosure;

[0077] FIG. 32A is a plan view of a first shielding layer according to one or more embodiments of the present disclosure;

[0078] FIG. 32B is a plan view of a first wiring layer according to one or more embodiments of the present disclosure;

[0079] FIG. 32C is a plan view of a second shielding layer according to one or more embodiments of the present disclosure;

[0080] FIG. 32D is a plan view of a third shielding layer according to one or more embodiments of the present disclosure;

[0081] FIG. 32E is a plan view of a second wiring layer according to one or more embodiments of the present disclosure; and

[0082] FIG. 32F is a plan view of a fourth shielding layer according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0083] Aspects of some embodiments of the present disclosure and methods of realizing the same can be more readily understood by reference to the following detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the scope of the aspects of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are redundant, irrelevant to the description of the embodiments, or not necessary for those of ordinary skill in the art to understand aspects of the present disclosure can be omitted. Unless otherwise stated, the same reference numbers, characters or combinations thereof in the drawings and written description throughout the specification indicate the same elements, and thus, repetitive description thereof can be omitted.

[0084] The described embodiments can have various modifications and can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. In describing the embodiments, the use of “can,” “may,” or “might” corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents, and alternatives falling within the idea and technical scope of the present disclosure. Furthermore, each of the features of the various embodiments of the present disclosure can be partially or wholly combined with each other, and various interlocks and drives are possible technically. Each of the embodiments can be implemented independently of each other, or can be implemented together in association.

[0085] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. Also, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries, regions, and / or elements of the drawings. As such, the absence of cross-hatching and / or shading is not intended to imply any particular characteristic, attribute, property, etc., of a particular material, material property, dimension, ratio, commonality between elements, and / or any other characteristic, attribute, property, etc., of the illustrated elements, unless specifically stated otherwise.

[0086] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic representations of schematics embodiments and / or intermediate structures of embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, the specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative of the embodiments according to the concepts of the present disclosure. Thus, the embodiments disclosed herein are not to be interpreted as being limited to the shapes of the elements as illustrated, but include deviations in shapes that result from, for example, manufacturing.

[0087] For example, an implant region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation occurs.

[0088] For purposes of this description, spatially relative terms such as "beneath", "below", "lower", "bottom", "under", "above", "upper", "top", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being "on" a second part, it can be either be disposed directly on the second part or be disposed indirectly such that an intermediate part is interposed therebetween. Likewise, when a first part is described as being disposed "on" a second part, it can be either be disposed directly on the second part or be disposed indirectly such that an intermediate part is interposed therebetween.

[0089] Furthermore, the phrase "in plan view" means viewing a portion of an object from above, and the phrase "in schematic cross-sectional view" means viewing a schematic cross-section of a portion of an object taken by cutting the object vertically from the side. The term "overlapping" or "overlap" means that a first object can be above or below a second object, or to one side of the second object, and vice versa. Additionally, the term "overlapping" can include overlying, facing or facing towards, extending throughout, covering or partially covering, or any other suitable term as would be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include the meaning of "separated from" or "disposed alongside" or "offset from" as well as any other suitable equivalent as would be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "facing towards" can mean that a first object can be directly or indirectly opposite a second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, although still facing each other.

[0090] It will be understood that when an element, layer, region or component is referred to as being "formed on", "adjacent" or "connected to" or "coupled to" another element, layer, region or component, it can be directly formed on, directly adjacent to, directly connected to or directly coupled to the other element, layer, region or component, or there can be one or more intervening elements, layers, regions or components such that the contact is indirect. In addition, it can be that the contact is either whole or partial. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to the other layer, region and / or component, or there can be one or more intervening layers, regions or components. The intervening component(s) can include a switch, resistor, capacitor, etc. In describing implementations, expressions of the form "connected" or "coupled" or "directly connected / directly coupled" or "directly on" mean, unless specifically stated otherwise, electrically connected or coupled, and "directly connected / directly coupled" or "directly on" mean that one component is connected or coupled to or on another component without an intervening component.

[0091] Also, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the direction of formation is not limited to the upper direction, but includes formation of the part on a side surface or in the lower direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly" under the other part, but also the case where there is a further part between the part and the other part. On the other hand, other expressions describing the relationship between components, such as "between", "directly between" or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0092] For purposes of this disclosure, expressions such as “at least one of,” when preceding the list of elements, modifies the element list as a whole and does not modify the individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one of X, Y, and Z” are each interpreted as X, Y, and Z individually, or any combination thereof such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, an expression such as “at least one of A and B” can include A, B, or A and B. As used herein, “or” is generally employed in its sense including “and / or” unless the context of such usage indicates otherwise. The term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of,” “one or more of,” “a or b,” and other similar phrases, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0093] It will be understood that, although the terms “first,” “second,” “third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, section or part from another element, component, region, layer, section or part. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure. Describing an element as “first” does not require or imply the presence of a second element or other elements. The terms “first,” “second,” etc. can also be used herein to distinguish different categories or different groups of elements. For the sake of clarity, the terms “first,” “second,” etc. can be used herein to denote “first category (or first group),” “second category (or second group),” etc. respectively.

[0094] In examples, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0095] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0096] When one or more embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed at substantially the same time, or in the reverse order of the described sequence.

[0097] As used herein, the terms "substantially", "about", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, "substantially" can include a range of ±5% of a recited value. In view of the discussed measurement and the error associated with measuring a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein includes the recited value and means within an acceptable range of deviation from the particular value as would be determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value. Furthermore, the use of "may" when describing embodiments of the present disclosure relates to "one or more embodiments of the present disclosure".

[0098] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0099] The terms "part" and "unit" refer to a software component or a hardware component that performs a specific function. The hardware component can include, for example, a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The software component can refer to executable code in an addressable storage medium and / or data used by the executable code. Thus, the software component can be, for example, an object-oriented software component, a class component, and a task component, a process, a function, an attribute, a procedure, a subroutine, a program code segment, a driver, firmware, microcode, a circuit, data, a database, a data structure, a table, an array, or a variable.

[0100] Hereinafter, embodiments of the disclosure will be described with reference to the accompanying drawings.

[0101] FIG. 1A is a perspective view of an electronic device 1000 according to one or more embodiments of the disclosure. FIG. 1B is a rear perspective view of an electronic device 1000 according to one or more embodiments of the disclosure.

[0102] Referring to FIG. 1A and FIG. 1B , the electronic device 1000 can be a device that is activated according to an electrical signal. For example, the electronic device 1000 can display an image and sense an input applied from the outside. The external input can be a user's input. The user's input can include various types of external inputs such as a part of the user's body, a pen PN, light, heat, or pressure.

[0103] The electronic device 1000 can include a first display panel DP1 and a second display panel DP2. The first display panel DP1 and the second display panel DP2 can be separate panels that are separated from each other. The first display panel DP1 can be referred to as a main display panel, and the second display panel DP2 can be referred to as an auxiliary display panel, or as an external display panel.

[0104] The first display panel DP1 can include a first display portion DA1-F, and the second display panel DP2 can include a second display portion DA2-F. The surface area of the second display panel DP2 can be smaller than the surface area of the first display panel DP1. The surface area of the first display portion DA1-F can be greater than the surface area of the second display portion DA2-F to correspond to the size of each of the first display panel DP1 and the second display panel DP2.

[0105] In a state in which the electronic device 1000 is unfolded, the first display portion DA1-F can have a plane substantially parallel to the first direction DR1 and the second direction DR2. A thickness direction of the electronic device 1000 can be parallel to a third direction DR3 crossing the first direction DR1 and the second direction DR2. Accordingly, a front surface (or a top surface) and a rear surface (or a bottom surface) of each of the components constituting the electronic device 1000 can be defined based on the third direction DR3.

[0106] The first display panel DP1 or the first display portion DA1-F can include a foldable and unfoldable folding area FA and a plurality of non-folding areas NFA1 and NFA2 spaced apart from each other, with the folding area FA between the plurality of non-folding areas NFA1 and NFA2. The second display panel DP2 can overlap one of the plurality of non-folding areas NFA1 and NFA2. For example, the second display panel DP2 can overlap the first non-folding area NFA1.

[0107] A display direction of the first image IM1a displayed on a portion of the first display panel DP1 (e.g., in the second non-folding area NFA2) and a display direction of the second image IM2a displayed on the second display panel DP2 can be opposite to each other. For example, the first image IM1a can be displayed in a third direction DR3, and the second image IM2a can be displayed in a fourth direction DR4 opposite to the third direction DR3.

[0108] In one or more embodiments of the disclosure, the folding area FA can be bent with respect to a folding axis extending in a direction parallel to a long side of the electronic device 1000, e.g., in a direction parallel to the second direction DR2. When the electronic device 1000 is folded, the folding area FA can have a curvature and a radius of curvature (e.g., a predetermined curvature and a radius of curvature). The first non-folding area NFA1 and the second non-folding area NFA2 can face each other, and the electronic device 1000 can be folded inwardly such that the first display portion DA1-F is not exposed to the outside.

[0109] In one or more embodiments of the disclosure, the electronic device 1000 can be folded outwardly such that the first display portion DA1-F is exposed to the outside. In one or more embodiments of the disclosure, the electronic device 1000 can be capable of being folded inwardly and outwardly both from the unfolded state, but is not limited thereto.

[0110] In FIG. 1AIn FIG. 1A, an example in which one folding area FA is defined in the electronic device 1000 is shown, but the present disclosure is not limited thereto. For example, the electronic device 1000 can define a plurality of folding axes and a plurality of folding areas corresponding thereto, and the electronic device 1000 can be in an inner folding, an outer folding, or an unfolded state at each of the folding areas.

[0111] According to one or more embodiments of the present disclosure, at least one of the first display panel DP1 and the second display panel DP2 can sense an input of the pen PN even if the at least one of the first display panel DP1 and the second display panel DP2 does not include a digitizer. Accordingly, since the digitizer for sensing the pen PN is omitted, an increase in thickness, an increase in weight, and a decrease in flexibility of the electronic device 1000 due to the addition of the digitizer can be avoided. Thus, not only the first display panel DP1 but also the second display panel DP2 can be designed to sense the pen PN.

[0112] FIG. 2 is a perspective view of an electronic device 1000-1 according to one or more embodiments of the present disclosure. FIG. 3 is a perspective view of an electronic device 1000-2 according to one or more embodiments of the present disclosure.

[0113] FIG. 2 An example in which the electronic device 1000-1 is a mobile phone and the electronic device 1000-1 can include a display panel DP is shown. FIG. 3 An example in which the electronic device 1000-2 is a laptop computer and the electronic device 1000-2 can include a display panel DP is shown. Although FIG. 3 is a perspective view of the electronic device 1000-2, but FIG. 3 The coordinate axes included in FIG. 1B are displayed based on the display panel DP within the electronic device 1000-2.

[0114] In one or more embodiments of the present disclosure, the display panel DP can sense an input applied from the outside. The external input can be an input of a user. The input of the user can include various types of external inputs such as a part of the user's body, a pen PN (see FIG. 1A ), light, heat, or pressure.

[0115] According to one or more embodiments of the present disclosure, the display panel DP can sense an input of the pen PN even if the display panel DP does not include a digitizer. Accordingly, since the digitizer for sensing the pen PN is omitted, an increase in thickness, an increase in weight, and a decrease in flexibility of the electronic device 1000-1 or 1000-2 due to the addition of the digitizer can not occur.

[0116] In FIG. 1AIn the following description, the foldable electronic device 1000 can be illustrated as an example, while in FIG. 2 In the following description, the bar-type electronic device 1000-1 can be illustrated as an example. However, the disclosure to be described below is not limited thereto. For example, the description described below can be applied to various electronic devices such as a rollable electronic device, a slidable electronic device, and a stretchable electronic device.

[0117] FIG. 4 FIG. 1 is a schematic cross-sectional view of a display panel DP according to an embodiment of the disclosure.

[0118] Referring to FIG. 4 , the display panel DP can include a display layer 100 and a sensor layer 200.

[0119] The display layer 100 can be configured to substantially generate an image. The display layer 100 can be an emission-type display layer. For example, the display layer 100 can be an organic light emitting display layer, an inorganic light emitting display layer, an organic-inorganic light emitting display layer, a quantum dot display layer, a micro LED display layer, or a nano LED display layer. The display layer 100 can include a base layer 110, a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140.

[0120] The base layer 110 can be a member that provides a base surface on which the circuit layer 120 is positioned. The base layer 110 can have a single layer structure or a multi-layer structure. The base layer 110 can be a glass substrate, a metal substrate, a silicon substrate, or a polymer substrate, but the disclosure is not particularly limited thereto.

[0121] The circuit layer 120 can be located on the base layer 110 (for example, "on" can mean "above" as used herein). The circuit layer 120 can include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The insulating layer, the semiconductor layer, and the conductive layer can be formed on the base layer 110 in a manner such as coating or vapor deposition, and then the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned by a plurality of photolithography processes.

[0122] The light emitting element layer 130 can be located on the circuit layer 120. The light emitting element layer 130 can include a light emitting element. For example, the light emitting element layer 130 can include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0123] The encapsulation layer 140 can be located on the light emitting element layer 130. The encapsulation layer 140 can protect the light emitting element layer 130 from moisture, oxygen, and impurities such as dust particles.

[0124] The sensor layer 200 can be located on the display layer 100. The sensor layer 200 can sense an external input applied from the outside. The sensor layer 200 can be an integrated sensor that is continuously formed during a process of manufacturing the display layer 100, or the sensor layer 200 can be an external sensor attached to the display layer 100. The sensor layer 200 can be referred to as a sensor, an input sensing layer, an input sensing panel, or an electronic device for sensing input coordinates.

[0125] According to one or more embodiments of the disclosure, the sensor layer 200 can sense inputs from both a passive type input unit such as a user's body and an input device that generates a magnetic field having a resonance frequency (e.g., a predetermined resonance frequency). The input device can be referred to as a pen, an input pen, a magnetic pen, a stylus, or an electromagnetic resonance pen.

[0126] FIG. 5 is a view for explaining the operation of the electronic device 1000 according to one or more embodiments of the disclosure.

[0127] Referring to FIG. 5 , the electronic device 1000 can include a display layer 100, a sensor layer 200, a display driver 100C (e.g., a first driver circuit), a sensor driver 200C (e.g., a second driver circuit), a main driver 1000C (e.g., a third driver circuit), and a power circuit 1000P.

[0128] The sensor layer 200 can sense a first input 2000 or a second input 3000 applied from the outside. Each of the first input 2000 and the second input 3000 can be an input unit capable of providing a change in capacitance of the sensor layer 200, or an input unit capable of inducing an induced current in the sensor layer 200. For example, the first input 2000 can be a passive input unit such as a user's body. The second input 3000 can be an input using a pen PN or a radio frequency integrated circuit (RFIC) tag. For example, the pen PN can be a passive type pen or an active type pen.

[0129] In one or more embodiments of the disclosure, the pen PN can be a device that generates a magnetic field having a resonance frequency (e.g., a predetermined resonance frequency). The pen PN can be configured to transmit an output signal based on electromagnetic resonance. The pen PN can be referred to as an input device, an input pen, a magnetic pen, a stylus, or an electromagnetic resonance pen.

[0130] The pen PN can include an RLC resonance circuit, and the RLC resonance circuit can include an inductor L and a capacitor C. In one or more embodiments of the disclosure, the RLC resonance circuit can be a variable resonance circuit whose resonance frequency is variable. In this case, the inductor L can be a variable inductor, and / or the capacitor C can be a variable capacitor, but both are not particularly limited thereto.

[0131] The inductor L can generate an electric current through a magnetic field generated in the electronic device 1000 (e.g., the sensor layer 200). However, the present disclosure is not particularly limited thereto. For example, if the pen PN operates as an active type, the pen PN can generate an electric current even if it does not receive a magnetic field from the outside. The generated electric current can be transferred to the capacitor C. The capacitor C can be charged with the electric current input from the inductor L, and can discharge the charged electric current to the inductor L. Thereafter, the inductor L can emit a magnetic field at a resonance frequency. Due to the magnetic field emitted by the pen PN, an induced electric current can flow in the sensor layer 200, and the induced electric current can be transmitted to the sensor driver 200C as a reception signal (or a sensing signal, a signal, etc.).

[0132] The main driver 1000C can control the overall operation of the electronic device 1000. For example, the main driver 1000C can control the operation of the display driver 100C and the sensor driver 200C. The main driver 1000C can include at least one microprocessor, and can further include a graphic controller. The main driver 1000C can be referred to as an application processor, a central processing unit, or a main processor.

[0133] The display driver 100C can control the display layer 100. The display driver 100C can receive image data and a control signal from the main driver 1000C. The control signal can include various signals. For example, the control signal can include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock signal, and a data enable signal.

[0134] The sensor driver 200C can control the sensor layer 200. The sensor driver 200C can receive a control signal from the main driver 1000C. The control signal can include a clock signal of the sensor driver 200C. In addition, the control signal can further include a mode decision signal that determines a driving mode of the sensor driver 200C and the sensor layer 200.

[0135] The sensor driver 200C can be implemented as an integrated circuit (IC), and can be electrically connected to the sensor layer 200. For example, the sensor driver 200C can be directly mounted on a region (e.g., a predetermined region) of the display panel, or can be mounted on a separate printed circuit board using a chip on film (COF) method, and can be electrically connected to the sensor layer 200.

[0136] The sensor driver 200C and the sensor layer 200 can selectively operate in a first mode or a second mode. For example, the first mode can be a mode for sensing a touch input (e.g., the first input 2000). The second mode can be a mode for sensing a pen PN input (e.g., the second input 3000). The first mode can be referred to as a touch sensing mode, and the second mode can be referred to as a pen sensing mode.

[0137] The switching between the first mode and the second mode can be implemented in various ways. For example, the sensor driver 200C and the sensor layer 200 are driven in the first mode and the second mode in a time-division manner, and can sense the first input 2000 and the second input 3000. Alternatively, the switching between the first mode and the second mode can occur due to a selection of a user or a corresponding action (or input) of the user, or one of the first mode and the second mode can be activated or deactivated by activating or deactivating a corresponding application, or can be switched from one to the other. Alternatively, if the first input 2000 is sensed while the sensor driver 200C and the sensor layer 200 are alternately operated in the first mode and the second mode, the sensor driver 200C and the sensor layer 200 can remain in the first mode, and if the second input 3000 is sensed, the sensor driver 200C and the sensor layer 200 can remain in the second mode.

[0138] The sensor driver 200C can calculate input coordinate information based on a signal received from the sensor layer 200, and can provide a coordinate signal having the input coordinate information to the main driver 1000C. The main driver 1000C can perform an operation corresponding to a user input based on the coordinate signal. For example, the main driver 1000C can operate the display driver 100C to display a new application image on the display layer 100.

[0139] The power circuit 1000P can include a power management integrated circuit (PMIC). The power circuit 1000P can generate a plurality of driving voltages for driving the display layer 100, the sensor layer 200, the display driver 100C, and the sensor driver 200C. For example, the plurality of driving voltages can include a gate high voltage, a gate low voltage, a first driving voltage, a second driving voltage, an initialization voltage, etc., but the present disclosure is not particularly limited thereto.

[0140] FIG. 6A is a cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure.

[0141] Reference FIG. 6AAt least one buffer layer BFL can be located on a top surface of the base layer 110. The buffer layer BFL can improve adhesion between the base layer 110 and the semiconductor pattern. The buffer layer BFL can be provided as multiple layers. Alternatively, the display layer 100 can further include a barrier layer. The buffer layer BFL can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL can include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0142] The semiconductor patterns SC, AL, DR, and SCL can be located on the buffer layer BFL. Each of the semiconductor patterns SC, AL, DR, and SCL can include polysilicon. However, each of the semiconductor patterns SC, AL, DR, and SCL is not limited thereto and can include amorphous silicon, low-temperature polysilicon, or an oxide semiconductor.

[0143] FIG. 6A Only some of the semiconductor patterns SC, AL, DR, and SCL are illustrated, and additional semiconductor patterns can also be located in one or more other areas. The semiconductor patterns SC, AL, DR, and SCL can be arranged in a corresponding arrangement throughout a pixel. The semiconductor patterns SC, AL, DR, and SCL can have different electrical characteristics depending on whether they are doped. The semiconductor patterns SC, AL, DR, and SCL can include first regions SC, DR, and SCL having high conductivity and a second region AL having low conductivity. The first regions SC, DR, and SCL can be doped with N-type or P-type dopants. A P-type transistor can include a doped region doped with a P-type dopant, and an N-type transistor can include a doped region doped with an N-type dopant. The second region AL can be an undoped region, or can be doped at a lower concentration than that of the first regions SC, DR, and SCL.

[0144] The conductivity of the first regions SC, DR, and SCL can be greater than that of the second region AL, and can substantially function as an electrode or a signal line. The second region AL can substantially correspond to an active region AL (or a channel) of the transistor 100PC. In other words, a portion AL of the semiconductor patterns SC, AL, DR, and SCL can be the active region AL of the transistor 100PC, and other portions SC and DR can be a source region SC or a drain region DR of the transistor 100PC, respectively, and another portion SCL can be a connection electrode or a connection signal line SCL.

[0145] Each of the pixels can have an equivalent circuit including a plurality of transistors, at least one capacitor, and at least one light emitting element. The equivalent circuit diagram of the pixel can be modified in various forms. In FIG. 6A In the equivalent circuit diagram, one transistor 100PC and one light emitting element 100PE provided in the pixel are illustrated as an example.

[0146] The source region SC, the active region AL, and the drain region DR of the transistor 100PC can be formed of the semiconductor patterns SC, AL, DR, and SCL. The source region SC and the drain region DR can extend in opposite directions from the active region AL in a cross section, respectively. FIG. 6A A portion of the connection signal line SCL formed of the semiconductor patterns SC, AL, DR, and SCL is shown. In one or more embodiments, the connection signal line SCL can be connected to the drain region DR of the transistor 100PC in a plan view.

[0147] The first insulating layer 10 can be located on the buffer layer BFL. The first insulating layer 10 can overlap the plurality of pixels in common, and can cover the semiconductor patterns SC, AL, DR, and SCL. The first insulating layer 10 can include an inorganic layer and / or an organic layer, and can have a single layer structure or a multi-layer structure. The first insulating layer 10 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer 10 can include a single layer of silicon oxide. The insulating layer of the circuit layer 120 to be described later, other than the first insulating layer 10, can also be an inorganic layer and / or an organic layer, and can have a single layer structure or a multi-layer structure. The inorganic layer can include at least one of the above-described materials, but is not limited thereto.

[0148] The gate GT of the transistor 100PC is located on the first insulating layer 10. The gate GT can be a portion of a metal pattern. The gate GT overlaps the active region AL. The gate GT can be used as a mask in a process of doping or reducing the semiconductor patterns SC, AL, DR, and SCL.

[0149] The second insulating layer 20 can be located on the first insulating layer 10 to cover the gate GT. The second insulating layer 20 can overlap the pixels in common. The second insulating layer 20 can be an inorganic layer and / or an organic layer, and can have a single layer structure or a multi-layer structure. The second insulating layer 20 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second insulating layer 20 can have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0150] The third insulating layer 30 can be located on the second insulating layer 20. The third insulating layer 30 can have a single layer structure or a multi-layer structure. For example, the third insulating layer 30 can have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0151] The first connection electrode CNE1 can be located on the third insulating layer 30. The first connection electrode CNE1 can be connected to the connection signal line SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0152] A fourth insulating layer 40 can be located on the third insulating layer 30. The fourth insulating layer 40 can be a single layer of silicon oxide. A fifth insulating layer 50 can be located on the fourth insulating layer 40. The fifth insulating layer 50 can be an organic layer.

[0153] A second connection electrode CNE2 can be located on the fifth insulating layer 50. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through a contact hole CNT-2 that passes through the fourth insulating layer 40 and the fifth insulating layer 50.

[0154] A sixth insulating layer 60 can be located on the fifth insulating layer 50 to cover the second connection electrode CNE2. The sixth insulating layer 60 can be an organic layer.

[0155] A light emitting element layer 130 can be located on the circuit layer 120. The light emitting element layer 130 can include a light emitting element 100PE. For example, the light emitting element layer 130 can include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED. Hereinafter, the light emitting element 100PE will be described as an example of an organic light emitting element, but the present disclosure is not particularly limited thereto.

[0156] The light emitting element 100PE can include a first electrode AE, an emission layer EL, and a second electrode CE.

[0157] The first electrode AE can be located on the sixth insulating layer 60. The first electrode AE can be connected to the second connection electrode CNE2 through a contact hole CNT-3 that passes through the sixth insulating layer 60.

[0158] A pixel defining layer 70 can be located on the sixth insulating layer 60 to cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining layer 70. The opening 70-OP of the pixel defining layer 70 exposes at least a portion of the first electrode AE.

[0159] A first display portion DA1-F (see FIG. 1A ) can include an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA can surround the emission region PXA (e.g., in a plan view). The emission region PXA can be defined as a portion of a region corresponding to the first electrode AE that is exposed by the opening 70-OP.

[0160] The emission layer EL can be located on the first electrode AE. The emission layer EL can be located in a region corresponding to the opening 70-OP. FIG. 6A An example in which the emission layer EL is located within the opening 70-OP is shown, but the present disclosure is not particularly limited thereto. For example, the emission layer EL can extend to cover some of a top surface of the pixel defining layer 70 and side surfaces of the pixel defining layer 70 that define the opening 70-OP.

[0161] According to one or more embodiments of the disclosure, the emission layer EL can be individually positioned for each of the pixels. When the emission layer EL is individually positioned for each of the pixels, each of the emission layers EL can emit light having at least one color among blue, red, and green. However, the disclosure is not limited thereto. For example, the emission layer EL can be commonly included in a plurality of pixels while having an integrated shape. In this case, the emission layer EL can provide blue light or white light.

[0162] The second electrode CE can be located on the emission layer EL. The second electrode CE can be commonly included in a plurality of pixels while having an integrated shape.

[0163] In one or more embodiments of the disclosure, a hole control layer can be located between the first electrode AE and the emission layer EL. The hole control layer can be commonly located in the emission area PXA and the non-emission area NPXA. The hole control layer can include a hole transport layer, and can further include a hole injection layer. An electron control layer can be located between the emission layer EL and the second electrode CE. The electron control layer can include an electron transport layer, and can further include an electron injection layer. The hole control layer and the electron control layer can be commonly disposed in the pixel by using an opening mask or an inkjet process.

[0164] The encapsulation layer 140 can be located on the light emitting element layer 130. The encapsulation layer 140 can include an inorganic layer, an organic layer, and another inorganic layer which are sequentially stacked, but the layers constituting the encapsulation layer 140 are not limited thereto. The inorganic layer can protect the light emitting element layer 130 from moisture and oxygen, and the organic layer can protect the light emitting element layer 130 from impurities such as dust particles. The inorganic layer can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer can include an acrylic-based organic layer, but the disclosure is not limited thereto.

[0165] The sensor layer 200 can include a base layer 201, a first conductive layer 202, an intermediate insulating layer 203, a second conductive layer 204, and a cover insulating layer 205.

[0166] The base layer 201 can be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the base layer 201 can be an organic layer including an epoxy resin, an acrylic resin, or an imide-based resin. The base layer 201 can have a single layer structure or a multi-layer structure in which a plurality of layers are stacked in a third direction DR3. In one or more embodiments of the disclosure, the sensor layer 200 can omit the base layer 201.

[0167] Each of the first conductive layer 202 and the second conductive layer 204 can have a single layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3.

[0168] In one or more embodiments, each of the first conductive layer 202 and the second conductive layer 204 has a single layer structure, and can include a metal layer or a transparent conductive layer. The metal layer can include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer can include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer can include a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, graphene, or the like.

[0169] In one or more embodiments, each of the first conductive layer 202 and the second conductive layer 204 has a multi-layer structure, and can include a metal layer. The metal layer can have a three-layer structure of titanium / aluminum / titanium. The conductive layer having a multi-layer structure can include at least one metal layer and at least one transparent conductive layer.

[0170] In one or more embodiments of the disclosure, the thickness of the first conductive layer 202 can be equal to or greater than the thickness of the second conductive layer 204. When the thickness of the first conductive layer 202 is greater than the thickness of the second conductive layer 204, the resistance of a component (e.g., an electrode, a sensing pattern, or a bridging pattern, etc.) included in the first conductive layer 202 can be reduced. In addition, because the first conductive layer 202 is located below the second conductive layer 204, even if the thickness of the first conductive layer 202 increases, the probability of visible recognition of the component can be lower than the probability of visible recognition of the second conductive layer 204.

[0171] At least one of the intermediate insulating layer 203 and the cover insulating layer 205 can include an inorganic layer. The inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0172] At least one of the intermediate insulating layer 203 and the cover insulating layer 205 can include an organic layer. The organic layer can include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, an ethylene-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin.

[0173] Previously, it was described as an example that the sensor layer 200 includes the first conductive layer 202 and the second conductive layer 204, i.e., a total of two conductive layers, but is not particularly limited thereto. For example, the sensor layer 200 can include three or more conductive layers.

[0174] FIG. 6B is a cross-sectional view of a sensor layer 200 according to one or more embodiments of the disclosure.

[0175] Referring to FIG. 6A and FIG. 6B A second width 204wt of the second mesh line MS2 included in the second conductive layer 204 can be equal to or greater than a first width 202wt of the first mesh line MS1 included in the first conductive layer 202. When the user USR views the first mesh line MS1 and the second mesh line MS2 from the side, since the width of the first mesh line MS1 is smaller than the width of the second mesh line MS2, the probability that the first mesh line MS1 is visually recognized can be reduced.

[0176] Each of the first mesh line MS1 and the second mesh line MS2 can include a first metal layer M1 and a second metal layer M2 located between the first metal layer M1. For example, each of the first metal layer M1 can include titanium (Ti), and the second metal layer M2 can include aluminum (Al). However, this is merely an example, and the disclosure is not particularly limited thereto.

[0177] In one or more embodiments of the disclosure, a first thickness TK1 of the second metal layer M2 of the first mesh line MS1 and a second thickness TK2 of the second metal layer M2 of the second mesh line MS2 can be substantially the same, but the disclosure is not particularly limited thereto. For example, the first thickness TK1 can be greater than the second thickness TK2. Alternatively, the second thickness TK2 can be greater than the first thickness TK1. In one or more embodiments of the disclosure, each of the first thickness TK1 and the second thickness TK2 can be about 1,000 angstroms or greater, for example, about 6,000 angstroms.

[0178] FIG. 7 is a plan view of a display panel DP and a circuit board MFPC according to one or more embodiments of the disclosure.

[0179] Referring to FIG. 7 The display panel DP can include a first area AA1, a bending area BA, and a second area AA2. The bending area BA can be located between the first area AA1 and the second area AA2, which are spaced apart from each other in a second direction DR2. Each of the bending area BA and the second area AA2 extending in parallel to the first direction DR1 can have a width (or length) smaller than a width of the first area AA1 in the first direction DR1. An area having a short length in the direction of the bending axis can be bent more easily.

[0180] FIG. 7The plan view of the display panel DP shown in FIG. 1A is a plan view of the display panel DP in an unfolded state before assembly with other components (i.e., before modularization). A portion of the display panel DP can be bent and modularized. For example, the bending area BA can be bent such that the second area AA2 is located below (e.g., in the third direction DR3) the first area AA1.

[0181] The display driver 100C can be mounted on the second area AA2 of the display panel DP. The display driver 100C can be referred to as a first driver chip. The display driver 100C can include a driving element, such as a data driving circuit, for driving a pixel included in the display layer 100 (see FIG. 1A) of the display panel DP. FIG. 5 ) of the display panel DP.

[0182] The circuit board MFPC can be coupled to the second area AA2 of the display panel DP. The circuit board MFPC can be electrically connected to the pad PD of the display panel DP through an anisotropic conductive adhesive layer. However, one or more embodiments of the present disclosure are not particularly limited thereto. For example, the pad PD-M of the circuit board MFPC can be directly coupled to the pad PD of the display panel DP. The circuit board MFPC can be referred to as a flexible circuit board, a flexible circuit film, a multi-layer flexible substrate, or a multi-layer flexible film.

[0183] The sensor driver 200C can be mounted on the circuit board MFPC. The sensor driver 200C can be referred to as a second driver chip. Although FIG. 7 Although a structure in which the display driver 100C is mounted on the display panel DP and in which the sensor driver 200C is mounted on the circuit board MFPC is shown, the present disclosure is not limited thereto. For example, the display driver 100C can also be mounted on the circuit board MFPC.

[0184] The display panel DP includes a sensor layer 200. A sensing area 200A and a peripheral area 200NA adjacent to the sensing area 200A can be defined on the sensor layer 200. The first area AA1 can overlap some of the sensing area 200A and the peripheral area 200NA. The bending area BA and the second area AA2 can overlap another portion of the peripheral area 200NA.

[0185] The sensor layer 200 can include a plurality of first electrodes 210, a plurality of second electrodes 220, a plurality of third electrodes 230, and a plurality of fourth electrodes 240 located in the first area AA1 and the sensing area 200A.

[0186] Each of the first electrodes 210 can cross the second electrodes 220. Each of the first electrodes 210 can extend in the second direction DR2, and the first electrodes 210 can be arranged to be spaced apart from each other in the first direction DR1. Each of the second electrodes 220 can extend in the first direction DR1, and the second electrodes 220 can be arranged to be spaced apart from each other in the second direction DR2. The sensing unit SU of the sensor layer 200 can be an area in which one of the first electrodes 210 and one of the second electrodes 220 cross each other.

[0187] In FIG. 7 , six first electrodes 210 and ten second electrodes 220 can be illustrated as an example, and sixty sensing units SU can be illustrated as an example. However, the number of the first electrodes 210 and the second electrodes 220 is not limited thereto.

[0188] Each of the third electrodes 230 can extend in the second direction DR2, and the third electrodes 230 can be arranged to be spaced apart from each other in the first direction DR1. One of the third electrodes 230 can at least partially overlap one of the first electrodes 210. According to one or more embodiments of the present disclosure, an overlapping area between one of the first electrodes 210 and one of the third electrodes 230 can be adjusted to adjust a capacitance (or a coupling capacitance) between one of the first electrodes 210 and one of the third electrodes 230. The third electrode 230 can also be referred to as a ring electrode.

[0189] The fourth electrodes 240 can be arranged along the second direction DR2, and the fourth electrodes 240 can extend along the first direction DR1. One of the fourth electrodes 240 can at least partially overlap one of the second electrodes 220. According to one or more embodiments of the present disclosure, an overlapping area between one of the second electrodes 220 and one of the fourth electrodes 240 can be adjusted to adjust a capacitance (or a coupling capacitance) between one of the second electrodes 220 and one of the fourth electrodes 240.

[0190] In one or more embodiments of the present disclosure, at least some of the fourth electrodes 240 can be electrically connected to each other to form one electrode group. For example, in FIG. 7 , five of the fourth electrodes 240 can be connected to the same single trace, e.g., an auxiliary trace 240t, to form one electrode group. Accordingly, in FIG. 7 , two electrode groups arranged along the second direction DR2 are illustrated. However, the number of the fourth electrodes 240 constituting one electrode group is not limited thereto. For example, the number of the fourth electrodes 240 constituting one electrode group can be 10, and in this case, the sensor layer 200 can include one electrode group.

[0191] The sensor layer 200 can further include a plurality of first traces 210t and a plurality of second traces 220t in the peripheral area 200NA. The first traces 210t can correspond to and be electrically connected to the first electrodes 210 one-to-one. The second traces 220t can correspond to and be electrically connected to the second electrodes 220 one-to-one.

[0192] The sensor layer 200 can further include a plurality of first ring traces 230rt1, a second ring trace 230rt2, and a plurality of auxiliary traces 240t in the peripheral area 200NA.

[0193] The first ring traces 230rt1 can be connected to the third electrodes 230 one-to-one in correspondence. That is, the number of the first ring traces 230rt1 can correspond to the number of the third electrodes 230. In FIG. 7 In an embodiment, six first ring traces 230rt1 and six third electrodes 230 are illustrated as an example.

[0194] In one or more other embodiments of the disclosure, one first ring trace can be electrically connected to a plurality of third electrodes. The plurality of third electrodes connected to one first ring trace can be referred to as one electrode group. In this case, as the number of the third electrodes connected in parallel included in one electrode group increases, the resistance of one electrode group can be reduced to improve power efficiency and sensing sensitivity. Conversely, as the number of the third electrodes included in one electrode group decreases, the ring coil pattern formed using one electrode group can be implemented in a more diverse form.

[0195] The second ring trace 230rt2 can be electrically connected to the third electrodes 230. In one or more embodiments of the disclosure, the second ring trace 230rt2 can be electrically connected to all of the third electrodes 230. The second ring trace 230rt2 can include a first line portion 231t extending in the first direction DR1 and electrically connected to the third electrodes 230, a second line portion 232t extending from a first end of the first line portion 231t in the second direction DR2, and a third line portion 233t extending from a second end of the first line portion 231t in the second direction DR2.

[0196] It should be noted that the third electrodes 230, the first ring traces 230rt1, and the second line portion 232t and the third line portion 233t of the second ring trace 230rt2 can each have a first electrode portion, a second electrode portion, and / or a third electrode portion. For example, each of the electrodes or each of the lines described herein can have a first electrode portion in the first area AA1, a second electrode portion in the bending area BA, and a third electrode portion in the second area AA2.

[0197] Each of the third electrodes 230, the first portion of the first annular trace 230rt1, the first portion of the second line portion 232t, and the first portion of the third line portion 233t are respectively disposed in the first area AA1, and can respectively correspond to the first electrode portion. The second portion of the first annular trace 230rt1, the second portion of the second line portion 232t, and the second portion of the third line portion 233t are respectively disposed in the bending area BA, and can respectively correspond to the second electrode portion. The third portion of the first annular trace 230rt1, the third portion of the second line portion 232t, and the third portion of the third line portion 233t are respectively disposed in the second area AA2, and can respectively correspond to the third electrode portion. In one or more embodiments of the present disclosure, each of the resistance of the second line portion 232t and the resistance of the third line portion 233t can be substantially equal to the resistance of one of the third electrodes 230. Thus, there can be an effect in which the second line portion 232t and the third line portion 233t effectively serve as the third electrodes 230 located in the peripheral area 200NA. For example, one of the second line portion 232t and the third line portion 233t and one of the third electrodes 230 can form a coil. Thus, a pen located on an area adjacent to the peripheral area 200NA can also be sufficiently charged by a loop including the second line portion 232t or the third line portion 233t.

[0198] In one or more embodiments of the present disclosure, in order to adjust the resistance of the second line portion 232t and the resistance of the third line portion 233t, the width of each of the second line portion 232t and the third line portion 233t in the first direction DR1 can be adjusted. However, this is merely an example, and the first line portion 231t, the second line portion 232t, and the third line portion 233t can have substantially the same width.

[0199] The auxiliary traces 240t can be spaced apart from each other, and the sensing area 200A is between the auxiliary traces 240t. FIG. 7 An example in which two electrode groups are arranged is illustrated. The auxiliary traces 240t connected to the five fourth electrodes 240 located at the upper side and the auxiliary traces 240t connected to the five fourth electrodes 240 located at the lower side can be spaced apart from each other, and the sensing area 200A is between the auxiliary traces 240t. However, the present disclosure is not particularly limited thereto.

[0200] According to one or more embodiments of the disclosure, at least a portion of each of the first trace 210t, the second trace 220t, the first loop trace 230rt1, the second loop trace 230rt2, and the plurality of auxiliary traces 240t can have a multi-layer structure. For example, portions of the first trace 210t, the second trace 220t, the first loop trace 230rt1, the second loop trace 230rt2, and the plurality of auxiliary traces 240t extending in the second direction DR2 can have a multi-layer structure. For example, these portions can be located in the bending area BA and the second area AA2. Each of these portions can include a first line portion included in the first conductive layer 202 (see FIG. 6A ) and a second line portion included in the second conductive layer 204 (see FIG. 6A ).

[0201] FIG. 8A is a plan view illustrating a first conductive layer 202SU of a sensing unit according to one or more embodiments of the disclosure. FIG. 8B is a plan view illustrating a second conductive layer 204SU of a sensing unit according to one or more embodiments of the disclosure. FIG. 9 is a cross-sectional view of the sensor layer 200 taken along the line I-I' of FIG. 8A and FIG. 8B .

[0202] The shape of the sensing unit SU described with reference to FIG. 8A and FIG. 8B is merely an example, and the shape of the sensing unit SU is not limited thereto.

[0203] With reference to FIG. 8A , FIG. 8B and FIG. 9 , the first electrode 210 can include first sensing patterns 210-sp and a first bridge pattern 210-bp. The first sensing patterns 210-sp and the first bridge pattern 210-bp can be electrically connected to each other by the first contact portion CNa. The second electrode 220 can be located on the same layer as the first sensing patterns 210-sp. For example, the first sensing patterns 210-sp can be spaced apart from each other, and the second electrode 220 is between them. The first bridge pattern 210-bp can be located on a different layer from the second electrode 220, and can be insulated from and can cross the second electrode 220.

[0204] The third electrode 230 can be located on the same layer as the first bridge pattern 210-bp. An opening around the first bridge pattern 210-bp can be defined in the third electrode 230. The third electrode 230 can overlap the first sensing patterns 210-sp. Accordingly, a coupling capacitor can be defined between the first electrode 210 and the third electrode 230.

[0205] The fourth electrode 240 can include a second sensing pattern 240-sp and a second bridge pattern 240-bp. The second sensing pattern 240-sp and the second bridge pattern 240-bp can be electrically connected to each other through the second contact CNb. The third electrode 230 can be located on the same layer as the second sensing pattern 240-sp. For example, the second sensing pattern 240-sp can be spaced apart from each other, and the third electrode 230 is between them. The second bridge pattern 240-bp is located on a different layer from the third electrode 230, and can be insulated from the third electrode 230 and can cross the third electrode 230.

[0206] In one or more embodiments of the disclosure, the first conductive layer 202SU can include the first bridge pattern 210-bp, the third electrode 230, and the second sensing pattern 240-sp. The second conductive layer 204SU can include the first sensing pattern 210-sp, the second electrode 220, and the second bridge pattern 240-bp.

[0207] In one or more embodiments of the disclosure, the first conductive layer 202SU can further include dummy patterns DMP. Since the dummy patterns DMP are located in empty spaces, the probability of visible recognition of the corresponding patterns due to reflection of external light can be reduced. In other words, an electronic device 1000 (see FIG. 1A ) with improved visibility due to reflection of external light can be provided. Each of the dummy patterns DMP can be electrically floating or electrically grounded. In one or more embodiments of the disclosure, the dummy patterns DMP can be omitted.

[0208] Referring to FIG. 8A and FIG. 8B , the area occupied by components included in the first electrode 210 and the second electrode 220 in the second conductive layer 204SU within one sensing unit SU can be greater than the area occupied by components included in the third electrode 230 and the fourth electrode 240. The change in capacitance due to the first input 2000 (see FIG. 5 ) can increase as the distance becomes shorter. Accordingly, components for sensing the first input 2000 (see FIG. 5 ) can be located in a relatively large area on a layer adjacent to the surface of the electronic device 1000 (see FIG. 1A ). Accordingly, the touch performance can be improved.

[0209] Previously, FIG. 6A to FIG. 9The structure in which the first electrode 210, the second electrode 220, the third electrode 230, and the fourth electrode 240 are respectively located in two conductive layers 202SU and 204SU is shown, but the present disclosure is not particularly limited thereto. For example, the first electrode 210, the second electrode 220, the third electrode 230, and the fourth electrode 240 can be divided into three or four conductive layers.

[0210] In one or more embodiments of the present disclosure, the third electrode 230 to which a signal is applied in the charging driving mode can be included in a third conductive layer located below the first conductive layer 202SU and the second conductive layer 204SU. For example, the third conductive layer can be disposed below the base layer 201. The third conductive layer can be located between the base layer 201 and the display layer 100, can be located below the display layer 100, or can be included in the display layer 100.

[0211] The first electrode 210, the second electrode 220, and the fourth electrode 240 can be included in the first conductive layer 202SU and the second conductive layer 204SU. For example, if the third electrode 230 is implemented as a separate conductive layer, such as a third conductive layer, the shape of the third electrode 230 can be more freely designed. For example, the third electrode 230 can be disposed in a form including a plurality of coils. Further, by using the third conductive layer, the third electrode 230 can be more densely disposed, and in this case, pen sensing sensitivity can be improved. In one or more other embodiments of the present disclosure, the third conductive layer can include the fourth electrode 240 instead of the third electrode 230.

[0212] FIG. 10A is an enlarged plan view of a region AA' of FIG. 8A FIG. 10B is an enlarged plan view of a region BB' of FIG. 8B

[0213] Referring to FIG. 8A , FIG. 8B , FIG. 10A and FIG. 10B , each of the first electrode 210, the second electrode 220, the third electrode 230, the fourth electrode 240, and the dummy pattern DMP can have a mesh structure. Each of the mesh structures can include a plurality of mesh lines. Each of the plurality of mesh lines can have a shape extending in one direction (e.g., a predetermined direction), and the plurality of mesh lines can be connected to each other. The mesh lines can have various shapes, such as straight lines, lines with protrusions, or uneven lines. An opening in which the mesh structure is not disposed (e.g., provided or formed) can be defined in each of the first electrode 210, the second electrode 220, the third electrode 230, the fourth electrode 240, and the dummy pattern DMP.

[0214] FIG. 10A and​​FIG. 10B An example is shown in which the mesh structure includes mesh lines extending in a first cross direction CDR1 intersecting the first direction DR1 and the second direction DR2, and mesh lines extending in a second cross direction CDR2 intersecting the first cross direction CDR1. However, the extension directions of the mesh lines constituting the mesh structure are not particularly limited to the directions shown in FIG. 10A and FIG. 10B For example, the mesh structure can include only mesh lines extending in the first direction DR1 and the second direction DR2, or can include mesh lines extending in the first direction DR1, the second direction DR2, the first cross direction CDR1, and the second cross direction CDR2. That is, the mesh structure can be changed into various forms.

[0215] FIG. 11 is a view showing the operation of a sensor driver according to one or more embodiments of the present disclosure.

[0216] Referring to FIG. 5 and FIG. 11 , the sensor driver 200C can be configured to be selectively driven in one of a first operation mode DMD1, a second operation mode DMD2, and a third operation mode DMD3.

[0217] The first operation mode DMD1 can be referred to as a touch and pen standby mode, the second operation mode DMD2 can be referred to as a touch active and pen standby mode, and the third operation mode DMD3 can be referred to as a pen active mode. The first operation mode DMD1 can be a mode in which the first input 2000 and the second input 3000 are awaited. The second operation mode DMD2 can be a mode in which the first input 2000 is sensed and the second input 3000 is awaited. The third operation mode DMD3 can be a mode for sensing the second input 3000.

[0218] In one or more embodiments of the present disclosure, the sensor driver 200C can be first driven in the first operation mode DMD1. When the first input 2000 is sensed in the first operation mode DMD1, the sensor driver 200C can be switched (or changed) to the second operation mode DMD2. Alternatively, if the second input 3000 is sensed in the first operation mode DMD1, the sensor driver 200C can be switched (or changed) to the third operation mode DMD3.

[0219] In one or more embodiments of the disclosure, the sensor driver 200C can be switched to a third operation mode DMD3 if the second input 3000 is sensed in the second operation mode DMD2. The sensor driver 200C can be switched to the first operation mode DMD1 when the first input 2000 is released (or no longer detected) in the second operation mode DMD2. The sensor driver 200C can be switched to the first operation mode DMD1 when the second input 3000 is released (or no longer detected) in the third operation mode DMD3.

[0220] FIG. 12 is a view illustrating an operation of a sensor driver according to one or more embodiments of the disclosure.

[0221] Referring to FIG. 5 , FIG. 11 and FIG. 12 , operations in the first operation mode DMD1, the second operation mode DMD2, and the third operation mode DMD3 are shown in order of time t.

[0222] In the first operation mode DMD1, the sensor driver 200C can be repeatedly driven in the second mode MD2-d and the first mode MD1-d. During the second mode MD2-d, the sensor layer 200 can be scanned to detect the second input 3000. During the first mode MD1-d, the sensor layer 200 can be scanned to detect the first input 2000. FIG. 12 An example in which the sensor driver 200C operates in the first mode MD1-d continuously (e.g., immediately) after the second mode MD2-d is shown, but the order is not limited thereto.

[0223] In the second operation mode DMD2, the sensor driver 200C can be repeatedly driven in the second mode MD2-d and the first mode MD1. During the second mode MD2-d, the sensor layer 200 can be scanned to detect the second input 3000. During the first mode MD1, the sensor layer 200 can be scanned to detect coordinates of the first input 2000.

[0224] In the third operation mode DMD3, the sensor driver 200C can be driven in the second mode MD2. During the second mode MD2, the sensor layer 200 can be scanned to detect coordinates of the second input 3000. In the third operation mode DMD3, the sensor driver 200C can not operate in the first mode MD1-d or MD1 until the second input 3000 is released (or not detected).

[0225] FIG. 13 is a plan view for explaining the first mode according to one or more embodiments of the disclosure.

[0226] Reference FIG. 5 、 FIG. 12 and FIG. 13 , the first mode MD1-d of the first operation mode DMD1 and the first mode MD1 of the second operation mode DMD2 can include a mutual capacitance detection mode. FIG. 13 is a view for explaining the mutual capacitance detection mode in the first mode MD1-d of the first operation mode DMD1 and / or the first mode MD1 of the second operation mode DMD2.

[0227] In the mutual capacitance detection mode, the sensor driver 200C can sequentially provide the transmission signal TX to the first electrodes 210, and can detect the coordinates of the first input 2000 by using the reception signal RX detected through the second electrodes 220. For example, the sensor driver 200C can be configured to calculate the input coordinates by sensing a change in mutual capacitance between the first electrodes 210 and the second electrodes 220.

[0228] FIG. 13 An example in which the transmission signal TX is provided to one first electrode 210 and the reception signal RX is output from the second electrode 220 is shown. For the sake of clarifying the representation of the signals, only one first electrode 210 to which the transmission signal TX is provided can be shown in bold in FIG. 13 The sensor driver 200C can detect the input coordinates of the first input 2000 by sensing a change in capacitance between each of the second electrodes 220 and the first electrode 210.

[0229] In one or more other embodiments of the disclosure, at least one of the first mode MD1-d of the first operation mode DMD1 and the first mode MD1 of the second operation mode DMD2 can further include a self-capacitance detection mode. In the self-capacitance detection mode, the sensor driver 200C can be configured to output a driving signal to the first electrodes 210 and the second electrodes 220, and can be configured to calculate the input coordinates by sensing a change in capacitance of each of the second electrodes 220.

[0230] In the first mode MD1-d of the first operation mode DMD1 and the first mode MD1 of the second operation mode DMD2, all of the third electrodes 230 and the fourth electrodes 240 can be grounded. Accordingly, touch noise can be reduced or can be prevented from flowing through the third electrodes 230 and the fourth electrodes 240.

[0231] FIG. 14 is a plan view for explaining the second mode according to one or more embodiments of the disclosure. FIG. 15A is a graph showing a waveform of a first signal according to one or more embodiments of the disclosure. FIG. 15Bis a graph showing a waveform of a second signal according to one or more embodiments of the present disclosure.

[0232] Referring to FIG. 14 , FIG. 15A and FIG. 15B , the second mode MD2 can include a charge driving mode. The charge driving mode can include a search charge driving mode and a tracking charge driving mode.

[0233] The search charge driving mode can be a driving mode before sensing a position of a pen. Accordingly, the first signal SG1 and / or the second signal SG2 can be provided to all channels included in the sensor layer 200. That is, the entire area of the sensor layer 200 can be scanned in the search charge driving mode. When the pen PN (see FIG. 5 ) is sensed in the search charge driving mode, the sensor driver 200C can drive the sensor layer 200 to perform tracking charging. For example, in the tracking charge driving mode, the sensor driver 200C can sequentially output the first signal SG1 and the second signal SG2 to an area overlapping a point at which the pen PN is sensed, rather than to the entire sensor layer 200.

[0234] In the charge driving mode, the sensor driver 200C can apply the first signal SG1 to one pad and can apply the second signal SG2 to another pad. The second signal SG2 can be an inverse signal of the first signal SG1. For example, the first signal SG1 can be a sine wave signal.

[0235] Because the first signal SG1 and the second signal SG2 are applied to at least two pads, the current RFS can have a current path flowing from one pad to another pad. In addition, because the first signal SG1 and the second signal SG2 are sine wave signals having an inverse relationship with each other, the direction of the current RFS can be periodically changed. In one or more other embodiments of the present disclosure, the first signal SG1 and the second signal SG2 can be square wave signals having an inverse relationship with each other.

[0236] When the first signal SG1 and the second signal SG2 have an inverse relationship, noise induced by the first signal SG1 in the display layer 100 (see FIG. 4 ) can be canceled by noise induced by the second signal SG2. Accordingly, a flickering phenomenon can not occur in the display layer 100, and the display quality of the display layer 100 can be improved.

[0237] In one or more other embodiments of the disclosure, the first signal SG1 can be a sine wave signal. However, the disclosure is not limited thereto, and the first signal SG1 can be a square wave signal. Also, the second signal SG2 can have a constant voltage V (e.g., a predetermined constant voltage V). For example, the second signal SG2 can be a ground voltage. In other words, a pad to which the second signal SG2 is applied can be regarded as being grounded. Even in this case, the current RFS can flow from one pad to another pad. Also, even if the other pad is grounded, since the first signal SG1 is a sine wave signal or a square wave signal, the direction of the current RFS can be periodically changed.

[0238] Reference FIG. 14 , the first signal SG1 can be provided to one pad connected to one first loop trace 230rt1, and the second signal SG2 can be provided to one pad connected to a second loop trace 230rt2. The current RFS can flow through a current path defined by one first loop trace 230rt1, one third electrode 230 connected to one first loop trace 230rt1, and a portion of the second loop trace 230rt2. The current path can have a coil shape. That is, the first signal SG1 can be provided to one third electrode 230 connected to one first loop trace 230rt1, and the second signal SG2 can be provided to at least another third electrode 230 connected to the second loop trace 230rt2. Accordingly, in the charging driving mode of the second mode, the RLC resonance circuit of the pen PN can be charged through the current path.

[0239] According to one or more embodiments of the disclosure, the current path of the loop coil pattern can be implemented by components included in the sensor layer 200. Accordingly, the electronic device 1000 (see FIG. 1A ) can charge the pen PN using the sensor layer 200. Accordingly, since a coil for charging the pen PN does not need to be separately added, the electronic device 1000 can not increase thickness and weight, and can not reduce flexibility.

[0240] In the charging driving mode, the first electrode 210, the second electrode 220, and the fourth electrode 240 can be grounded, can have a constant voltage applied, or can be electrically floating. For example, the first electrode 210, the second electrode 220, and the fourth electrode 240 can be floating. In this case, the current RFS can not flow through the first electrode 210, the second electrode 220, and the fourth electrode 240.

[0241] FIG. 16 is a view of a pen PN according to one or more embodiments of the disclosure.

[0242] Reference FIG. 16The pen PN can include a housing PN-H, a pen tip PN-T, an inductor L, a capacitor C, a resistor R, an elastic body PN-ED, a pressure capacitor C-P, a switch SW-B, and a button capacitor C-B. The pen PN can not include active elements such as a power source, a transistor, or a diode, however the switch SW-B is connected to the button capacitor C-B. The components included in the pen PN are not limited to the above-described components. At least a portion of the above-described components can be omitted, and other components can be added.

[0243] In one or more embodiments of the disclosure, the pen tip PN-T can include a non-conductive material. The pen tip PN-T can have a structure protruding to the outside of the housing PN-H. The pen tip PN-T can be coupled separately from the housing PN-H, and can be a replaceable component.

[0244] In one or more embodiments of the disclosure, the resistor R, the inductor L, and the capacitor C can be connected in series to each other. Accordingly, the pen PN can have a structure having a resonance frequency and selectivity, which is a characteristic of an RLC series circuit. In this case, the frequency of each of the signals provided to the sensor layer 200 (for example, if the sensor layer 200 is driven to be charged) can correspond to the resonance frequency of the pen PN. The capacitor C, the pressure capacitor C-P, and the button capacitor C-B can have a structure connected in parallel to each other. For reference, if the switch SW-B is on, the button capacitor C-B can be connected in parallel to the capacitor C.

[0245] In one or more embodiments of the disclosure, the button capacitor C-B can be electrically connected to the capacitor C or disconnected from the capacitor C when the switch SW-B is on and off. That is, the switch SW-B can be turned on and off to enable the pen PN to respond to other resonance frequencies. For example, a button can be provided on the outer peripheral surface of the housing PN-H. When the button is pressed, the switch SW-B can be turned on, and the button capacitor C-B can be electrically connected to the capacitor C, and thus the capacitance of the entire pen PN can increase.

[0246] In one or more embodiments of the disclosure, the capacitor C can be provided by cutting some of a plurality of capacitors connected in parallel to each other. For example, during a process of manufacturing the pen PN, the pen PN can tune the capacitor C by cutting or disabling some of a plurality of capacitors, thereby matching a target resonance frequency.

[0247] In one or more embodiments of the disclosure, if the pen tip PN-T is partially inserted into the housing PN-H by the pen pressure, an area, a distance, or an area and a distance corresponding to the capacitance of the pressure capacitor C-P can be changed. Accordingly, the capacitance of the pressure capacitor C-P can be changed. For example, if the pen pressure is applied to the pen PN, the capacitance of the pressure capacitor C-P can increase, and the resonance frequency of the pen PN can correspondingly decrease. Thereafter, if the pen pressure is removed, the capacitance of the pressure capacitor C-P can return to its original state due to the elastic body PN-ED.

[0248] FIG. 17A is a view for explaining an operation of the pen PN according to one or more embodiments of the disclosure. FIG. 17B is a view for explaining an operation of the sensor layer 200 according to one or more embodiments of the disclosure.

[0249] Referring to FIG. 14 , FIG. 16 , FIG. 17A and FIG. 17B , the second mode MD2 can include a charging portion MD2-ch and a discharging portion MD2-dc. The charging portion MD2-ch can correspond to a charging driving mode, and the discharging portion MD2-dc can correspond to a pen sensing driving mode.

[0250] The first signal SG1 and the second signal SG2 can be provided to the sensor layer 200 during a first time period. The first time period can correspond to one charging portion MD2-ch. During the first time period, the pen PN adjacent to the sensor layer 200 can be charged. For example, the inductor L can generate a current through a magnetic field generated in the sensor layer 200. The generated current can be delivered to the capacitor C. The capacitor C can charge the current input from the inductor L. Thereafter, the capacitor C can release the charged current to the inductor L, and the inductor L can emit a magnetic field at a resonance frequency.

[0251] A portion of the magnetic field emitted from the pen PN can correspond to the discharging portion MD2-dc. Due to the magnetic field emitted by the pen PN, an induced current can flow in the sensor layer 200, and the induced current can be transmitted to the sensor driver 200C as a reception signal (e.g., a sensing signal, a signal, etc.).

[0252] In one or more embodiments of the disclosure, the charging driving voltage of the sensor layer 200 can have a sine wave or a square wave, and FIG. 17B An example in which the charging driving voltage has a sine wave is illustrated. The voltage charged to the pen PN or the voltage released from the pen PN can have a sine wave.

[0253] FIG. 18Ais a plan view for explaining a second mode according to one or more embodiments of the disclosure. FIG. 18B is a view for explaining the second mode based on one sensing unit SU according to one or more embodiments of the disclosure.

[0254] Referring to FIG. 18A and FIG. 18B , the second mode can include a charge driving mode and a pen sensing driving mode. FIG. 18A and FIG. 18B is a view for explaining the pen sensing driving mode.

[0255] Referring to FIG. 18A , in the pen sensing driving mode, a first reception signal PRX1 can be output from the first electrode 210, and a second reception signal PRX2 can be output from the second electrode 220. FIG. 18B One sensing unit SU is shown through which a first induced current Ia, a second induced current Ib, a third induced current Ic, and a fourth induced current Id generated by a pen PN flow.

[0256] Referring to FIG. 18A and FIG. 18B , the wiring direction of one electrode and the other electrode of the sensor layer 200 that overlap each other can be different from each other. For example, the wiring direction of the first electrode 210 and the wiring direction of the third electrode 230 can be different from each other. Also, the wiring direction of the second electrode 220 and the wiring direction of the fourth electrode 240 can be different from each other. The wiring direction can be a direction in which a trace protrudes and extends from a position at which the electrode and the trace are connected to each other.

[0257] For example, in FIG. 18B , the first electrode 210 and the first trace 210t can be connected at a lower portion of the sensing unit SU, and the first trace 210t can protrude and extend from the lower portion of the first electrode 210. The third electrode 230 and the second loop-shaped trace 230rt2 can be connected at an upper portion of the sensing unit SU, and the second loop-shaped trace 230rt2 can protrude and extend from the upper portion of the third electrode 230. The second electrode 220 and the second trace 220t can be connected at a right side of the sensing unit SU, the second trace 220t can protrude and extend from the right side of the second electrode 220, and the fourth electrode 240 and the auxiliary trace 240t can be connected at a left side of the sensing unit SU, and the auxiliary trace 240t can protrude and extend from the left side of the fourth electrode 240.

[0258] The RLC resonance circuit of the pen PN can emit a magnetic field at a resonance frequency while discharging the charged electric charge. By the magnetic field provided from the pen PN, a first induced current Ia can be generated in the first electrode 210, and a second induced current Ib can be generated in the second electrode 220. Also, a third induced current Ic can be generated in the third electrode 230, and a fourth induced current Id can be generated in the fourth electrode 240.

[0259] The first coupling capacitor Ccp1 can be located between the third electrode 230 and the first electrode 210, and the second coupling capacitor Ccp2 can be located between the fourth electrode 240 and the second electrode 220. The third induced current Ic can be transferred to the first electrode 210 through the first coupling capacitor Ccp1, and the fourth induced current Id can be transferred to the second electrode 220 through the second coupling capacitor Ccp2.

[0260] The sensor driver 200C can receive a first reception signal PRX1a based on the first induced current Ia and the third induced current Ic from the first electrode 210, and can receive a second reception signal PRX2a based on the second induced current Ib and the fourth induced current Id from the second electrode 220. The sensor driver 200C can detect an input coordinate of the pen PN based on the first reception signal PRX1a and the second reception signal PRX2a.

[0261] When the sensor driver 200C receives the first reception signal PRX1a from the first electrode 210 and the second reception signal PRX2a from the second electrode 220, all one ends of the third electrode 230 and the fourth electrode 240 can be floated. Accordingly, by the coupling between the first electrode 210 and the third electrode 230 and by the coupling between the second electrode 220 and the fourth electrode 240, compensation of the sensing signal can be improved or maximized.

[0262] Also, the other ends of the third electrode 230 and the fourth electrode 240 can be grounded or floated. Accordingly, by the coupling between the first electrode 210 and the third electrode 230 and the coupling between the second electrode 220 and the fourth electrode 240, the third induced current Ic and the fourth induced current Id can be sufficiently transferred to the first electrode 210 and the second electrode 220, respectively.

[0263] FIG. 19 FIG. 1 is a plan view illustrating a display panel DP and a circuit board MFPC according to one or more embodiments of the present disclosure.

[0264] Reference FIG. 7 and FIG. 19A portion of the display panel DP can be bent and modularized. For example, the bent area BA can be bent such that the second area AA2 is located below (e.g., in the third direction DR3) the first area AA1. Accordingly, the second area AA2 of the display panel DP and the circuit board MFPC can be located below the first area AA1.

[0265] FIG. 19 An example in which the first measurement area TA1, the second measurement area TA2, and the third measurement area TA3 overlap the sensing area 200A is illustrated. The first measurement area TA1 and the second measurement area TA2 can not overlap the second area AA2 and the circuit board MFPC, and the third measurement area TA3 can overlap (e.g., in the thickness direction) the second area AA2 and the circuit board MFPC. An input can be provided corresponding to each of the first measurement area TA1, the second measurement area TA2, and the third measurement area TA3, and a signal-to-noise ratio can be measured accordingly.

[0266] A portion of the first loop trace 230rt1 located in the first area AA1 and a portion of the first loop trace 230rt1 located in the second area AA2 can overlap each other. Also, a portion of the first loop trace 230rt1 located in the first area AA1 and the plurality of connection lines 230c included in the circuit board MFPC can overlap each other.

[0267] Unlike some embodiments of the disclosure, if the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the second area AA2 are different from each other and are affected by each other, the first magnetic field and the second magnetic field can cancel each other out. Accordingly, the strength of the magnetic field provided by the electronic device 1000 (see FIG. 1A ) can be reduced. In this case, the pen PN can not be sufficiently charged, and the magnetic field emitted from the pen PN can also be insufficient. The signal-to-noise ratio of the third measurement area TA3 can be less than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Accordingly, the sensing sensitivity of the pen PN of the electronic device 1000 (see FIG. 1A ) can be reduced.

[0268] According to one or more embodiments of the disclosure, a structure in which the first magnetic field generated in the first area AA1 and the second magnetic field generated in the second area AA2 or the circuit board MFPC do not cancel each other out can be provided. For example, the arrangement of the first loop trace 230rt1, the second loop trace 230rt2, or the plurality of connection lines 230c can be adjusted so that the direction of the first magnetic field generated in the first area AA1 is the same as the direction of the second magnetic field generated in the second area AA2 or the circuit board MFPC. Alternatively, a shielding structure can be applied to the electronic device 1000 so that the second magnetic field generated in the second area AA2 or the circuit board MFPC does not affect the first magnetic field generated in the first area AA1. Accordingly, the signal-to-noise ratio of the third measurement area TA3 can be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Accordingly, the sensing sensitivity of the pen PN of the electronic device 1000 (see FIG. 1A ) can be improved.

[0269] FIG. 20 is a view of a display panel DP and a circuit board MFPC according to one or more embodiments of the disclosure.

[0270] Referring to FIG. 7 , FIG. 19 and FIG. 20 , the first loop trace 230rt1 can include a first-first loop trace 230rt11, a first-second loop trace 230rt12, a first-third loop trace 230rt13, a first-fourth loop trace 230rt14, a first-fifth loop trace 230rt15, and a first-sixth loop trace 230rt16.

[0271] The second line portion 232t, the first-first loop trace 230rt11 to the first-sixth loop trace 230rt16, and the third line portion 233t can be sequentially arranged along the first direction DR1. For example, in the display panel DP, the second line portion 232t, the first-first loop trace 230rt11 to the first-sixth loop trace 230rt16, and the third line portion 233t can extend from the first area AA1 toward the second area AA2 via the bending area BA.

[0272] The circuit board MFPC can include a plurality of connection lines 230c that are correspondingly electrically connected to the second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t. The plurality of connection lines 230c can include a first connection line 230c1, a second connection line 230c2, a third connection line 230c3, a fourth connection line 230c4, a fifth connection line 230c5, a sixth connection line 230c6, a seventh connection line 230c7, and an eighth connection line 230c8.

[0273] According to one or more embodiments of the present disclosure, the arrangement order of the third electrode 230 can be different from that of the second to seventh connection lines 230c2 to 230c7 that are correspondingly electrically connected to the third electrode 230. Also, the arrangement order of the second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t can be different from that of the first to eighth connection lines 230c1 to 230c8 that are correspondingly electrically connected to each other. For example, the second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t can be sequentially arranged in the first direction DR1, and at least some of the first to eighth connection lines 230c1 to 230c8 can be sequentially arranged in a direction opposite to the first direction DR1.

[0274] In one or more embodiments of the present disclosure, all of the first to eighth connection lines 230c1 to 230c8 can be sequentially arranged in a direction opposite to the first direction DR1. In this case, the first connection line 230c1 electrically connected to the second line portion 232t can be located at the rightmost side, and the eighth connection line 230c8 electrically connected to the third line portion 233t can be located at the leftmost side. That is, if the second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t are arranged in a forward order, the first to eighth connection lines 230c1 to 230c8 can be arranged in a reverse order.

[0275] In one or more embodiments of the disclosure, only the second connection line 230c2 to the seventh connection line 230c7 among the first connection line 230c1 to the eighth connection line 230c8 electrically connected to the first-first loop trace 230rt11 to the first-sixth loop trace 230rt16 among the first connection line 230c1 to the eighth connection line 230c8 can be arranged in a direction opposite to the first direction DR1. In this case, the first connection line 230c1, the seventh connection line 230c7, the sixth connection line 230c6, the fifth connection line 230c5, the fourth connection line 230c4, the third connection line 230c3, the second connection line 230c2, and the eighth connection line 230c8 can be sequentially arranged in the first direction DR1.

[0276] According to one or more embodiments of the disclosure, the circuit board MFPC can further include a plurality of bridge lines BL. The bridge lines BL can include a first bridge line BL1, a second bridge line BL2, a third bridge line BL3, a fourth bridge line BL4, a fifth bridge line BL5, a sixth bridge line BL6, a seventh bridge line BL7, and an eighth bridge line BL8. The first bridge line BL1, the second bridge line BL2, the third bridge line BL3, the fourth bridge line BL4, the fifth bridge line BL5, the sixth bridge line BL6, the seventh bridge line BL7, and the eighth bridge line BL8 can be electrically connected to the first connection line 230c1 to the eighth connection line 230c8 in a one-to-one correspondence. In addition, the first bridge line BL1, the second bridge line BL2, the third bridge line BL3, the fourth bridge line BL4, the fifth bridge line BL5, the sixth bridge line BL6, the seventh bridge line BL7, and the eighth bridge line BL8 can be electrically connected to the second line portion 232t and the first-first loop trace 230rt11 to the first-sixth loop trace 230rt16 and the third line portion 233t in a one-to-one correspondence.

[0277] The first bridge line BL1, the second bridge line BL2, the third bridge line BL3, the fourth bridge line BL4, the fifth bridge line BL5, the sixth bridge line BL6, the seventh bridge line BL7, and the eighth bridge line BL8 can extend in the first direction DR1 and can be arranged to be spaced apart from each other in the second direction DR2. However, this is only an example, and if the arrangement order of the second line portion 232t, the first-first loop trace 230rt11 to the first-sixth loop trace 230rt16, and the third line portion 233t and the arrangement order of the corresponding electrically connected first connection line 230c1 to the eighth connection line 230c8 are differently adjusted, the first bridge line BL1, the second bridge line BL2, the third bridge line BL3, the fourth bridge line BL4, the fifth bridge line BL5, the sixth bridge line BL6, the seventh bridge line BL7, and the eighth bridge line BL8 can have various shapes and can be variously arranged.

[0278] According to one or more embodiments of the present disclosure, each of the second line portion 232t, the first-first to first-sixth looped traces 230rt11 to 230rt16, and the third line portion 233t and the first to eighth connection lines 230c1 to 230c8 electrically connected thereto, respectively, can be spaced apart from each other in the first direction DR1. For example, one looped trace and one connection line electrically connected thereto can be spaced apart from each other in the first direction DR1.

[0279] Referring to FIG. 2A together FIG. 19 The bending area BA can be bent, and the second area AA2 and the circuit board MFPC can be located below the first area AA1. In this case, a bending edge BA-E can be defined in the bending area BA. According to one or more embodiments of the present disclosure, if the display panel DP is bent, the first to eighth bridge lines BL1 to BL8 can be located within a limited distance (e.g., a predetermined distance) DT from the bending edge BA-E. For example, the limited distance (e.g., the predetermined distance) DT can be about 50 mm, but the present disclosure is not particularly limited thereto. In an area within the limited distance DT from the bending edge BA-E, the arrangement order of the second line portion 232t, the first-first to first-sixth looped traces 230rt11 to 230rt16, and the third line portion 233t can be changed.

[0280] The lines having the same arrangement order as the second line portion 232t, the first-first to first-sixth looped traces 230rt11 to 230rt16, and the third line portion 233t can overlap each other on a plane, and the directions of the overlapping magnetic fields can be opposite, and thus the magnetic fields can cancel each other out. Accordingly, the positions of the first to eighth bridge lines BL1 to BL8 can be closer to the bending edge BA-E, and an area in the magnetic field can be further reduced in a state in which the display panel DP is bent.

[0281] According to one or more embodiments of the disclosure, if the bending area BA of the display panel DP is bent and assembled, the direction of the first magnetic field generated in the first area AA1 in the charging driving mode and the direction of the second magnetic field generated in the circuit board MFPC can be the same. Accordingly, the magnetic field in the third measurement area TA3 and the area adjacent thereto can not be canceled out. For example, the strength of the magnetic field received by the pen PN adjacent to the third measurement area TA3 can be equal to or greater than the strength of the magnetic field received by the pen PN adjacent to the first measurement area TA1 or the second measurement area TA2. Accordingly, the signal-to-noise ratio of the third measurement area TA3 can be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Accordingly, the sensing sensitivity of the pen PN of the electronic device 1000 (see FIG. 1A ) can be improved.

[0282] FIG. 21 is a view of a display panel and a circuit board MFPC according to one or more embodiments of the disclosure. In the description of FIG. 21 , the same reference numerals can be given to components identical to those of FIG. 20 , and detailed descriptions thereof will be omitted.

[0283] Referring to FIG. 7 , FIG. 19 and FIG. 21 , the arrangement order of the second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t can be different from the arrangement order of the first to eighth connection lines 230c1 to 230c8 which are electrically connected to each other, respectively. For example, the second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t can be sequentially arranged along the first direction DR1, and at least some of the first to eighth connection lines 230c1 to 230c8 can be sequentially arranged along a direction opposite to the first direction DR1.

[0284] The arrangement order of the second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t can be changed within the display panel DP. For example, the arrangement order can be changed in the non-active area 200NA.

[0285] According to one or more embodiments of the disclosure, the display panel DP can include a first bridge line BL1a, a second bridge line BL2a, a third bridge line BL3a, a fourth bridge line BL4a, a fifth bridge line BL5a, a sixth bridge line BL6a, a seventh bridge line BL7a, and an eighth bridge line BL8a. The first bridge line BL1a to the eighth bridge line BL8a can be arranged in the first area AA1. Also, the first bridge line BL1a to the eighth bridge line BL8a can be located in the peripheral area 200NA.

[0286] The second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t can be electrically connected to the first bridge line BL1a, the second bridge line BL2a, the third bridge line BL3a, the fourth bridge line BL4a, the fifth bridge line BL5a, the sixth bridge line BL6a, the seventh bridge line BL7a, and the eighth bridge line BL8a in a one-to-one correspondence. The first to eighth connection lines 230c1 to 230c8 can be electrically connected to the first bridge line BL1a, the second bridge line BL2a, the third bridge line BL3a, the fourth bridge line BL4a, the fifth bridge line BL5a, the sixth bridge line BL6a, the seventh bridge line BL7a, and the eighth bridge line BL8a in a one-to-one correspondence.

[0287] The arrangement order of the first to eighth connection lines 230c1 to 230c8 that receive the same signals as the second line portion 232t, the first-first to first-sixth loop traces 230rt11 to 230rt16, and the third line portion 233t can be changed by the first bridge line BL1a, the second bridge line BL2a, the third bridge line BL3a, the fourth bridge line BL4a, the fifth bridge line BL5a, the sixth bridge line BL6a, the seventh bridge line BL7a, and the eighth bridge line BL8a.

[0288] Therefore, if the bending area BA of the display panel DP is bent and assembled, the direction of the first magnetic field generated in the first area AA1 in the charging driving mode and the direction of the second magnetic field generated in the second area AA2 and the circuit board MFPC can be the same. Therefore, the magnetic field in the third measurement area TA3 and the area adjacent thereto can not be canceled out. Therefore, the signal-to-noise ratio of the third measurement area TA3 can be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first and second measurement areas TA1 and TA2. Therefore, the sensing sensitivity of the pen PN of the electronic device 1000 (see FIG. 1A ) can be improved.

[0289] FIG. 22 is a view of a display panel and a circuit board MFPC according to one or more embodiments of the disclosure. In FIG. 22The same reference numbers are used throughout the various drawings to refer to the same or like parts. FIG. 20 and FIG. 21 described in

[0290] Referring to FIG. 7 , FIG. 19 and FIG. 22 , the display panel DP can include a first bridge line BL1a, a second bridge line BL2a, a third bridge line BL3b, a fourth bridge line BL4b, a fifth bridge line BL5b, a sixth bridge line BL6b, a seventh bridge line BL7a, and an eighth bridge line BL8a. The first bridge line BL1a, the second bridge line BL2a, the third bridge line BL3b, the fourth bridge line BL4b, the fifth bridge line BL5b, the sixth bridge line BL6b, the seventh bridge line BL7a, and the eighth bridge line BL8a can be arranged in the first area AA1.

[0291] In one or more embodiments of the disclosure, at least some of the first bridge line BL1a, the second bridge line BL2a, the third bridge line BL3b, the fourth bridge line BL4b, the fifth bridge line BL5b, the sixth bridge line BL6b, the seventh bridge line BL7a, and the eighth bridge line BL8a can overlap the sensing area 200A. For example, the third bridge line BL3b, the fourth bridge line BL4b, the fifth bridge line BL5b, and the sixth bridge line BL6b can be located in the sensing area 200A, and the first bridge line BL1a, the second bridge line BL2a, the seventh bridge line BL7a, and the eighth bridge line BL8a can be located in the peripheral area 200NA. However, this is only an example, and the arrangement relationship can be modified in various ways.

[0292] In one or more embodiments of the disclosure, some of the third electrodes 230 can be directly connected to the third bridge line BL3b, the fourth bridge line BL4b, the fifth bridge line BL5b, and the sixth bridge line BL6b. That is, the first-second loop trace 230rt12, the first-third loop trace 230rt13, the first-fourth loop trace 230rt14, and the first-fifth loop trace 230rt15 can be connected to the third electrodes 230 corresponding to the third bridge line BL3b, the fourth bridge line BL4b, the fifth bridge line BL5b, and the sixth bridge line BL6b.

[0293] According to one or more embodiments of the disclosure, if the bending area BA of the display panel DP is bent and assembled, the direction of the first magnetic field generated in the first area AA1 in the charging driving mode and the direction of the second magnetic field generated in the circuit board MFPC and the second area AA2 can be the same. Accordingly, the signal-to-noise ratio of the third measurement area TA3 can be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Accordingly, the sensing sensitivity of the pen PN of the electronic device 1000 (see FIG. 1A ) can be improved.

[0294] FIG. 23 is a view of a display panel and a circuit board MFPC according to one or more embodiments of the disclosure. In the description of FIG. 23 , the same reference numerals are given to components identical to those of FIG. 21 , and detailed descriptions thereof will be omitted.

[0295] Referring to FIG. 7 , FIG. 19 and FIG. 23 , the display panel DP can include a first bridge line BL1a, a second bridge line BL2a, a third bridge line BL3a, a fourth bridge line BL4a, a fifth bridge line BL5a, a sixth bridge line BL6a, a seventh bridge line BL7a, and an eighth bridge line BL8a. The first bridge line BL1a to the eighth bridge line BL8a can be located in the peripheral area 200NA. For example, the first bridge line BL1a to the eighth bridge line BL8a can be located in at least one of the first area AA1, the bending area BA, and the second area AA2. FIG. 23 An example in which the first bridge line BL1a to the eighth bridge line BL8a are uniformly located in the first area AA1, the bending area BA, and the second area AA2 is illustrated.

[0296] According to one or more embodiments of the disclosure, when the bending area BA of the display panel DP is bent and assembled, the direction of the first magnetic field generated in the first area AA1 (in particular, in the sensing area 200A in the charging driving mode) and the direction of the second magnetic field generated in the circuit board MFPC can be the same. Accordingly, the signal-to-noise ratio of the third measurement area TA3 can be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Accordingly, the sensing sensitivity of the pen PN of the electronic device 1000 (see FIG. 1A ) can be improved.

[0297] FIG. 24 is a view of a display panel and a circuit board MFPC according to one or more embodiments of the disclosure. In the description of FIG. 24 , the same reference numerals are given to components identical to those ofFIG. 20 and FIG. 21 The components described in

[0298] Referring to FIG. 7 , FIG. 19 and FIG. 24 , at least one of the display panel DP and the circuit board MFPC can include a first bridge line BL1b, a second bridge line BL2b, a third bridge line BL3a, a fourth bridge line BL4a, a fifth bridge line BL5a, a sixth bridge line BL6a, a seventh bridge line BL7b, and an eighth bridge line BL8b. For example, the first bridge line BL1b, the second bridge line BL2b, the seventh bridge line BL7b, and the eighth bridge line BL8b can be included in the circuit board MFPC, and the third bridge line BL3a, the fourth bridge line BL4a, the fifth bridge line BL5a, and the sixth bridge line BL6a can be included in the display panel DP. However, this is only an example, and the arrangement positions of the first bridge line BL1b, the second bridge line BL2b, the third bridge line BL3a, the fourth bridge line BL4a, the fifth bridge line BL5a, the sixth bridge line BL6a, the seventh bridge line BL7b, and the eighth bridge line BL8b can be modified in various ways.

[0299] In addition, as shown in FIG. 24 , the first-first to first-sixth loop traces 230rt11 to 230rt16 can be connected to the third electrode 230, respectively.

[0300] FIG. 25A is a view showing a result of simulation of a magnetic field on a surface of a display panel according to a comparative example of the present disclosure. FIG. 25B is a view showing a result of simulation of a magnetic field on a surface of a display panel according to an embodiment of the present disclosure.

[0301] Referring to FIG. 7 , FIG. 19 , FIG. 25A and FIG. 25B , in the simulation results of FIG. 25A and FIG. 25B , a magnetic field measured in the third measurement area TA3 is represented by contour lines.

[0302] FIG. 25A and FIG. 25B , the reference line RER represents a height at which the intensity of a reference magnetic field is measured if the display panel DP is not bent as shown in FIG. 7 . For example, the intensity of the reference magnetic field can be about 3 × 10 -7 T.

[0303] According to a comparative example of the present disclosure, the arrangement order of the first loop trace 230rt1 electrically connected to the third electrode 230 can be extended without change and electrically connected to the sensor driver 200C. Referring to FIG. 25A If the display panel DP is bent and assembled, the directions of the currents AA1em1 and AA1em2 in the first area AA1 and the directions of the currents AA2em1c and AA2em2c in the second area AA2 or the circuit board MFPC can be different from each other in the charging driving mode. Accordingly, the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the second area AA2 and the circuit board MFPC can be different from each other. Accordingly, the height SEM-c having the intensity of the reference magnetic field can be less than the reference line RER.

[0304] According to one or more embodiments of the present disclosure, as previously described with reference to FIG. 20 to FIG. 24 the arrangement order of the first loop trace 230rt1 electrically connected to the third electrode 230 can be changed to be electrically connected to the sensor driver 200C. Referring to FIG. 25B If the display panel DP is bent and assembled, the directions of the currents AA1em1 and AA1em2 in the first area AA1 and the directions of the currents AA2em1 and AA2em2 in the second area AA2 or the circuit board MFPC can be the same in the charging driving mode. Accordingly, the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the second area AA2 and the circuit board MFPC can be the same. Accordingly, the height SEM having the intensity of the reference magnetic field can be greater than the reference line RER.

[0305] FIG. 26 is a cross-sectional view of the electronic device 1000 taken along the line II-II' of FIG. 19 According to one or more embodiments of the present disclosure.

[0306] Referring to FIG. 7 , FIG. 19 and FIG. 26 If the bent area BA of the display panel DP is bent, the first area AA1 can overlap the second area AA2 and the circuit board MFPC. Accordingly, as previously described with reference to FIG. 20 to FIG. 24 the arrangement order of the first loop trace 230rt1 electrically connected to the third electrode 230 can be changed to be electrically connected to the sensor driver 200C.

[0307] In the charging driving mode, the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the second area AA2 and the circuit board MFPC can be the same. Accordingly, the magnetic field in the third measurement area TA3 and an area adjacent thereto can not be canceled out. Accordingly, it is possible to increase the signal-to-noise ratio of the third measurement area TA3 to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Accordingly, it is possible to improve the sensing sensitivity of the pen PN of the electronic device 1000 (see FIG. 1A ).

[0308] According to one or more embodiments of the present disclosure, the electronic device 1000 can further include a first magnetic field shielding layer MSL1 positioned under the first area AA1 of the display panel DP and a lower plate (e.g., a metal lower plate) LST positioned under the first magnetic field shielding layer MSL1. The second area AA2 and the circuit board MFPC can be positioned under the lower plate LST.

[0309] The first magnetic field shielding layer MSL1 can include a magnetic metal powder. The first magnetic field shielding layer MSL1 can be referred to as a ferrite sheet, a magnetic metal powder layer, a magnetic layer, a magnetic path layer, or a magnetic route layer. The first magnetic field shielding layer MSL1 can shield a magnetic field from the first area AA1 of the display panel DP to the second area AA2 of the display panel DP. For example, the first magnetic field shielding layer MSL1 can serve to direct the direction of the transmitted magnetic field in another direction. Accordingly, the magnetic field reaching the first magnetic field shielding layer MSL1 can be shielded without leaking to the outside, for example, to the lower portion of the first magnetic field shielding layer MSL1.

[0310] The lower plate LST can be a plate for reflecting a magnetic field toward the first magnetic field shielding layer MSL1. The lower plate LST can include a metal or a metal alloy. For example, the lower plate LST can include aluminum, copper, or a copper alloy.

[0311] FIG. 27 is a cross-sectional view of the electronic device 1000a taken along line II-II' of FIG. 19 In the description of FIG. 27 , the same reference numerals can be given to components identical to those of FIG. 26 , and detailed descriptions thereof will be omitted.

[0312] Referring to FIG. 7 and FIG. 27The electronic device 1000a can further include a first magnetic field shielding layer MSL1 positioned under the first area AA1 of the display panel DP, a lower plate LST positioned under the first magnetic field shielding layer MSL1, and a second magnetic field shielding layer MSL2 positioned under the lower plate LST. The second area AA2 and the circuit board MFPC can be positioned under the second magnetic field shielding layer MSL2.

[0313] The second magnetic field shielding layer MSL2 can also include substantially the same material as the first magnetic field shielding layer MSL1. Accordingly, according to one or more embodiments of the disclosure, two or more magnetic field shielding layers MSL1 and MSL2 can be positioned between the first area AA1 of the display panel DP and the second area AA2 of the display panel DP and between the first area AA1 of the display panel DP and the circuit board MFPC. Accordingly, the possibility that the magnetic field generated in the first area AA1 and the magnetic field generated in the second area AA2 and the circuit board MFPC affect each other can be reduced.

[0314] According to one or more embodiments of the disclosure, the area (e.g., surface area) of the first magnetic field shielding layer MSL1 can be greater than the area (e.g., surface area) of the second magnetic field shielding layer MSL2. For example, the first magnetic field shielding layer MSL1 can completely overlap the first area AA1 of the display panel DP, and the second magnetic field shielding layer MSL2 can overlap the second area AA2 of the display panel DP and the circuit board MFPC.

[0315] The first area AA1 can include a first partial area AAp1, a second partial area AAp2, and a third partial area AAp3. The first partial area AAp1 can be an area that does not overlap the second area AA2 of the display panel DP and the circuit board MFPC.

[0316] The magnetic field generated in the first partial area AAp1 can not be canceled out, or can be only slightly canceled out, by the magnetic field generated in the second area AA2 and the circuit board MFPC.

[0317] The second partial area AAp2 can be an area that overlaps the circuit board MFPC. The third partial area AAp3 can be an area that overlaps the second area AA2 of the display panel DP. That is, the magnetic field generated in the second partial area AAp2 and the third partial area AAp3 can be canceled out by the magnetic field generated in the second area AA2 and the circuit board MFPC. Accordingly, in one or more embodiments, two or more magnetic field shielding layers MSL1 and MSL2 can be positioned between the second partial area AAp2 and the third partial area AAp3 and the circuit board MFPC to reduce or minimize the cancellation of the magnetic field. Accordingly, the possibility that the magnetic field generated in the first area AA1 and the magnetic field generated in the second area AA2 and the circuit board MFPC affect each other can be reduced.

[0318] In the case of one or more embodiments corresponding to FIG. 27 , it can be combined with each of the embodiments described above with reference to FIG. 20 to FIG. 24 In addition, one or more embodiments corresponding to FIG. 27 may be combined with a structure in which the arrangement order of the first loop trace 230rt1 electrically connected to the third electrode 230 is extended without change and is electrically connected to the sensor driver 200C.

[0319] FIG. 28 is a cross-sectional view of the electronic device 1000b taken along line II-II' of FIG. 19 In the description of FIG. 28 , the same reference numerals can be given to components identical to those of FIG. 27 , and detailed descriptions thereof will be omitted.

[0320] Referring to FIG. 7 and FIG. 28 , the electronic device 1000b can further include a first magnetic field shielding layer MSL1 positioned under the first area AA1 of the display panel DP, a lower plate LST positioned under the first magnetic field shielding layer MSL1, and a second magnetic field shielding layer MSL2a positioned under the lower plate LST. The second area AA2 and the circuit board MFPC can be positioned under the second magnetic field shielding layer MSL2a.

[0321] According to one or more embodiments of the disclosure, the area of the first magnetic field shielding layer MSL1 can be substantially the same as the area of the second magnetic field shielding layer MSL2a. For example, each of the first magnetic field shielding layer MSL1 and the second magnetic field shielding layer MSL2a can completely overlap the first area AA1 of the display panel DP.

[0322] In the case of one or more embodiments corresponding to FIG. 28 , it can be combined with each of the embodiments described above with reference to FIG. 20 to FIG. 24 In addition, one or more embodiments corresponding to FIG. 28 may be combined with a structure in which the arrangement order of the first loop trace 230rt1 electrically connected to the third electrode 230 is extended without change and is electrically connected to the sensor driver 200C.

[0323] FIG. 29 is a cross-sectional view of the circuit board MFPC according to one or more embodiments of the disclosure. For example, FIG. 29 is an enlarged plan view of the area CC' shown in FIG. 28 .

[0324] Referring toFIG. 28 and FIG. 29 The circuit board MFPC can include a plurality of conductive layers ML1, ML2, and ML3, and the plurality of connection lines 230c can be included in the conductive layer ML3, which is the layer farthest from the first area AA1 of the display panel DP among the plurality of conductive layers ML1, ML2, and ML3. The plurality of conductive layers ML1 and ML2 can be referred to as conductive shielding layers.

[0325] FIG. 29 An example in which the circuit board MFPC includes three conductive layers ML1, ML2, and ML3 is illustrated, but the present disclosure is not particularly limited thereto. For example, the circuit board MFPC can include two conductive layers, or can include four or more conductive layers.

[0326] FIG. 30A is a cross-sectional view of a circuit board MFPCa according to one or more embodiments of the present disclosure. FIG. 30B is a plan view of a circuit board MFPCa according to one or more embodiments of the present disclosure. FIG. 30A is FIG. 28 is an enlarged plan view of the area CC' of

[0327] Referring to FIG. 28 , FIG. 30A and FIG. 30B The circuit board MFPCa can include a plurality of conductive layers ML1a, ML2, and ML3, and the plurality of connection lines 230c can be included in the conductive layer ML3, which is the layer farthest from the first area AA1 of the display panel DP among the plurality of conductive layers ML1a, ML2, and ML3.

[0328] In one or more embodiments of the present disclosure, a shielding layer ML1a can be disposed between the connection lines 230c and the first area AA1 of the display panel DP. That is, at least one conductive layer among the plurality of conductive layers ML1a, ML2, and ML3 can function as the shielding layer ML1a, which can be referred to as the shielding layer ML1a. The shielding layer ML1a can overlap all of the connection lines 230c when viewed on a plane, for example, when viewed in the third direction DR3.

[0329] In one or more embodiments of the present disclosure, the shielding layer ML1a can be grounded or can be provided at a constant voltage (for example, a predetermined constant voltage). In this case, the possibility that the magnetic field generated in the first area AA1 and the magnetic field generated in the second area AA2 and the circuit board MFPCa affect each other can be reduced by the shielding layer ML1a.

[0330] One or more embodiments corresponding to FIG. 30A and FIG. 30B may be applied to the above-described embodiments with reference to FIG. 20 to FIG. 24each of the embodiments described above in combination. Furthermore, one or more embodiments corresponding to FIG. 30A and FIG. 30B may be combined with the structure in which the arrangement order of the first ring trace 230rt1 electrically connected to the third electrode 230 is extended without change and is electrically connected to the sensor driver 200C. Furthermore, one or more embodiments corresponding to FIG. 30A and FIG. 30B may be combined with each of the embodiments described above in reference to FIG. 26 to FIG. 28 . Furthermore, one or more embodiments corresponding to FIG. 30A and FIG. 30B may be combined with each of the embodiments described above in reference to FIG. 20 to FIG. 24 and the embodiments described above in reference to FIG. 26 to FIG. 28 .

[0331] FIG. 31 is a cross-sectional view of a circuit board MFPCb according to one or more embodiments of the present disclosure. For example, FIG. 31 is an enlarged plan view of a region CC' of FIG. 28 .

[0332] In reference to FIG. 28 and FIG. 31 , the circuit board MFPCb can include a plurality of layers ML1b, ML2b, ML3b, ML4b, ML5b, and ML6b and an insulating layer IL positioned between the plurality of layers ML1b, ML2b, ML3b, ML4b, ML5b, and ML6b. The plurality of layers ML1b, ML2b, ML3b, ML4b, ML5b, and ML6b can include a first shield layer ML1b, a first line layer ML2b, a second shield layer ML3b, a third shield layer ML4b, a second line layer ML5b, and a fourth shield layer ML6b.

[0333] The first shield layer ML1b can be a layer closest to the display panel DP (see FIG. 7 ). Accordingly, it can be understood that the first shield layer ML1b, the first line layer ML2b, the second shield layer ML3b, the third shield layer ML4b, the second line layer ML5b, and the fourth shield layer ML6b are sequentially laminated in a direction away from the display panel DP.

[0334] FIG. 32A is a plan view of a first shield layer (e.g., a first conductive shield layer) ML1b according to one or more embodiments of the present disclosure.

[0335] In reference to FIG. 31 and FIG. 32AThe first shielding layer ML1b can not cover a pad region PD-MA in which a pad PD-M of the circuit board MFPCb is positioned.

[0336] FIG. 32B is a plan view of the first wire layer ML2b according to one or more embodiments of the disclosure.

[0337] Referring to FIG. 31 and FIG. 32B , the circuit board MFPCb can include a plurality of connection lines 230ca. FIG. 32B Some of the connection lines 230ca included in the first wire layer (e.g., first conductive layer) ML2b are illustrated.

[0338] The connection lines 230ca can include a plurality of first connection lines 230ca1 and a plurality of second connection lines 230ca2. The first connection lines 230ca1 and the second connection lines 230ca2 can be spaced apart from each other in the first direction DR1.

[0339] The sensor driver 200C can be mounted adjacent to any one of the first connection lines 230ca1 and the second connection lines 230ca2. In this case, any one of the first connection lines 230ca1 and the second connection lines 230ca2 can be connected to the sensor driver 200C via an extension connection line 230ca2-CL (see FIG. 32E ) extending along a width direction of the circuit board MFPCb (e.g., along the first direction DR1).

[0340] According to one or more embodiments of the disclosure, the first wire layer ML2b can correspond to a layer positioned closer to the display panel DP (see FIG. 7 ) than a second wire layer ML5b to be described later. Accordingly, a portion extending along a width direction of the circuit board MFPCb (e.g., along the first direction DR1) can not be included in the first wire layer ML2b.

[0341] The first shielding layer ML1b is disposed between the connection lines 230ca and the first electrode portion. The first electrode portion can include at least one of a first portion of the first loop trace 230rt1 (see FIG. 7 ), a first portion of the second line portion 232t (see FIG. 7 ), and a first portion of the third line portion 233t (see FIG. 7 ), and each of the third electrodes 230 (see FIG. 7 ) is disposed in the first area AA1 (see FIG. 7 ).

[0342] FIG. 32Cis a plan view of a second shielding layer ML3b according to one or more embodiments of the disclosure. FIG. 32D is a plan view of a third shielding layer ML4b according to one or more embodiments of the disclosure.

[0343] Referring to FIG. 32A , FIG. 32B , FIG. 32C and FIG. 32D , each of the second shielding layer (e.g., second conductive shielding layer) ML3b and the third shielding layer (e.g., third conductive shielding layer) ML4b or the first shielding layer ML1b can be grounded or provided with a constant voltage (e.g., a predetermined constant voltage). However, the disclosure is not limited thereto, and the second shielding layer ML3b and the third shielding layer ML4b can also be floated.

[0344] Each of the second shielding layer ML3b and the third shielding layer ML4b can include a conductive material. Accordingly, the second shielding layer ML3b and the third shielding layer ML4b can also include a wire through which a signal (e.g., a predetermined signal) is transmitted.

[0345] FIG. 32E is a plan view of a second wire layer ML5b according to one or more embodiments of the disclosure. FIG. 32F is a plan view of a fourth shielding layer ML6b according to one or more embodiments of the disclosure.

[0346] Referring to FIG. 32B , FIG. 32E and FIG. 32F , the second wire layer (e.g., second conductive layer) ML5b can include an extension connection line 230ca2-CL. The extension connection line 230ca2-CL can be connected to the second connection line 230ca2 to extend along the width direction of the circuit board MFPCb.

[0347] The second shielding layer ML3b (see FIG. 32C ) and the third shielding layer ML4b (see FIG. 32D ) are disposed between the connection line 230ca and the extension connection line 230ca2-CL.

[0348] Referring to FIG. 32F , a mounting area 200C-A on which the sensor driver 200C is mounted is shown. Accordingly, the extension connection line 230ca2-CL can be provided to allow the second connection line 230ca2 relatively distant from the sensor driver 200C to extend to the mounting area 200C-A overlapping the sensor driver 200C.

[0349] The length of the extension connection line 230ca2-CL can be longer than the length of the second connection line 230ca2. Accordingly, the extension connection line 230ca2-CL can be designed to be included in the second wire layer ML5b relatively far from the display panel DP (see FIG. 7 ) in the first area AA1.

[0350] The fourth shield layer ML6b can cover the second wire layer ML5b. The sensor driver 200C can be mounted on a mounting area 200C-A shown on the fourth shield layer ML6b.

[0351] Referring to FIG. 7 , FIG. 31 and FIGS. 32A-32F , the circuit board MFPCb can be designed to reduce or minimize cancellation of the magnetic field generated in the first area AA1 of the display panel DP by the connection line 230ca. For example, the circuit board MFPCb can include at least two wire layers including the connection line 230ca, and a portion having a relatively long length can be located on a layer farthest from the display panel DP. Furthermore, the circuit board MFPCb can be provided with a plurality of shield layers, such as the second shield layer ML3b and the third shield layer ML4b, not only between the fourth shield layer ML6b and the first shield layer ML1b disposed at the outermost portion but also between the first wire layer ML2b and the second wire layer ML5b, and thus can further reduce the possibility that the magnetic field generated in the first area AA1 and the magnetic field generated in the circuit board MFPCb affect each other.

[0352] As described above, the sensor layer can be used to sense a pen input as well as a touch input. Accordingly, since a separate component (e.g., a digitizer) for pen sensing need not be added to the electronic device, an increase in the thickness and weight of the electronic device and a reduction in the flexibility of the electronic device due to the addition of the digitizer can not occur. Furthermore, a structure in which the first magnetic field generated in the first area of the display panel and the second magnetic field generated in the second area or the circuit board are not canceled can be provided. In this case, the signal-to-noise ratio of the second area of the display panel and one area of the electronic device overlapping the circuit board can be improved to be similar to or slightly greater than the signal-to-noise ratio of the first area of the display panel and the other area of the electronic device not overlapping the circuit board. Accordingly, the pen sensing sensitivity of the electronic device can be improved.

[0353] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of the disclosed implementations provided they come within the scope of the appended claims and their equivalents. Accordingly, the technical scope of the present disclosure should not be limited to what is described in the foregoing detailed description, but should be determined by the appended claims.

Claims

1. An electronic device, characterized in that, include: The display panel includes: First area; The display panel is bent at the curved area; The second region overlaps with the first region; A first electrode is arranged in the first region in a first direction; A second electrode is arranged in the first region in a second direction intersecting the first direction and intersecting the first electrode; and A third electrode is located in the first region and overlaps with the first electrode; A circuit board, connected to the display panel at the second region, and including connecting lines arranged in the first direction and electrically connected to the third electrode respectively; A metal lower plate is located between the display panel and the circuit board; and A first magnetic field shielding layer is located between the third electrode of the display panel and the lower metal plate.

2. The electronic device according to claim 1, characterized in that, The connecting wire is electrically connected to the third electrode at the first region, the curved region, or the second region, respectively.

3. The electronic device according to claim 1, characterized in that, The display panel further includes a display layer and a sensor layer, the sensor layer comprising: A first annular trace is electrically connected to the first end of the third electrode and arranged in the first direction; and The second annular trace is electrically connected to the second end of the third electrode.

4. The electronic device according to claim 3, characterized in that, The first annular trace is spaced apart from the connecting lines that are electrically connected to the first annular trace in the first direction.

5. The electronic device according to claim 3, characterized in that, The second circular trace includes: The first wire portion is electrically connected to the third electrode; The second line portion extends from the first end of the first line portion in the second direction; and The third line portion extends from the second end of the first line portion in the second direction. The second line portion, the first annular trace, and the third line portion are arranged sequentially in the first direction.

6. The electronic device according to claim 3, characterized in that, At least one of the display panel and the circuit board further includes a bridging wire that electrically connects the connecting line and the third electrode, respectively.

7. The electronic device according to claim 6, characterized in that, The bridging wire extends in the first direction.

8. The electronic device according to claim 6, characterized in that, The bridging wire is in the first region.

9. The electronic device according to claim 6, characterized in that, The first region includes a sensing region for sensing external input and a peripheral region adjacent to the sensing region, and At least some of the bridging wires are located in the peripheral area.

10. The electronic device according to claim 6, characterized in that, The bridging line is separate from the curved area.

11. The electronic device according to claim 6, characterized in that, Some of the bridging wires are in the first region, and other bridging wires are in the circuit board.

12. An electronic device, characterized in that, include: The display panel includes: First area; The display panel is bent at the curved area; The second region overlaps with the first region; The first electrode portion is arranged in the first region in a first direction; The second electrode portion is arranged in the first direction in the curved region and is electrically connected to the first electrode portion; and The third electrode portion is arranged in the second region in the first direction and is electrically connected to the second electrode portion; A circuit board, connected to the display panel at the second region, and including connecting lines arranged in the first direction and electrically connected to the third electrode portion; A lower metal plate, located between the first electrode portion and the connecting wire; and A first magnetic field shielding layer is located between the first electrode portion and the lower metal plate.

13. The electronic device according to claim 12, characterized in that, The connecting line has an arrangement order in the first direction that is different from the arrangement order of the third electrode portions respectively connected to the connecting line in the first direction.

14. The electronic device according to claim 13, characterized in that, The arrangement order of the third electrode portion is the reverse of the arrangement order of the connecting lines.

15. An electronic device, characterized in that, include: The display panel includes: First area; The display panel is bent at the curved area; The second region overlaps with the first region; The first electrode portion is arranged in the first region in a first direction; The second electrode portion is arranged in the first direction in the curved region and is electrically connected to the first electrode portion; and The third electrode portion is arranged in the second region in the first direction and is electrically connected to the second electrode portion; A circuit board, connected to the display panel at the second region, and comprising: The connecting wire is electrically connected to the third electrode portion; Extend the connecting line and connect it to the connecting line; A first conductive shielding layer is located between the first electrode portion and the connecting line; and A second conductive shielding layer is provided between the connecting line and the extended connecting line; A metal lower plate is located between the display panel and the circuit board; and A magnetic field shielding layer is located between the display panel and the lower metal plate.

16. The electronic device according to claim 15, characterized in that, The first conductive shielding layer or the second conductive shielding layer is grounded.

17. The electronic device according to claim 15, characterized in that, The first conductive shielding layer or the second conductive shielding layer is configured to receive a constant voltage.

18. The electronic device according to claim 15, characterized in that, The circuit board is located below the display panel in the first region, and further includes a first conductive layer having the connecting lines and a second conductive layer having the extended connecting lines, and The first conductive layer is located between the second conductive layer and the first area of ​​the display panel.

19. The electronic device according to claim 18, characterized in that, The first conductive layer is below the first conductive shielding layer and partially overlaps with the second region of the display panel.

20. The electronic device according to claim 18, characterized in that, The second conductive layer is below the second conductive shielding layer and partially overlaps with the second area of ​​the display panel.

21. An electronic device, characterized in that, include: A substrate includes a first region, a curved region, and a second region overlapping the first region, wherein the substrate is curved at the curved region; A circuit layer, above the substrate, includes transistors; A light-emitting element layer is located above the circuit layer and includes light-emitting elements electrically connected to the transistor. A sensor layer, above the light-emitting element layer, and including electrodes arranged in a first direction in the first region; A sensor driver configured to use the electrodes to generate a magnetic field for charging a pen that includes an RLC resonant circuit; A circuit board, coupled to the substrate at the second region, and including connection lines electrically connected to the electrodes; A lower metal plate is located between the electrode and the connecting line; as well as A first magnetic field shielding layer is located between the electrode and the lower metal plate.

22. The electronic device according to claim 21, characterized in that, The sensor driver is configured to operate selectively in a first mode or a second mode, in which the sensor layer is driven to sense touch input, and in the second mode, the sensor driver is driven to sense pen input, the second mode including a charging drive mode.

23. The electronic device according to claim 22, characterized in that, The sensor layer is configured to sense the pen input by applying a first signal to at least one of the electrodes and by applying a second signal to at least another of the electrodes.

24. The electronic device according to claim 21, characterized in that, The sensor layer further includes a first mesh line, a second mesh line, and an intermediate insulating layer between the first mesh line and the second mesh line. The first mesh line has a first width, and the second mesh line is above the first mesh line and has a second width equal to or greater than the first width.

25. The electronic device according to claim 21, characterized in that, The connecting line has an arrangement order in the first direction that is different from the arrangement order of the electrodes respectively connected to the connecting line in the first direction.

26. The electronic device according to claim 21, characterized in that, It also includes bridging lines in the first region of the substrate and / or in the circuit board, the bridging lines electrically connecting the electrodes to the connecting lines, respectively.

27. The electronic device according to claim 26, characterized in that, The bridging line is within a limited distance from the curved edge defined in the curved region.

28. The electronic device according to claim 21, characterized in that, It also includes a display driver in the second region and configured to control the circuit layer. The circuit board overlaps with the first region.

29. The electronic device according to claim 21, characterized in that, It also includes a second magnetic field shielding layer between the connecting line and the lower metal plate, and the second magnetic field shielding layer overlaps with the second region of the circuit board and the substrate.

30. The electronic device according to claim 21, characterized in that, It also includes a second magnetic field shielding layer between the connecting line and the lower metal plate, and the surface area of ​​the first magnetic field shielding layer is equal to or greater than the surface area of ​​the second magnetic field shielding layer.

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