Double-chip cascaded data communication system

Abstract

The utility model discloses a double-chip cascaded data communication system, which comprises an acquisition unit, a data isolation module, a main control module, an isolation switch module, a power supply module and an external communication module, and is characterized in that the acquisition unit comprises a first acquisition device U1 and a second acquisition device U2, the second acquisition device U2 and the first acquisition device U1 are directly connected with the main control module, and the main control module is connected with the isolation switch module; the second collector U2 is connected with the data isolation module, the data isolation module is connected with the main control module through the isolation switch module, and the main control module is connected with the power supply module and the external communication module; an independent grounding end B11-is set for the second collector U2 so that reference grounds of two collection chips can be kept consistent, meanwhile, data transmission between the first collector U1 and the second collector U2 and the main controller U3 is achieved through the isolation switch module, a high-voltage data signal of the second collector U2 is converted into a low-voltage data signal, and the low-voltage data signal is transmitted to the main controller U3 through the isolation switch module. And the stability of data transmission is ensured.

Description

TECHNICAL FIELD

[0001] The utility model relates to communication circuit technical field, concretely relates to a kind of data communication system of double-chip cascade. BACKGROUND

[0002] In the lithium battery BMS (battery management system) design, when two acquisition units cascade, the reference ground of system is different, which can cause the reference level of signal level to be inconsistent. The communication between the main control MCU and the acquisition unit is usually based on a certain level standard, such as SPI (serial peripheral interface) or I2C (inter-integrated circuit bus) communication protocol.

[0003] Taking I2C communication as an example, the communication line includes SDA (data line) and SCL (clock line). If the reference ground of the two acquisition units is different, the level of SDA and SCL will be different during signal transmission. Similarly, for SPI communication, it includes MOSI (master out slave in), MISO (master in slave out) and clock signal lines. Different reference grounds can cause errors in the transmission of these signals, resulting in communication failures such as data transmission errors, communication interruptions, etc. SUMMARY

[0004] In view of the deficiencies in the prior art, the purpose of the utility model is to provide a data communication system of double-chip cascade.

[0005] In order to achieve the above purpose, the utility model provides the following technical scheme:

[0006] A data communication system of double-chip cascade includes an acquisition unit, a data isolation module, a main control module, an isolation switch module, a power module and an external communication module. The acquisition unit includes a first collector U1 and a second collector U2. The second collector U2 is directly connected to the main control module with the first collector U1. The second collector U2 is connected to the data isolation module. The data isolation module is connected to the main control module through the isolation switch module. The main control module is connected to the power module and the external communication module.

[0007] In the utility model, preferably, the data isolation module includes a plurality of groups of isolation balancing circuits, and the isolation balancing circuits have the same structure. One of the isolation balancing circuits includes a transistor Q25. The emitter of the transistor Q25 is connected to a battery B11. The collector of the transistor Q25 is connected to B11- through a resistor R89. The base of the transistor Q25 is connected to V11 through a resistor R109. V11 is connected to the second collector U2.

[0008] In the utility model, preferably, the first collector U1 adopts BQ7693001 series chip, and the input end is connected with B0-B10 end of battery pack respectively, and the No. 9 pin of first collector U1 is connected with the No. 2 end of MOS tube N20, and the No. 3 end of MOS tube N20 is connected with resistance R162 and diode D18 in series and then connects B10 end of battery, and the both ends of diode D18 are also connected with resistance R155 in parallel, and the No. 1 end of MOS tube N20 connects the No. 10 pin of first collector U1, and the No. 10 pin of first collector U1 is also connected with capacitor C45 in series and then connects ground terminal.

[0009] In the utility model, preferably, the second collector U2 adopts BQ7693003 series chip, and the input end is connected with B11-B20 end of battery pack respectively, and the input end is connected with the output end of isolation balance circuit simultaneously, and the No. 9 pin of second collector U2 is connected with the No. 2 end of MOS tube N19, and the No. 3 end of MOS tube N19 is connected with resistance R67 and diode D32 in series and then connects B20 end of battery, and the both ends of diode D32 are also connected with resistance R171 in parallel, and the No. 1 end of MOS tube N19 connects the No. 10 pin of second collector U2, and the No. 1 end of MOS tube N19 is also connected with resistance R165 in series and then connects B20 end of battery.

[0010] In the utility model, preferably, the main control module includes main controller U3, and the No. 27-No. 30 pin of main controller U3 is connected with first collector U1 and second collector U2 respectively, and data interaction is carried out.

[0011] In the utility model, preferably, the isolating switch module includes switch circuit and isolation circuit, the switch circuit includes transistor Q1 and MOS tube Q7, the emitter of transistor Q1 connects VCC-5V power terminal, the collector connects VCC5_1 terminal, the base is connected with resistance R141 in series and then connects the drain of MOS tube Q7, the source of MOS tube Q7 connects ground, and the gate is connected with resistance R145 in series and then connects the main controller U3.

[0012] In the utility model, preferably, the isolation circuit is connected between the power module and the second collector U2, and the isolation circuit includes isolator U15, transformer B1 and transformer B2, the input end of isolator U15 is connected with VCC5_1 terminal, and the output is connected with transformer B1 and transformer B2, the output of transformer B1 is connected with 5V_IIC power terminal and B11-end, and B11-end is connected with the second collector U2, and the output of transformer B2 is connected with 5V power terminal and GAN_G terminal.

[0013] In the utility model, preferably, the power module includes voltage conversion circuit and isolation power supply circuit, the voltage conversion circuit includes voltage stabilizer U13, converter U14 and converter U11, voltage stabilizer U13 connects BAT_POW power supply end, and the output is connected with resistance R68 and inductance L1 output 12V power supply, then connects converter U14, and converter U14 converts 12V power supply into 5V output, and 12V power supply input converter U11, and converter U11 is converted into 3.3V output.

[0014] In the utility model, preferably, the isolation power supply circuit includes transistor Q4, transistor Q5 and transistor Q11, the emitter of transistor Q4 is connected with resistance R140 and diode D29, and then is connected with battery B200 end, and the collector is connected with BAT_POW power supply end, and the base is connected with the emitter of transistor Q5, and the collector of transistor Q5 is also the BAT_POW power supply end, and the base of transistor Q5 is connected with resistance R147, and then is connected with the drain of transistor Q11, and the gate of transistor Q11 is connected with resistance R149, and then is connected with the first collector U1, and the source of transistor Q11 is grounded, and the emitter of transistor Q4 and the base of transistor Q5 are connected with resistance R142, and one end of resistance R140 is also connected with bidirectional transient voltage suppression diode D48, and then is grounded.

[0015] In the utility model, preferably, the external communication module includes isolator U4 and communicator U6, and the isolator U4 is connected between the communicator U6 and the main controller U3.

[0016] Compared with the prior art, the utility model has the advantages that:

[0017] The system of the utility model adopts unified power supply to avoid the inconsistency of battery caused by the power consumption difference of separate power supply, and the independent ground end B11- of the second collector U2 is set to keep the reference ground of the two collection chips consistent, and the isolation switch module is realized, the first collector U1 and the second collector U2 perform data transmission with the main controller U3 in the order, and the high-voltage data signal of the second collector U2 is converted into low-voltage data signal, and the stability of data transmission is ensured. ACCURACY OF DRAWINGS

[0018] Figure 1 It is a structure block diagram of the data communication system of the dual-chip cascade of the utility model.

[0019] Figure 2 It is a circuit diagram of the data isolation module of the utility model.

[0020] Figure 3 It is a circuit diagram of the first collector U1 of the utility model.

[0021] Figure 4 The circuit diagram of the second collector U2.

[0022] Figure 5 The circuit diagram of the main control module.

[0023] Figure 6 The circuit diagram of the isolating switch module.

[0024] Figure 7 The circuit diagram of the isolating power supply.

[0025] Figure 8 The circuit diagram of the voltage conversion.

[0026] Figure 9 The circuit diagram of the external communication module. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0028] It should be noted that when a component is referred to as being "fixed" to another component, it can be directly on the other component or there can be intervening components. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or there can be intervening components. When a component is referred to as being "disposed" on another component, it can be directly on the other component or there can be intervening components. The terms "vertical", "horizontal", "left", "right", and similar terms as used herein are for purposes of illustration only.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this description, the terms "therefore" and "because" are merely used to introduce an explanation of associated elements. They are not used to cause a departure from the scope of the application.

[0030] Please refer to Figure 1The utility model provides a kind of data communication system of double-chip cascade, including acquisition unit, data isolation module, main control module, isolating switch module, power module and external communication module, the acquisition unit includes first collector U1 and second collector U2, first collector U1 connects battery pack 1, for the data of battery pack 1 is collected, second collector U2 connects battery pack 2, for the data of battery pack 2 is collected, the second collector U2 and the first collector U1 are directly connected with the main control module, the second collector U2 connects the data isolation module, the data isolation module is connected between the main control module by the isolating switch module, the main control module is connected with the power module, external communication module.When working, first by power module power supply, main control module controls the opening and closing of isolating switch module to give the data isolation module power supply.Main control module first passes through first collector U1 and collects the data of battery pack 1, the data of battery pack 1 is collected, and then main control module controls second collector U2 to work by isolating switch module, and the data of battery pack 2 is collected, and the collected data is packed and exported by external communication module after collection is completed.

[0031] Please see Figure 2 In the embodiment, the data isolation module includes several groups of isolation balance circuits, the isolation balance circuits are the same structure, one of the isolation balance circuits includes transistor Q25, the emitter of the transistor Q25 is connected to the battery B11 end, the collector is connected to B11- end through resistance R89, the base is connected to V11 end through resistance R109, and V11 end is connected to the second collector U2. Each isolation balance circuit corresponds to one battery in battery pack 2, and is used to convert high voltage into low voltage signal input into the second collector U2. B11- end is generated by isolation circuit, which is controlled by main controller U3.

[0032] Please see Figure 3 In the embodiment, the first collector U1 adopts BQ7693001 series chip, the input end is connected to B0-B10 end of battery pack respectively, the No.9 pin of the first collector U1 is connected to the No.2 end of MOS tube N20, the No.3 end of the MOS tube N20 is connected to B10 end of battery through resistance R162 and diode D18 in series, the diode D18 is also connected to resistance R155 in parallel, the No.1 end of the MOS tube N20 is connected to the No.10 pin of the first collector U1, and the No.10 pin of the first collector U1 is also connected to ground end through capacitor C45 in series.

[0033] Please see Figure 4In the embodiment, the second collector U2 adopts BQ7693003 series chip, the input end is connected with B11-B20 end of the battery pack respectively, and the input end is connected with the output end of the isolation balance circuit, the No. 9 pin of the second collector U2 is connected with the No. 2 end of the MOS tube N19, the No. 3 end of the MOS tube N19 is connected with the B20 end of the battery after being connected with the resistance R67 and the diode D32 in series, the resistance R171 is also connected in parallel between the diode D32, the No. 1 end of the MOS tube N19 is connected with the No. 10 pin of the second collector U2, and the No. 1 end of the MOS tube N19 is also connected with the B20 end of the battery after being connected with the resistance R165 in series, the ground end connected with the second collector U2 is the ground end B11-. The second collector U2 adopts the ground end B11- set for the system, avoids the case that the reference ground of the two collection chips is different, and ensures the communication process of the collection data.

[0034] Please refer to Figure 5 In the embodiment, the main control module includes the main controller U3, the main controller U3 adopts STM32F072CBT6 series chip, and the No. 27-30 pin of the main controller U3 is connected with the first collector U1 and the second collector U2 respectively to interact data.

[0035] Please refer to Figure 6 In the embodiment, the isolating switch module includes the switch circuit and the isolation circuit, the switch circuit includes the transistor Q1 and the MOS tube Q7, the emitter of the transistor Q1 is connected with the VCC-5V power supply end, the collector is connected with the VCC5_1 end, the base is connected with the drain of the MOS tube Q7 after being connected with the resistance R141 in series, the source of the MOS tube Q7 is grounded, and the gate is connected with the main controller U3 after being connected with the resistance R145 in series.

[0036] In the embodiment, the isolation circuit is connected between the power module and the second collector U2, and is controlled by the main controller U3 through the switch circuit, the isolation circuit includes the isolator U15, the transformer B1 and the transformer B2, the input end of the isolator U15 is connected with the VCC5_1 end, the output is connected with the transformer B1 and the transformer B2, the output of the transformer B1 is connected with the 5V_IIC power supply end and the B11- end, the B11- end is connected with the second collector U2, and the output of the transformer B2 is connected with the 5V power supply end and the GAN_G end.

[0037] Please refer to Figure 7 and Figure 8In the embodiment, the power module includes a voltage conversion circuit and an isolation power supply circuit, the voltage conversion circuit includes a voltage regulator U13, a converter U14 and a converter U11, the voltage regulator U13 is connected to the BAT_POW power supply end, outputs a 12V power supply through a series connection of a resistor R68 and an inductor L1, and then is connected to the converter U14, the converter U14 converts the 12V power supply into a 5V output, the 12V power supply is input into the converter U11, and the converter U11 is converted into a 3.3V output.

[0038] In the embodiment, the isolation power supply circuit includes a transistor Q4, a transistor Q5 and a transistor Q11, the emitter of the transistor Q4 is connected to the battery B200 end through a series connection of a resistor R140 and a diode D29, the collector is connected to the BAT_POW power supply end, and the base is connected to the emitter of the transistor Q5; the collector of the transistor Q5 is also connected to the BAT_POW power supply end, the base of the transistor Q5 is connected to the drain of the transistor Q11 through a series connection of a resistor R147, the gate of the transistor Q11 is connected to the first collector U1 through a series connection of a resistor R149, the source of the transistor Q11 is grounded, and the emitter of the transistor Q4 is connected to the base of the transistor Q5 through a resistor R142, and one end of the resistor R140 is connected to the ground end through a series connection of a bidirectional transient voltage suppression diode D48.

[0039] Please refer to Figure 9 In the embodiment, the external communication module includes an isolator U4 and a communicator U6, and the isolator U4 is connected between the communicator U6 and the main controller U3.

[0040] Working principle:

[0041] After the system is powered on, the first collector U1 is powered by the battery pack 1 to work, outputs a signal to the isolation power supply circuit, so that the isolation power supply circuit outputs a power supply BAT_POW, the power supply BAT_POW is converted into a 3.3V voltage through the voltage conversion circuit to supply power to the main controller U3, the first collector U1 is connected to the battery pack 1, that is, the B0-B10 end of the battery pack 1, collects the current and voltage data of each battery in the battery pack 1, and sends the collected data to the main controller U3, when the collection of the battery pack 1 is completed, the main controller U3 sends a signal to the switch circuit, the MOS tube Q7 in the switch circuit is turned on, so that the transistor Q1 is turned on, the VCC5_1 end outputs a current to the isolation circuit, the isolator U15 of the isolation circuit works, and finally the B11 end is effective, so that the isolation balance circuit works, the second collector U2 works, collects the current and voltage data of the resistor between the B11 end and the B20 end, and inputs the data into the main controller U3, and the main controller U3 outputs through the communicator U6 after completing the data collection.

[0042] The above description is directed to the detailed description of the preferred feasible embodiment of the present application, but the embodiment is not used to limit the patent application range of the present application, and any equivalent change or modification change completed under the technical spirit of the present application should belong to the patent range covered by the present application.

Claims

1. A dual-chip cascade data communication system, characterized by, It includes collecting unit, data isolation module, main control module, isolation switch module, power module and external communication module, the collecting unit includes first collector U1 and second collector U2, the second collector U2 and the first collector U1 are directly connected with the main control module, the second collector U2 is connected with the data isolation module, the data isolation module is connected between the main control module, the main control module is connected with the power module, external communication module.

2. A dual-chip cascade data communication system according to claim 1, wherein, The data isolation module includes several groups of isolation balance circuits, the isolation balance circuits are the same structure, wherein the isolation balance circuit includes transistor Q25, the emitter of the transistor Q25 is connected at the battery B11 end, the collector is connected with resistance R89 and connects B11-end, the base is connected with resistance R109 and connects V11 end, V11 end is connected into the second collector U2.

3. A dual-chip cascade data communication system according to claim 2, wherein, The first collector U1 adopts BQ7693001 series chip, the input end is connected with B0-B10 end of battery pack respectively, the No.9 pin of the first collector U1 is connected with the No.2 end of MOS tube N20, the No.3 end of the MOS tube N20 is connected with resistance R162 and diode D18 and then connects B10 end of battery, the both ends of the diode D18 are also connected with resistance R155, the No.1 end of the MOS tube N20 is connected with the No.10 pin of the first collector U1, the No.10 pin of the first collector U1 is also connected with capacitor C45 and then connects ground end.

4. The dual-chip cascade data communication system according to claim 1, wherein, The second collector U2 adopts BQ7693003 series chip, the input end is connected with B11-B20 end of battery pack respectively, and the input end is connected with the output end of isolation balance circuit, the No.9 pin of the second collector U2 is connected with the No.2 end of MOS tube N19, the No.3 end of the MOS tube N19 is connected with resistance R67 and diode D32 and then connects B20 end of battery, the both ends of the diode D32 are also connected with resistance R171, the No.1 end of the MOS tube N19 is connected with the No.10 pin of the second collector U2, and the No.1 end of the MOS tube N19 is also connected with resistance R165 and then connects B20 end of battery.

5. A dual-chip cascade data communication system according to claim 4, wherein, The main control module includes main controller U3, the No.27-No.30 pin of the main controller U3 is connected with the first collector U1 and the second collector U2 respectively, and data interaction is carried out.

6. A dual-chip cascade data communication system according to claim 5, wherein, The isolation switch module includes switch circuit and isolation circuit, the switch circuit includes transistor Q1 and MOS tube Q7, the emitter of the transistor Q1 is connected with VCC-5V power supply end, the collector is connected with VCC5_1 end, the base is connected with resistance R141 and then connects the drain of the MOS tube Q7, the source of the MOS tube Q7 is connected with ground, the gate is connected with resistance R145 and then connects the main controller U3.

7. A dual-chip cascade data communication system according to claim 6, wherein, The isolation circuit is connected between the power module and the second collector U2, the isolation circuit includes isolator U15, transformer B1 and transformer B2, isolator U15 input end is connected VCC5_1 end, output is connected the transformer B1 and transformer B2, the output of the transformer B1 is connected with 5V_IIC power end and B11-end, B11-end is connected with the second collector U2, the output of the transformer B2 is connected with 5V power end and GAN_G end.

8. A dual-chip cascade data communication system according to claim 7, wherein, The power module includes voltage conversion circuit and isolation power supply circuit, the voltage conversion circuit includes voltage regulator U13, converter U14 and converter U11, voltage regulator U13 is connected with BAT_POW power end, output is connected with resistance R68 and inductance L1 output 12V power, then is connected with converter U14, converter U14 converts 12V power into 5V output, 12V power input is connected with the converter U11, and converter U11 is converted into 3.3V output.

9. A dual-chip cascade data communication system according to claim 8, wherein, The isolation power supply circuit includes transistor Q4, transistor Q5 and transistor Q11, the emitter of the transistor Q4 is connected with resistance R140 and diode D29 in series, then is connected with battery B200 end, the collector is connected with BAT_POW power end, the base is connected with the emitter of transistor Q5, the collector of transistor Q5 is also connected with the BAT_POW power end, the base of transistor Q5 is connected with resistance R147 in series, then is connected with the drain of the transistor Q11, the gate of the transistor Q11 is connected with resistance R149 in series, then is connected with the first collector U1, the source of the transistor Q11 is connected with ground, the emitter of the transistor Q4 and the base of the transistor Q5 are connected with resistance R142 in series, one end of the resistance R140 is also connected with bidirectional transient voltage suppression diode D48 in series, then is connected with ground.

10. A dual-chip cascade data communication system according to claim 5, wherein, The external communication module includes isolator U4 and communicator U6, the isolator U4 is connected between the communicator U6 and the main controller U3.

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