Sensitive amplifier circuit and memory
By adjusting the source voltage of the MOS transistor using the current mirror unit and current clamping unit in the sensitive amplifier circuit, the bit line potential dispersion problem of independent NOR-Flash memory when the power supply voltage changes is solved, achieving fast response and high reliability data reading.
Patent Information
- Application Number
- CN202423150013.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2034-12-19
AI Technical Summary
In stand-alone NOR-Flash memory, when the power supply voltage varies over a large range, the bit line potentials become highly discrete, resulting in a large range of read currents for the memory cells and a smaller current window, which affects memory reliability and response speed.
A sensitive amplifier circuit is used, and the source voltage of the MOSFET is adjusted by a current mirror unit and a current clamping unit to reduce the bit line voltage dispersion range and improve the response speed.
This reduces the discrete range of the bit line voltage of the memory cell, improves the response speed and reliability of the sensitive amplifier, and expands its application range under low voltage conditions.
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Figure CN223582691U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of memory, for example to a sense amplifier circuit and a memory. BACKGROUND
[0002] For a stand-alone NOR-Flash memory, a relatively wide working voltage range is generally required, for example, 1.2V-3.6V.
[0003] Under the premise of a large variation range of the power supply voltage, the design difficulty of the convergence of the bit line potential of the memory is increased. If the bit line potential is relatively large, the readout current range of the memory cell is large, the current window between the memory cell and the reference memory cell is small, and the storage reliability index is poor.
[0004] The related art discloses a sense amplifier and a memory. The gate of a first PMOS tube and the gate of a second PMOS tube are connected to the source of a first NMOS tube, the gate of the first NMOS tube is connected to the drain of the second PMOS tube, the drain of the first NMOS tube is connected to a power supply, and the source of the first NMOS tube is connected to ground through a mirror current source providing a fixed current. The gate potential required for the conduction of the second PMOS tube is the difference between the potential required for the drain of the second PMOS tube and the threshold voltage of the first NMOS tube. Based on this, when the potential required for the drain of the second PMOS tube remains unchanged, the present application reduces the gate potential required for the first PMOS tube and the second PMOS tube, thereby reducing the source potential requirement of the first PMOS tube and the second PMOS tube, i.e., reducing the power supply voltage required for the normal operation of the sense amplifier, and expanding the use range of the sense amplifier in the memory under low voltage conditions.
[0005] In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
[0006] The related art relates to a current clamping unit, but has the problem of slow response. CONTENT OF THE INVENTION
[0007] To provide a basic understanding of some aspects of the disclosed embodiments, the following brief summary is given. The summary is not an extensive overview of the application, nor is it intended to identify key / critical elements of the application or to delineate the scope of the embodiments. The sole purpose of the summary is to present some concepts of the embodiments in a simplified form as a prelude to the more detailed description that is presented later.
[0008] The embodiments of the present disclosure provide a sense amplifier circuit and a memory, which improve the response speed while reducing the dispersion range of the bit line potential of the memory.
[0009] In some embodiments, the sense amplifier circuit comprises:
[0010] A current mirror unit includes a pair of transistors for mirroring a first reference current to a second reference current. A first reference current clamping unit includes a first amplifier and a second NMOS transistor. The first input terminal of the first amplifier is connected to a first reference voltage, the second input terminal is connected to the source of the second NMOS transistor, and the output terminal is connected to the gate of the second NMOS transistor, for clamping the source voltage of the second NMOS transistor. The drain of the second NMOS transistor is connected to one transistor of the current mirror unit, and its source is connected to the first reference current. A unit current clamping unit includes a second amplifier and a fifth NMOS transistor. The first input terminal of the second amplifier is connected to a second reference voltage, the second input terminal is connected to the source of the fifth NMOS transistor, and the output terminal is connected to the gate of the fifth NMOS transistor, for clamping the source voltage of the fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the other transistor of the current mirror unit, and its source is connected to the unit current. A comparison unit, connected to the unit current clamping unit, is used to compare a reference voltage and a comparison voltage to output a comparison result.
[0011] Optionally, the comparison voltage is the voltage output by comparing the second reference current and the cell current; wherein the cell current is obtained from the memory cell and the memory cell is connected to the source of the fifth NMOS transistor; the first reference voltage and the second reference voltage are target bit line voltages.
[0012] Optionally, the current mirror unit includes:
[0013] The fifth PMOS transistor has its source connected to the power supply and its drain connected to the drain of the second NMOS transistor in the first reference current clamping unit; the fourth PMOS transistor has its source connected to the power supply and its drain connected to the drain of the fifth NMOS transistor in the unit current clamping unit; the gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor.
[0014] Optionally, the sensitive amplifier circuit also includes:
[0015] The first terminal of the current source is connected to the gate of the current mirror unit transistor; the third NMOS transistor has its source connected to the first terminal of the current source, its drain connected to the power supply, and its gate connected to the drain of the second NMOS transistor of the first reference current clamping unit.
[0016] Optionally, the third NMOS transistor is a MOS transistor with a threshold voltage less than a preset threshold.
[0017] Optionally, the voltage V of the power supply for the current mirror unit DD The following relationship must be satisfied:
[0018] V DD =V BL +V dsat +V THP -V THN
[0019] wherein, V BL is a bit line voltage of the memory cell, V dsat is a drain-source saturation voltage of the second NMOS transistor or the fifth NMOS transistor, V THP is a threshold voltage of the fifth PMOS transistor or the fourth PMOS transistor, V THN is a threshold voltage of the third NMOS transistor.
[0020] Optionally, the current source is a mirror current source.
[0021] Optionally, the sense amplifier circuit further comprises:
[0022] a pre-charge unit comprising a third PMOS transistor, a gate connected to a control signal, a source connected to a power supply, and a drain connected to an output terminal of the current mirror transistor; configured to receive the control signal to pre-charge the sense amplifier circuit.
[0023] Optionally, the comparison unit comprises: a comparator, a non-inverting input terminal of the comparator connected to a comparison voltage, and an inverting output terminal of the comparator connected to a reference voltage; and a voltage dividing resistor comprising a first resistor and a second resistor connected in series, one end of the first resistor connected to a power supply voltage, and the other end of the first resistor connected to the inverting input terminal of the comparator to provide the reference voltage.
[0024] In some embodiments, the memory comprises:
[0025] a memory array comprising memory cells and reference memory cells; and a sense amplifier circuit as described above, configured to read data of the memory cells.
[0026] The sense amplifier circuit and the memory provided by the embodiments of the present disclosure can achieve the following technical effects:
[0027] In the embodiments of the present disclosure, the first reference current clamping unit is arranged in a path of the first reference current, and the cell current clamping unit is arranged in a path of the cell current. The on-off degree of the corresponding MOS transistor is controlled by the amplifier in the two current clamping units, so as to adjust the source voltage of the corresponding MOS transistor. In this way, the influence of the threshold voltage of the MOS transistor on the source voltage can be reduced, so as to reduce the discrete range of the bit line voltage of the memory cell, and the response speed is fast, and the reliability of the sense amplifier is increased.
[0028] The general description above and the following description below are exemplary and explanatory only and are not restrictive of the application. BRIEF DESCRIPTION OF DRAWINGS
[0029] One or more embodiments are illustrated by way of example, in which elements and / or features of the same or similar design, function and / or construction are marked with the same reference number, and implementation is not limited by the drawings, which do not constitute a proportional limitation, and in which:
[0030] Figure 1 is a structural schematic diagram of a sensitive amplifier circuit provided by an embodiment of the present disclosure;
[0031] Figure 2 is a structural schematic diagram of another sensitive amplifier circuit provided by an embodiment of the present disclosure;
[0032] Figure 3 is a structural schematic diagram of another sensitive amplifier circuit provided by an embodiment of the present disclosure;
[0033] Figure 4 is a structural schematic diagram of a memory provided by an embodiment of the present disclosure.
[0034] Reference signs:
[0035] 10: memory; 20: sensitive amplifier; 101: storage unit; 102: reference storage unit; 201: pre-charge unit; 202: current mirror unit; 203: first reference current clamping unit; 204: unit current clamping unit; 205: comparison unit; AMP1: first amplifier; AMP2: second amplifier; CMP: comparator; N2: second NMOS tube; N3: third NMOS tube; N5: fifth NMOS tube; P3: third PMOS tube; P4: fourth PMOS tube; P5: fifth PMOS tube; R1: first resistor; R2: second resistor. DETAILED DESCRIPTION
[0036] In order to enable a more detailed understanding of the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below, and the accompanying drawings are used for reference only and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, a plurality of details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be simplified to facilitate the drawings.
[0037] The terms "first", "second", and the like in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.
[0038] In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "back" and the like indicate the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the embodiments of the present disclosure and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation. In addition, in addition to indicating the orientation or positional relationship, the above-mentioned terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to the specific circumstances.
[0039] In addition, the terms "set", "connected", "fixed" should be broadly understood. For example, "connected" can be fixedly connected, detachably connected, or integrally configured; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.
[0040] Unless otherwise specified, the term "a plurality of" means two or more.
[0041] In the embodiments of the present disclosure, the character " / " represents an "or" relationship between the preceding and following objects. For example, A / B means A or B.
[0042] The term "and / or" is a description of the association between objects, which means that there can be three relationships. For example, A and / or B means: A or B, or, A and B, the three relationships.
[0043] It should be noted that the embodiments in the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0044] In combination with Figure 1As shown, the embodiment of the present disclosure provides a sensitive amplifier circuit, which includes a current mirror unit 202, a first reference current clamping unit 203, a cell current clamping unit 204 and a comparison unit 205. The current mirror unit 202 includes two transistors, which are used to mirror the first reference current Irefcell to the second reference current Icomp. The first reference current clamping unit 203 includes a first amplifier AMP1 and a second NMOS transistor N2; the first input terminal of the first amplifier AMP1 is connected with the first reference voltage VREF_RIO, the second input terminal is connected with the source of the second NMOS transistor N2, and the output terminal is connected with the gate of the second NMOS transistor N2, which is used to clamp the source voltage of the second NMOS transistor N2. The drain of the second NMOS transistor N2 is connected with one transistor of the current mirror unit 202, and the source is connected with the first reference current Irefcell. The cell current clamping unit 204 includes a second amplifier AMP2 and a fifth NMOS transistor N5; the first input terminal of the second amplifier AMP2 is connected with the second reference voltage VREF_IO, the second input terminal is connected with the source of the fifth NMOS transistor N5, and the output terminal is connected with the gate of the fifth NMOS transistor N5, which is used to clamp the source voltage of the fifth NMOS transistor N5. The drain of the fifth NMOS transistor N5 is connected with another transistor of the current mirror unit 202, and the source is connected with the cell current Icell. The comparison unit 205 is connected with the cell current clamping unit 204, which is used to compare the reference voltage V REF_E and the comparison voltage to output the comparison result DOUT.
[0045] Here, the sensitive amplifier includes a first current path, a second current path and a third current path. The working principle is to mirror the first reference current Irefcell (i.e. the first current path) of the memory reference storage unit to the second reference current Icomp (i.e. the second current path) by using the current mirror unit 202. At the same time, the cell current Icell (i.e. the third current path) is obtained from the memory storage unit, and the sizes of the second reference current and the cell current are compared to output the comparison voltage. The comparison unit compares the reference voltage and the comparison voltage to output the comparison result; the comparison result represents the logic state of the read storage unit.
[0046] The bit line potential of the read storage unit mainly depends on the source potential of the fifth NMOS transistor N5 (i.e. the potential of point D in the figure), which is affected by the threshold value of the fifth NMOS transistor. This makes the source potential of the fifth NMOS transistor have a large discrete range, and further makes the discrete range of the bit line potential large, so that the range of the cell current read from the storage unit is large. In order to solve this problem, the second amplifier is arranged in the embodiment of the present disclosure to clamp the source potential of the fifth NMOS transistor.
[0047] Specifically, the first input terminal of the second amplifier AMP2 is connected with the second reference voltage VREF IO, the second input terminal is connected with the source of the fifth NMOS N5, and the output terminal is connected with the gate of the fifth NMOS N5 (in the embodiment of the present disclosure, the first input terminal is the in-phase input terminal). The on-off degree of the fifth NMOS N5 is controlled by the comparison result, and the magnitude of the source potential of the fifth NMOS N5 is adjusted. More specifically, when the sensitive amplifier is working, the second amplifier AMP2 compares the magnitude of the source potential of the fifth NMOS N5 (hereinafter described as the potential of point D) and the second reference voltage VREF IO. When the potential of point D is higher than the second reference voltage VREF IO, the second amplifier AMP2 outputs a low level. The gate voltage of the fifth NMOS N5 is reduced, the on-off degree of the fifth NMOS N5 is weakened, and the potential of point D is weakened. Thus, the potential of point D is equal to the first reference voltage VREF RIO. Similarly, when the potential of point D is lower than the second reference voltage VREF IO, the first amplifier outputs a high level. The gate voltage of the fifth NMOS N5 is increased, the on-off degree of the fifth NMOS N5 is strengthened, and the potential of point D is increased. In this way, the potential of point D is no longer strongly affected by the threshold of the fifth NMOS, the discrete range of the bit line voltage for reading the storage unit is reduced, and the accuracy of the bit line voltage is ensured. At the same time, the design of the amplifier improves the response speed of the voltage clamping.
[0048] Similarly, the cell current read from the storage unit is compared with the second reference current. If the discrete range of the second reference current is large, it means that the discrete range of the reference bit line voltage is large, which also cannot guarantee the accuracy of reading data of the storage unit. Therefore, the first reference current clamping unit is arranged in the first current path of the sensitive amplifier. The source potential of the second NMOS N2 (i.e., the potential of point REFD in the figure) is clamped, and the degree of influence of the source potential on the threshold of the second NMOS N2 is reduced. The working principle of the first reference current clamping unit is the same as that of the cell current clamping unit.
[0049] Specifically, when the potential of point REFD is higher than the first reference voltage VREF RIO, the first amplifier AMP1 outputs a low level to weaken the on-off degree of the second NMOS N2, and the potential of point REFD is reduced. When the potential of point REFD is lower than the first reference voltage VREF RIO, the first amplifier AMP1 outputs a high level to strengthen the on-off degree of the second NMOS N2, and the potential of point REFD is increased. Finally, the potential of point REFD is equal to the first reference voltage VREF RIO, so that the potential of point REFD is no longer strongly affected by the threshold of the second NMOS N2, and the design of the amplifier improves the response speed of the voltage clamping.
[0050] In addition, it should be noted that the high level and low level output by the first amplifier AMP1 and the second amplifier AMP2 are not absolute 1 and 0; but are relatively high level and relatively low level. In this way, the sensitivity of the second NMOS tube N2 and the fifth NMOS tube N5 can be improved.
[0051] By using the sensitive amplifier circuit provided in the embodiments of the present disclosure, a first reference current clamping unit is arranged in the path of the first reference current, and a cell current clamping unit is arranged in the path of the cell current. The conduction degree of the corresponding MOS tube is controlled by the amplifiers in the two current clamping units, so as to adjust the source voltage of the corresponding MOS tube. In this way, the influence of the threshold voltage of the MOS tube on the source voltage can be reduced, so as to reduce the discrete range of the bit line voltage of the storage unit, improve the response speed, and increase the reliability of the sensitive amplifier.
[0052] Optionally, the comparison voltage is the voltage output by comparing the second reference current Icomp and the cell current Icell, the cell current Icell is provided by the storage unit 101 of the memory, and the source of the fifth NMOS tube N5 is connected to the storage unit; the first reference voltage VREF_RIO and the second reference voltage VREF_IO are target bit line voltages.
[0053] Here, the sensitive amplifier is applied to the storage, and the working principle is as described above. Among them, the comparison voltage is the voltage output by comparing the second reference current Icomp and the cell current Icell (i.e. the voltage at point E in the figure). The cell current Icell in the cell current clamping unit 204 is provided by the storage unit 101 (such as a Flash cell) of the memory, that is, the source of the fifth NMOS tube N5 is connected to the storage unit 101 to obtain the cell current Icell. In addition, it should be noted that the first reference current is provided by the reference storage unit 102 (such as a Flash recell) of the memory, and the source of the second NMOS tube N2 is connected to the reference storage unit 102.
[0054] The first reference voltage VREF_RIO and the second reference voltage VREF_IO are the same and are target bit line voltages. Among them, the target bit line voltage can be adjusted based on the demand. By adjusting the size of the first reference voltage VREF_RIO and the second reference voltage VREF_IO, the bit line voltage of the storage unit is adjusted. As an example, the target bit line voltage is 0.7V, and the D point potential and the REFD point potential can be clamped around 0.7V to reduce the discrete range.
[0055] Optionally, the current mirror unit comprises a fourth PMOS transistor P4 and a fifth PMOS transistor P5. The fifth PMOS transistor P5 has a source connected to the power supply, and a drain connected to the drain of the second NMOS transistor N2 of the first reference current clamping unit. The fourth PMOS transistor P4 has a source connected to the power supply, a drain connected to the drain of the fifth NMOS transistor of the unit current clamping unit, and a gate connected to the gate of the fifth PMOS transistor P5.
[0056] Here, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 constitute a current mirror. The fifth PMOS transistor P5 serves as an input transistor, and the fourth PMOS transistor P4 serves as an output transistor (the drain of the fourth PMOS transistor is the output terminal of the current mirror unit) to mirror the first reference current of the reference storage unit as the second reference current. The fourth PMOS transistor P4 is used as a second current path.
[0057] In combination Figure 2 As shown, optionally, the sensitive amplifier circuit further comprises a current source and a third NMOS transistor N3.
[0058] The first end of the current source is connected to the gate of the transistor of the current mirror unit. The source of the third NMOS transistor N3 is connected to the first end of the current source, the drain is connected to the power supply, and the gate is connected to the drain of the second NMOS transistor N2 of the first reference current clamping unit.
[0059] Here, in order to enable the first reference current to be mirrored as the second reference current at a low voltage and ensure the working point of the sensitive amplifier to be normal, the current source and the third NMOS transistor N3 are provided. The first end of the current source is connected to the source of the third NMOS transistor N3 and the gate of the fifth PMOS transistor P5 in the current mirror unit. The drain potential of the fifth PMOS transistor P5 is REFE, and the gate potential of the fifth PMOS transistor P5 and the fourth PMOS transistor P4 is REFE-V THN (V THN the threshold voltage of the third NMOS transistor N3). In this way, the gate potential requirement of the fifth PMOS transistor P5 and the fourth PMOS transistor P4 is reduced, and the potential of the source of the fifth PMOS transistor P5 and the fourth PMOS transistor P4 is also reduced. That is, the power supply voltage required for the sensitive amplifier to work normally is reduced, so that the sensitive amplifier can work normally at a low voltage.
[0060] Optionally, the voltage V DD satisfies the following relationship:
[0061] V DD = V BL + V dsat + V THP -V THN
[0062] wherein VBL VBL is the voltage of the bit line of the memory cell dsat VDSAT is the drain-source saturation voltage of the second NMOS transistor N2 or the fifth NMOS transistor THP VTH is the threshold voltage of the fifth PMOS transistor P5 or the fourth PMOS transistor P4 THN VTH is the threshold voltage of the third NMOS transistor N3
[0063] As mentioned above, the drain voltage of the fifth NMOS transistor depends on the first reference voltage VREF_RIO, and the first reference voltage VREF_RIO is the target bit line voltage. When the target bit line voltage is the bit line voltage of the memory, the drain voltage of the fifth NMOS transistor is V BL . When the sense amplifier is working, the fifth NMOS transistor generally works in the saturation region, and its drain-source voltage is V dsat . Therefore, the source voltage of the fifth NMOS transistor is V BL + V dsat . The gate voltage of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 is REFE-V THN , as the current mirror unit REFE and the E point have the same potential. Therefore, the gate voltage of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 is V BL + V dsat -V THN . Based on the threshold voltage V THP and the gate voltage of the fourth PMOS transistor P4 and the fifth PMOS transistor P5, the source voltage of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 is V BL + V dsat -V THN + |V THP |.
[0064] In the formula, the threshold voltage of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 is generally about -0.6V, and the threshold voltage of the third NMOS transistor N3 is generally in the range of 0.3V-0.8V. The drain-source voltage of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 is generally in the order of mV, which can be ignored. The bit line voltage is generally 0.7V, and therefore the source voltage of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 is close to 1.0V. That is, the sense amplifier can work normally at a voltage of 1.0V or above.
[0065] Optionally, the third NMOS transistor N3 is a MOS transistor with a threshold voltage less than a preset threshold value.
[0066] Here, the third NMOS transistor N3 can be a low-threshold MOS transistor or a zero-threshold NMOS transistor, i.e., a MOS transistor with a threshold voltage less than a preset threshold value. The preset threshold value is less than 0.6V, and exemplarily, the preset threshold value can be 0.4V.
[0067] Optionally, the current source Iref2 is a mirror current source.
[0068] Here, the current source of the embodiment of the present disclosure is obtained by mirroring the main current source outside the sensitive amplifier circuit. The mirror current source can provide accurate current matching and can provide stable current so that the current is not affected by load changes. In this way, it helps to reduce the deviation and noise of the circuit, so that the accuracy of the sensitive amplifier is improved.
[0069] Optionally, the sensitive amplifier circuit further comprises a pre-charge unit 201. The pre-charge unit 201 comprises a third PMOS tube P3, the gate is connected to a control signal, the source is connected to a power supply, and the drain is connected to the output end in the current mirror unit transistor. For receiving a control signal to pre-charge the sensitive amplifier circuit.
[0070] Here, the drain is connected to the output end in the current mirror unit transistor, that is, the drain of the fourth PMOS tube P4. Before the sensitive amplifier reads the storage unit, pre-charging is needed. In the pre-charge stage, the output node of the sensitive amplifier is set to an intermediate voltage. In this way, it is ensured that the sensitive amplifier is in a known state before reading data, improving the accuracy of reading. In the embodiment of the present disclosure, the gate of the third PMOS tube P3 is connected to a control signal, so as to control the pre-charge of the sensitive amplifier by the control signal. For example, the control signal is an ATD_SPREb signal. When the ATD_SPREb signal is a low-level signal, the third PMOS tube P3 is turned on to pre-charge the sensitive amplifier circuit.
[0071] In combination Figure 3 As shown, the comparison unit 205 comprises a comparator CMP and a voltage dividing resistor. The comparator CMP has a same-phase input end connected to a comparison voltage and an opposite-phase output end connected to a reference voltage. The voltage dividing resistor comprises a first resistor R1 and a second resistor R2 connected in series, one end of the first resistor R1 is connected to a power supply voltage, and the other end is connected to the opposite-phase input end of the comparator CMP to provide the reference voltage.
[0072] Here, in order to ensure that the comparison unit has a large enough window (i.e. the voltage range in which the comparator works is wide), the first resistor R1 and the second resistor R2 are used to provide a reference voltage for the comparator. The first end of the first resistor R1 is connected to a power supply, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The second end of the first resistor is connected to the opposite-phase input end of the comparator to provide a reference voltage VREF_E for the comparator. Among them, the resistance ratio of the first resistor and the second resistor makes the reference voltage VREF_E change with the change of the power supply voltage; it can make the comparator window working under the current power supply voltage larger. In this way, the sensitive amplifier can be applied to different power supply voltages to realize the task of sensitive amplification under different power supply voltages.
[0073] In combination Figure 4 As shown in the above, the embodiment of the present disclosure provides a memory, comprising: a memory array 10 comprising memory cells and reference memory cells; and a sense amplifier 20 as described above for reading data of the memory cells. The embodiment of the present disclosure can be applied to a wide voltage range, and realizes a small bit line voltage dispersion of the memory cells and a fast response speed.
[0074] The above description and drawings are illustrative of and not restrictive on the embodiments of the present disclosure. Other embodiments can include structural and other changes. The embodiments represent the possibilities of the variations. Unless specifically required, individual components and functions are optional, and the order of the operations can be changed. Some parts and features of some embodiments can be included in or replace parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims
1. A sense amplifier circuit, characterized by, The circuit comprises: a current mirror unit comprising two transistors, for mirroring a first reference current into a second reference current; a first reference current clamping unit comprising a first amplifier and a second NMOS transistor; a first input terminal of the first amplifier is connected to a first reference voltage, a second input terminal is connected to a source of the second NMOS transistor, and an output terminal is connected to a gate of the second NMOS transistor, for clamping a source voltage of the second NMOS transistor; a drain of the second NMOS transistor is connected to one of the transistors of the current mirror unit, and a source is connected to the first reference current; a cell current clamping unit comprising a second amplifier and a fifth NMOS transistor; a first input terminal of the second amplifier is connected to a second reference voltage, a second input terminal is connected to a source of the fifth NMOS transistor, and an output terminal is connected to a gate of the fifth NMOS transistor, for clamping a source voltage of the fifth NMOS transistor; a drain of the fifth NMOS transistor is connected to the other of the transistors of the current mirror unit, and a source is connected to a cell current; a comparison unit connected to the cell current clamping unit, for comparing a reference voltage and a comparison voltage to output a comparison result.
2. The sensitive amplifier circuit of claim 1, wherein, The application is applied to a memory, and the comparison voltage is a voltage output by comparing the second reference current and the cell current; wherein the cell current is obtained from a storage cell of the memory, and the storage cell is connected to the source of the fifth NMOS transistor; and the second reference voltage and the first reference voltage are target bit line voltages.
3. The sensitive amplifier circuit of claim 1, wherein, The current mirror unit comprises: a fifth PMOS transistor, a source of which is connected to a power supply, and a drain of which is connected to a drain of the second NMOS transistor of the first reference current clamping unit; a fourth PMOS transistor, a source of which is connected to the power supply, and a drain of which is connected to a drain of the fifth NMOS transistor of the cell current clamping unit; and a gate of which is connected to a gate of the fifth PMOS transistor.
4. The sensitive amplifier circuit of claim 1, wherein, Further comprising: a current source, a first end of which is connected to a gate of a transistor of the current mirror unit; a third NMOS transistor, a source of which is connected to the first end of the current source, a drain of which is connected to the power supply, and a gate of which is connected to a drain of the second NMOS transistor of the first reference current clamping unit.
5. The sensitive amplifier circuit of claim 4, wherein, The third NMOS transistor is a MOS transistor with a threshold voltage less than a preset threshold value.
6. The sensitive amplifier circuit of claim 4, wherein, The voltage V of the power supply of the current mirror unit DD satisfies the following relation: V DD = V BL + V dsat + V THP - V THN wherein V BL is a bit line voltage of the memory cell, V dsat is a drain-source saturation voltage of the second NMOS transistor or the fifth NMOS transistor, V THP is a threshold voltage of the fifth PMOS transistor or the fourth PMOS transistor, V THN is a threshold voltage of the third NMOS transistor.
7. The sensitive amplifier circuit of claim 4, wherein, The current source is a mirror-obtained current source.
8. The sensitive amplifier circuit according to any one of claims 1 to 7, characterized in that Further comprising: a pre-charge unit comprising a third PMOS transistor, a gate of which is connected to a control signal, a source of which is connected to the power supply, and a drain of which is connected to an output terminal of a transistor of the current mirror unit; for receiving the control signal to pre-charge the sense amplifier circuit.
9. The sensitive amplifier circuit according to any one of claims 1 to 7, characterized in that The comparison unit comprises: a comparator, a same-phase input terminal of which is connected to the comparison voltage, and an opposite-phase output terminal of which is connected to the reference voltage; a voltage dividing resistor comprising a first resistor and a second resistor connected in series, one end of the first resistor being connected to a power supply voltage, and the other end being connected to an opposite-phase input terminal of the comparator to provide the reference voltage.
10. A memory, comprising: comprising: a storage array comprising storage cells and reference storage cells; and the sense amplifier circuit according to any one of claims 1 to 9, for reading data of the storage cells.