Packaging structure with packaging surface rewiring function and packaging chip
By introducing a redistribution layer (RDL) into the packaging structure, the problem of complex circuit connections and cross-short circuits that are difficult to achieve in traditional packaging is solved, realizing efficient integration and optimized wiring of multi-chip packaging, which is particularly suitable for multi-chip packaging scenarios.
Patent Information
- Application Number
- CN202422978252.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2034-12-02
AI Technical Summary
Traditional framework-based encapsulation cannot achieve complex circuit connections, making it difficult to package multiple chips. Furthermore, existing encapsulation processes are prone to cross-short circuit issues in complex wire bonding scenarios, preventing projects from being implemented.
The packaging structure with surface redistribution capability includes a frame base island, chip, pads and redistribution layer RDL. Pads are formed by drilling and electroplating or grinding the solder joints of flip chips, and a redistribution layer is added to the packaging surface to achieve complex wiring and reduce the risk of cross-short circuits.
It enables efficient routing in complex wire bonding scenarios, reduces the risk of cross-short circuits, optimizes chip size and parasitic parameters, and improves the integration and encapsulation capabilities of multi-chip packages.
Smart Images
Figure CN223582987U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of packaging technology, specifically related to the packaging structure with the function of re-routing the packaging surface, isolation chip. BACKGROUND
[0002] The traditional frame type packaging, because it has only one layer of metal frame, thus the internal complex circuit connection function cannot be carried, and it is difficult to realize the internal multi-core plastic package scheme. In addition, the existing packaging process is difficult to deal with complex wire connection, almost no cross-wire connection is allowed, especially when using the sealing project, many wire connection problems and risks will lead to the project unable to land. SUMMARY
[0003] The utility model solves the technical problem that: provide the packaging structure with the function of re-routing the packaging surface, isolation chip, can realize the re-routing of the packaging surface, and is better applicable to the complex wire connection scene, and improves the chip integration.
[0004] In order to solve the above technical problem, the first technical scheme of the utility model is adopted:
[0005] A packaging structure with the function of re-routing the packaging surface, comprising: frame base island, chip, pad, first plastic package and redistribution layer RDL;
[0006] The frame base island and the chip are plastic packaged in the first plastic package;The chip is arranged on the base island frame;The first plastic package is provided with the pad connected with the chip at the position corresponding to the chip;The redistribution layer RDL is arranged on the first plastic package and connected with the pad.
[0007] Optionally, the pad is led out on the first plastic package at the position corresponding to the chip by the way of punching and electroplating.
[0008] Optionally, the chip is a flip chip;The pad is formed after the soldering point of the flip chip is ground.
[0009] Optionally, the frame base island comprises a first frame base island and a second frame base island which are isolated;The chip comprises a first chip and a second chip;The pad comprises a first pad and a second pad;The redistribution layer RDL comprises a first redistribution layer RDL and a second redistribution layer RDL;
[0010] The first chip is arranged on the first frame base island, and the second chip is arranged on the second frame base island; the first pad is arranged on the first plastic package body at a position corresponding to the first chip, and the second pad is arranged on the first plastic package body at a position corresponding to the second chip; the first redistribution layer RDL is arranged on the first plastic package body at a position corresponding to the first pad and is connected with the first pad; and the second redistribution layer RDL is arranged on the first plastic package body at a position corresponding to the second pad and is connected with the second pad.
[0011] Optionally, the first plastic package body, the pad and the redistribution layer RDL are all encapsulated in the second plastic package body.
[0012] Another technical solution provided by the utility model is:
[0013] A packaging chip comprises the packaging structure with the packaging surface redistribution function.
[0014] Optionally, the packaging chip is an isolator chip.
[0015] The utility model discloses the beneficial effect lies in: the utility model discloses a pad is arranged on the first plastic package body at a position corresponding to the chip, and the pad can be formed by punching and electroplating, and can also be formed by using the pad of flip chip; redistribution layer RDL is additionally arranged on the pad position of the first plastic package body, so that the packaging surface redistribution function is realized, the risk of cross connection is reduced, the problem that complex wire bonding is difficult to produce due to cross short circuit is solved, and wiring can be optimized in the complex wire bonding scene to reduce the size of the chip, and the parasitic parameter can also be improved; in addition, a plurality of chips can be integrated into a single package through the redistribution layer RDL, the sealing function is improved, and the utility model is especially suitable for multi-core packaging scenes, such as isolator chip packaging. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 Fig. 1 is a schematic view of a packaging structure with a packaging surface redistribution function provided by the utility model embodiment one;
[0017] Figure 2 Fig. 2 is a schematic view of another packaging structure with a packaging surface redistribution function provided by the utility model embodiment one;
[0018] Figure 3 Fig. 3 is a schematic view of a multi-core sealing structure provided by the utility model embodiment three;
[0019] Figure 4 Fig. 4 is a schematic view of another multi-core sealing structure provided by the utility model embodiment three;
[0020] Figure 5 For Figure 3 Process flow diagram of multi-core sealing structure one;
[0021] Figure 6 For Figure 4 Process flow diagram of multi-core sealing structure two;
[0022] Label explanation:
[0023] 1, frame base island; 2, chip; 4, solder pad; 5, first plastic sealing body; 6, second plastic sealing body; 7, welding point; 8, redistribution layer RDL;
[0024] 11, first frame base island; 12, second frame base island;
[0025] 21, first chip; 22, second chip;
[0026] 41, first solder pad; 42, second solder pad;
[0027] 81, first redistribution layer RDL; 82, second redistribution layer RDL. DETAILED DESCRIPTION
[0028] In order to explain the technical content, the purpose and the effect of the present application, the following will be described in combination with the embodiments and the drawings.
[0029] Embodiment one
[0030] Please refer to Figure 1 , the present embodiment provides a packaging structure with packaging surface rewiring function.
[0031] The packaging structure with packaging surface rewiring function provided by the present embodiment, as shown in Figure 1 , comprises: frame base island 1, chip 2, solder pad 4, first plastic sealing body 5 and redistribution layer RDL 8.
[0032] The frame base island 1 and the chip 2 are plastic sealed in the first plastic sealing body 5; the chip 2 is arranged on the base island frame 1; the first plastic sealing body 1 is provided with the solder pad 4 connected with the chip at the position corresponding to the chip 2; the redistribution layer RDL 8 is arranged on the first plastic sealing body 5 and connected with the solder pad 4.
[0033] The redistribution layer RDL refers to a metal layer that can realize the redistribution of electrical connection.
[0034] In the present embodiment, the solder pad can be obtained by at least the following two ways:
[0035] In some embodiments, as Figure 1As shown, the pads 4 can be led out by punching and plating. Specifically, the pads 4 vertically connected with the chip 2 are led out by punching circuit at the position corresponding to the chip 2 above the first plastic package 5.
[0036] In yet some specific embodiments, as Figure 2 As shown, the pads 4 can also be directly the face-up soldering points 7 on the flip chip after grinding treatment. That is, the chip 2 is a flip chip, and the soldering points 7 on the flip chip are directly ground as the pads 4. This way can greatly simplify the manufacturing process since the steps of making laser holes and plating the laser holes are omitted, and only direct grinding treatment is needed to obtain the pads.
[0037] In some preferred specific embodiments of the present embodiment, as Figure 1 and Figure 2 As shown, the soldering points of the pads 4 are all vertical soldering points, that is, the soldering points on the pads are vertically connected with the chip and the frame base island. Here, the packaging structure of the present embodiment will have the characteristics of vertical stacking and vertical connection, which can not only compress the structure size, but also shorten the signal transmission path, so that the transmission matching performance is more guaranteed.
[0038] In the present embodiment, a redistribution layer RDL 8 is additionally provided at the position of the pads 4 on the first plastic package 5, so as to realize the packaging surface redistribution function, which can reduce the risk of wire crossing and solve the problem that complex wire bonding cannot be put into production due to the problem of short circuit caused by crossing; at the same time, the chip size can be reduced in the complex wire bonding scene through optimized wiring, and the parasitic parameters can also be improved. In addition, through the redistribution layer RDL, multiple chips can be integrated into a single package, and the co-packaging function is improved.
[0039] The present embodiment is particularly suitable for traditional packaging projects of multi-chip co-packaging. Through redistribution within the package, multi-chip co-packaging can be more easily realized without delaying sample development.
[0040] Embodiment Two
[0041] Please refer to Figure 1 and Figure 2 The present embodiment is further extended based on Embodiment One, and detailed descriptions are given for different types of chips (flip chip and non-flip chip) adopted.
[0042] As Figure 1 shown, for the packaging structure of the chip 2 being a non-flip chip, the redistribution layer RDL 8 is provided at the position corresponding to the chip on the first plastic package 6 and connected with the pads 4 additionally provided on the first plastic package 6.
[0043] As Figure 2As shown, for the flip-chip packaging structure of the chip 2, the redistribution layer RDL 8 is arranged on the first plastic package 6 at a position corresponding to the flip-chip, and is connected to the pads 4 obtained by the flip-chip.
[0044] Corresponding to the two types of chips, i.e. the two implementation forms of the pads, the redistribution layer RDL also has two implementation modes accordingly:
[0045] In some specific embodiments, i.e. in the case of non-flip-chip chip, the signal ports, i.e. pads, to be connected can be first led out on the first plastic package by punching and plating; then, the redistribution layer RDL is formed by copper plating.
[0046] In some other specific embodiments, i.e. in the case of flip-chip chip, the pads of the flip-chip can be first ground flat and then used as pads; then, the redistribution layer RDL is formed by copper plating. It can be understood that, compared with the previous specific embodiment, the specific embodiment eliminates the steps of making laser holes and plating the laser holes, and the redistribution layer RDL can be directly formed on the pads formed by the flip-chip, so that the manufacturing process can be greatly simplified.
[0047] In the embodiment, as shown in Figure 1 and Figure 2 , a second plastic package 6 is further included; the first plastic package 5, the pads 4 and the redistribution layer RDL 8 are all plastic packaged in the second plastic package 6. That is, after the redistribution layer RDL is arranged at the pad position on the first plastic package, the whole is subjected to a packaging process again to obtain the second plastic package. Here, the second plastic package plays a role of fixing the first plastic package, the pads and the redistribution layer RDL.
[0048] Embodiment Three
[0049] Please refer to Figure 3 and Figure 4 , the embodiment is further extended based on Embodiment Two, and provides two multi-chip package structures with package surface redistribution function.
[0050] The first multi-chip package structure with package surface redistribution function provided by the embodiment is shown in Figure 3 , which includes a first frame base island 11 and a second frame base island 12 which are isolated (and can also be understood as independent of each other, without connection relationship); the chip 2 includes a first chip 21 and a second chip 22; the pad 4 includes a first pad 41 and a second pad 42; the redistribution layer RDL 8 includes a first redistribution layer RDL 81 and a second redistribution layer RDL 82;
[0051] The first chip 21 is arranged on the first frame base island 11, and the second chip 22 is arranged on the second frame base island 12; the first plastic package 5 is provided with the first pad 41 at a position corresponding to the first chip 21, and is provided with the second pad 42 at a position corresponding to the second chip 22; the first redistribution layer RDL 81 is arranged on the first plastic package 5 at a position corresponding to the first pad 41, and is connected with the first pad 41; and the second redistribution layer RDL 82 is arranged on the first plastic package 5 at a position corresponding to the second pad 42, and is connected with the second pad 42.
[0052] The multi-chip packaging structure with the packaging surface redistribution function can realize the packaging surface redistribution function of the multi-chip packaging structure, is better applicable to a complex wire bonding scene, and improves the packaging function.
[0053] The second multi-chip packaging structure with the packaging surface redistribution function provided in the embodiment is a flip chip scheme.
[0054] As shown in Figure 4 The first pad 41 and the second pad 42 are directly obtained by grinding the pads 7 on the first chip 21 and the second chip 22, respectively. It can be understood that, compared with the first multi-chip packaging structure, the multi-chip packaging structure with the flip chip has the advantage of simplifying the manufacturing process.
[0055] The multi-chip packaging structure provided in the embodiment simultaneously includes two chip base island structures that are independent of each other and have consistent structures and functions. By using the isolation property between the two chip base island structures, wireless isolation communication transmission can be realized, such as a high-low voltage wireless isolation device in a power system.
[0056] Embodiment Four
[0057] The embodiment further extends the embodiment three, and provides a corresponding process manufacturing procedure for the two multi-chip packaging structures.
[0058] (1) Figure 3 The process procedure of the first multi-chip packaging structure (non-flip chip scheme) is as shown in Figure 5
[0059] S1: manufacturing a frame base island;
[0060] S2: mounting a chip on the frame base island;
[0061] S3: wire bonding a pin;
[0062] S4: first plastic sealing, to obtain a first plastic sealing body;
[0063] S5: laser hole + electroplating + surface treatment, to form a pad on the first plastic sealing body;
[0064] S6: electroplating and re-wiring on the pad, to obtain a redistribution layer RDL;
[0065] S7: second plastic sealing, to obtain a second plastic sealing body;
[0066] S8: cutting and forming, to obtain a finished chip.
[0067] The process flow of the first multi-core sealing structure is as follows: based on the first plastic sealing body, a signal to be connected is led out through a laser hole, the laser hole is filled with electroplating and surface treatment is performed to form a surface-mounted pad; an electroplating circuit is deposited at the pad position, a redistribution layer is formed through pattern transfer to realize the connection of the signal on the first plastic sealing body; and finally, second packaging is performed to obtain a finished chip. The process flow can realize internal redistribution at the packaging level, solve the problem that complex wire bonding cannot be put into production due to cross short circuit, and improve the sealing function.
[0068] Figure 4 The second multi-core sealing structure (flip chip scheme) is shown in the process flow as shown in Figure 6
[0069] S1: frame base island manufacturing;
[0070] S2: flip chip with the face of the pad facing up is attached to the frame base island;
[0071] S3: first plastic sealing, to obtain a first plastic sealing body;
[0072] S4: polishing the pad of the flip chip + surface treatment, to form a pad on the first plastic sealing body;
[0073] S5: electroplating and re-wiring on the pad, to obtain a redistribution layer RDL;
[0074] S6: wire bonding connection pins;
[0075] S7: second plastic sealing, to obtain a second plastic sealing body;
[0076] S8: cutting and forming, to obtain a finished chip.
[0077] The process flow of the second multi-core sealing structure (flip chip scheme) is as follows: since the flip chip is used, the pads are directly obtained by grinding the pads on the basis of the first plastic sealing body; then the redistribution layer RDL is formed by electroplating the conductive lines on the pads; and finally, the second packaging is performed to obtain the finished chip. The internal redistribution at the packaging level can be realized, the problem that the complex wire bonding cannot be put into production due to the cross short circuit problem can be solved, and the sealing function is improved. More importantly, the manufacturing process can be greatly simplified.
[0078] Embodiment five
[0079] The packaging chip provided in the embodiment is based on any one of the embodiments one to four, and comprises the packaging structure with the packaging surface redistribution function described in any one of the embodiments one to four.
[0080] The packaging chip of the embodiment can realize the packaging surface redistribution function, effectively reduce the risk of wire crossing, solve the problem that the complex wire bonding cannot be put into production due to the cross short circuit problem, and optimize the wiring in the complex wire bonding scene to reduce the chip size. The parasitic parameters can also be improved. In addition, the multiple chips can be integrated into a single package through the redistribution layer RDL, the sealing function is improved, and the packaging chip is particularly suitable for the multi-core packaging scene.
[0081] In some preferred specific embodiments of the embodiment, the packaging chip is an isolator chip.
[0082] Since the multi-core packaging chip of the embodiment simultaneously comprises two chip base island structures which are independent of each other and have consistent structures and functions. By utilizing the isolation property between them, the isolator chip can be realized, which is used for wireless isolation communication transmission, such as high and low voltage wireless isolation transmission in a power system and the like.
[0083] In summary, the packaging structure with the packaging surface redistribution function and the packaging chip provided by the utility model realize the packaging surface redistribution function by additionally arranging the redistribution layer RDL. The wiring can be optimized in the complex wire bonding scene, the wire crossing problem is solved, the chip size is reduced, the parasitic parameters are also improved, the sealing function is improved, and the packaging chip is particularly suitable for the multi-core packaging scene, such as the isolator chip packaging.
[0084] The above only describes the embodiments of the utility model, and does not limit the patent range of the utility model, and any equivalent transformation or direct or indirect application in the related technical field based on the content of the utility model specification and drawings is also included in the patent protection range of the utility model.
Claims
1. A packaging structure having a function of re-routing a surface of a package, characterized by comprising: The application relates to a packaging structure with a packaging surface redistribution function. The frame base island and the chip are encapsulated in the first encapsulation body; the chip is arranged on the frame base island; the first encapsulation body is provided with the pads connected with the chip at positions corresponding to the chip; and the redistribution layer RDL is arranged on the first encapsulation body and connected with the pads. The pads are led out by punching and plating at positions on the first encapsulation body corresponding to the chip.
2. The package structure with a package surface rewire function according to claim 1, wherein, The chip is a flip chip; and the pads are formed by grinding the soldering points on the flip chip.
3. The package structure with a package surface rewire function according to claim 1, wherein, The frame base island comprises a first frame base island and a second frame base island which are isolated; the chip comprises a first chip and a second chip; the pads comprise first pads and second pads; and the redistribution layer RDL comprises a first redistribution layer RDL and a second redistribution layer RDL.
4. The package structure with a package surface rewire function according to claim 1, wherein, The first chip is arranged on the first frame base island, the second chip is arranged on the second frame base island; the first encapsulation body is provided with the first pads at positions corresponding to the first chip, and the first encapsulation body is provided with the second pads at positions corresponding to the second chip; the first redistribution layer RDL is arranged on the first encapsulation body at positions corresponding to the first pads and connected with the first pads; and the second redistribution layer RDL is arranged on the first encapsulation body at positions corresponding to the second pads and connected with the second pads. The first encapsulation body, the pads and the redistribution layer RDL are encapsulated in the second encapsulation body.
5. The package structure having a package surface rewire function according to any one of claims 1 to 4, wherein The application relates to a packaging structure with a packaging surface redistribution function.
6. A packaged chip, comprising: The packaging chip is an isolator chip.
7. The chip package of claim 6, wherein,