Entity impedance network for optimizing anti-aliasing circuit

Abstract

The utility model discloses an entity impedance network for optimizing an anti-aliasing circuit, and relates to the technical field of impedance networks. The entity impedance network for optimizing the anti-aliasing circuit comprises an amplifier U1, a positive input pin of the amplifier U1 is connected with one end of a resistor R2, the other end of the resistor R2 is grounded, and a negative input pin of the amplifier U1 is connected with one end of a resistor R1, one end of a resistor R3 and one end of a capacitor C3. The design of the cut-off frequency of 12.2 kHz and the selection of the sampling frequency of 25.6 kHz completely meet the requirements of the Nyquist sampling theorem; the signal frequency requirements of various standards are met, and meanwhile, the aliasing phenomenon of signal acquisition can be effectively avoided; standard requirements are considered, the influence of actual tested equipment on the whole measuring circuit is considered, and the sampling accuracy of current and voltage signals is ensured. The design of the whole circuit is optimized, and the cost is controllable.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of impedance network, concretely is an entity impedance network of optimization anti -aliasing circuit. BACKGROUND

[0002] In the latest electromagnetic compatibility test standard, there are requirements for harmonic current and voltage flicker of devices or products connected to public power grids. These standards divide the current harmonic limit into two categories according to the size of each phase current: "harmonic current emission limit of devices with input current not exceeding 16A per phase" and "harmonic current limit of devices connected to public low-voltage systems with input current > 16A and ≤ 75A per phase". The voltage flicker limit is divided into two categories: "voltage fluctuation limit in low-voltage power supply system for devices with rated current not exceeding 16A" and "voltage variation, voltage fluctuation and flicker limit for devices with rated current 75A and conditional connection".

[0003] The above limit requirements correspond to the latest International Electrotechnical Commission (IEC) standards:

[0004] IEC61000-3-2 standard 2020, harmonic current emission limit of devices with input current not exceeding 16A per phase;

[0005] IEC61000-3-12 standard 2011, harmonic current limit of devices connected to public low-voltage systems with input current > 16A and ≤ 75A per phase;

[0006] IEC61000-3-3 standard 2021, voltage fluctuation limit in low-voltage power supply system for devices with rated current not exceeding 16A;

[0007] IEC61000-3-11 standard 2017, voltage variation, voltage fluctuation and flicker limit for devices with rated current 75A and conditional connection in low-voltage power supply system;

[0008] The above limit requirements also correspond to the latest China National Standardization Management Committee (GB) standards:

[0009] GB17625.1 standard 2022, harmonic current emission limit of devices with input current not exceeding 16A per phase;

[0010] GB17625.8 standard 2015, harmonic current limit of devices connected to public low-voltage systems with input current > 16A and ≤ 75A per phase;

[0011] GB17625.2 standard 2007, voltage fluctuation limit in low-voltage power supply system for devices with rated current not exceeding 16A;

[0012] GB17625.7 standard 2013, voltage changes, voltage fluctuations and flicker limits in low voltage supply systems, rated current 75A and devices with conditional connection;

[0013] According to the latest IEC and GB standards related to harmonic current and voltage flicker, there are corresponding harmonic and interharmonic measuring instruments and flicker meters IEC61000-4-7 and IEC61000-4-15 standards.

[0014] These two standards require the impedance network and the attached measurement circuit to meet the measurement and design standards of IEC61000-4-7 and IEC61000-4-15.

[0015] In IEC61000-4-7 and IEC61000-4-15 standards, both require smoothing and weighted filtering of current or voltage signals. Considering the unity of the measurement circuit, combined with the Nyquist sampling theorem, in order not to distort the analog signal, the sampling frequency of current and voltage signals must be greater than or equal to 2 times the highest frequency in the analog signal spectrum.

[0016] Based on the above requirements, most of the following schemes are adopted:

[0017] As shown in Figure 2 A typical RC low-pass filter operational amplifier circuit, its main purpose is to filter out high-frequency signals contained in the analog current or voltage signal, and its cutoff frequency can be calculated according to the formula f = 1 / (2*3.14159*R*C) to be 338.6275 kHz. This means that when the current or voltage signal frequency exceeds 339 kHz, the analog current or voltage signal will be distorted or attenuated.

[0018] For the current or voltage sampling circuit of the above scheme, although the filter circuit is added, and the circuit cutoff frequency is far more than 100 kHz, which is enough for the subsequent analog-to-digital circuit or data acquisition card DAQ to perform analog-to-digital conversion of the current signal.

[0019] But based on the Nyquist sampling theorem, the sampling frequency must be greater than or equal to 2 times the highest frequency in the analog signal spectrum, so this means that the sampling frequency of the digital signal processing or data acquisition DAQ is at least above 680 kHz.

[0020] For the data acquisition card DAQ that supports such a high sampling rate, the design cost is not cheap.

[0021] If the high-cost data acquisition card DAQ is abandoned, and the low-cost DAQ is used, due to the influence of the sampling rate generally at about 100 kHz, in the process of analog-digital conversion sampling, the problem of superimposing high-frequency signals into low-frequency signals, that is, aliasing phenomenon, will inevitably occur.

[0022] Therefore, if the above filtering scheme is used, the design cost of the voltage and current measurement circuit will increase.

[0023] In addition, with the upcoming IEC61000-3-10 standard, combined with the current IEC61000-3-2 and IEC61000-3-12 standards, the signal frequency that needs to be filtered and sampled is at most 9 kHz.

[0024] Therefore, from the current and future measurement requirements, the above filtering scheme is a completely wasted cost design, and there is a problem of overdesign. Invention content

[0025] (1) Technical problems solved

[0026] In view of the deficiencies of the prior art, the utility model provides an entity impedance network of an optimized anti-aliasing circuit, which solves the above-mentioned problems.

[0027] (2) Technical scheme

[0028] In order to achieve the above purpose, the utility model realizes the following technical scheme: an entity impedance network of an optimized anti-aliasing circuit, comprising: an amplifier U1;

[0029] Among them, the + input pin of the amplifier U1 is connected with one end of the resistor R2, the other end of the resistor R2 is grounded, the - input pin of the amplifier U1 is connected with one end of the resistor R1, one end of the resistor R3 and one end of the capacitor C3, the other end of the resistor R3, the other end of the capacitor C3 and the output end of the amplifier U1 are connected with the Iout end, the positive side power supply pin of the amplifier U1 is connected with one end of the capacitor C1, the negative side power supply pin of the amplifier U1 is connected with one end of the capacitor C2, the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded, the positive side power supply pin and the negative side power supply pin of the amplifier U1 are also connected with a 12V power supply, and the other end of the resistor R1 is connected with the Iin.

[0030] The resistance value of the resistor R3 is 5.89kΩ, and the capacity of the capacitor C3 is 2.2nF.

[0031] Preferably, the capacity of the capacitor C1 and the capacitor C2 is 50uF, and the resistance value of the resistor R1 and the resistor R2 is 10kΩ.

[0032] (III) beneficial effects

[0033] The utility model provides an entity impedance network of optimization anti aliasing circuit, and compared with prior art, at least has following beneficial effects:

[0034] 12.2kHz cut-off frequency design, 25.6kHz sampling frequency selection, fully meet the requirement of nyquist sampling theorem;

[0035] In addition to meeting the signal frequency requirement of each standard, the aliasing phenomenon of signal acquisition can be effectively avoided;

[0036] The standard requirement is considered, and the influence of actual test equipment on the whole measurement circuit is considered, so that the sampling accuracy of current and voltage signals is guaranteed;

[0037] The whole circuit is optimized and the cost is controllable. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 It is the circuit schematic diagram of the utility model;

[0039] Figure 2 It is the principle diagram of prior low pass filter operational amplifier circuit. DETAILED DESCRIPTION

[0040] The technical scheme in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the utility model.

[0041] Please refer to Figure 1 The utility model provides a technical scheme: an entity impedance network of optimization anti aliasing circuit, comprising: amplifier U1;

[0042] Among them, the + input pin of the amplifier U1 is connected with one end of the resistance R2, the other end of the resistance R2 is grounded, the - input pin of the amplifier U1 is connected with one end of the resistance R1, one end of the resistance R3, one end of the capacitor C3, the other end of the resistance R3, the other end of the capacitor C3, the output end of the amplifier U1 and Iout end are connected, the positive side power supply pin of the amplifier U1 is connected with one end of the capacitor C1, the negative side power supply pin of the amplifier U1 is connected with one end of the capacitor C2, the other end of the capacitor C1, the other end of the capacitor C2 are all grounded, the positive side power supply pin and the negative side power supply pin of the amplifier U1 are also connected with 12V power supply, the other end of the resistance R1 is connected with Iin;

[0043] The resistance R3 is 5.89kΩ, the capacity of the capacitor C3 is 2.2nF, the capacity of the capacitor C1 and the capacitor C2 is 50uF, and the resistance R1 and the resistance R2 is 10kΩ.

[0044] The present scheme optimizes the original typical RC low-pass filter operational amplifier circuit design, and the values of R and C are recalculated to make the cutoff frequency of the entire operational amplifier circuit near 12.2kHz. The specific calculation process can be obtained from the formula f = 1 / (2*3.1415926*R*C), f = 1 / (6.2831852*5890*0.0000000022) = 12.28237kHz.

[0045] Therefore, the original 10kΩ resistor can be replaced with a 5.89kΩ resistor, and the original 47pF capacitor can be replaced with a 2.2nF capacitor.

[0046] In addition, for subsequent processing of analog signal conversion to digital signal, a cost-effective data acquisition card DAQ is used, and the sampling frequency of each channel can reach 25.6kHz. The A / D conversion of the analog-digital signal is carried out at this frequency, which fully meets the sampling theorem of Nyquist, and its 25.6kHz is just greater than twice the optimized low-pass filter cutoff frequency of 12.2kHz.

[0047] Through the optimization of the above-mentioned filter circuit, the optimization process of the anti-aliasing circuit for the existing physical impedance network is realized. In this way, the problem of overdesign and high hardware cost in the original typical scheme can be solved, and the design cost of the voltage and current measurement circuit can be controlled within a reasonable range, while meeting the requirements of IEC61000-3-2, IEC61000-3-12, IEC61000-4-7 and IEC61000-4-15 standards for signal sampling and processing below 2kHz, and meeting the requirements of future IEC61000-3-10 standard for signal sampling and processing of 2-9kHz.

[0048] The physical impedance network of the optimized anti-aliasing circuit focuses on re-optimizing the existing current and voltage sampling circuit of the physical impedance network according to the requirements of the current IEC61000-3-2, IEC61000-3-12, IEC61000-4-7 and IEC61000-4-15 standards for signal sampling and processing below 2kHz, and the requirements of the future IEC61000-3-10 standard for signal sampling and processing of 2-9kHz.

[0049] The physical impedance network after optimization of the anti-aliasing circuit needs to be combined with the host computer software and AC / DC power supply to realize the standard test of the input harmonic current and voltage flicker of the test equipment.

[0050] Considering that the input end of the existing test equipment widely adopts an active PFC circuit, the frequency thereof is often concentrated near 20 kHz, and therefore the optimized anti-aliasing circuit is just right in the selection of the cutoff frequency of the filter.

[0051] Therefore, the selection of the cutoff frequency of the entity impedance network of the optimized anti-aliasing circuit, and the design of the resistance and capacitance of the corresponding filter circuit are very crucial.

[0052] It should be noted that, in this document, the terms such as first and second are merely used to distinguish one entity or operation from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device.

[0053] Although the embodiments of the present application have been shown and described, it should be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. An entity impedance network for optimizing an anti-aliasing circuit, characterized by, Include: Amplifier U1; Wherein, the + input pin of the amplifier U1 is connected with one end of the resistor R2, the other end of the resistor R2 is grounded, the - input pin of the amplifier U1 is connected with one end of the resistor R1, one end of the resistor R3 and one end of the capacitor C3, the other end of the resistor R3, the other end of the capacitor C3 and the output of the amplifier U1 are connected with the Iout end, the positive power pin of the amplifier U1 is connected with one end of the capacitor C1, the negative power pin of the amplifier U1 is connected with one end of the capacitor C2, the other end of the capacitor C1 and the other end of the capacitor C2 are grounded, the positive power pin and the negative power pin of the amplifier U1 are also connected with the 12V power supply, the other end of the resistor R1 is connected with the Iin; The resistance value of the resistor R3 is 5.89kΩ, and the capacity of the capacitor C3 is 2.2nF.

2. An entity impedance network for an optimized anti-aliasing circuit according to claim 1, characterized in that: The capacity of the capacitor C1 and the capacitor C2 is 50uF, and the resistance value of the resistor R1 and the resistor R2 is 10kΩ.

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