WIFI circuit

Abstract

The utility model discloses a WIFI circuit. The WIFI circuit comprises a first WIFI module, a second WIFI module and a control module, the first WIFI module is connected with the control module through a high-speed PCIE interface, and the second WIFI module is connected with the control module through an SDIO interface; the first WIFI module comprises a Bluetooth communication end and a voice communication end, and the Bluetooth communication end and the voice communication end of the first WIFI module are connected with the control module. According to the utility model, the first WIFI module is arranged in the WIFI circuit, and a high-speed interface is used for data transmission, so that the data transmission rate is higher, the response speed is higher, and the time delay is lower. The two WIFI modules are arranged at the same time, two WIFI working modes can be supported to be carried out at the same time, and the function of the WIFI circuit is more flexible to realize.

Description

TECHNICAL FIELD

[0001] The utility model relates to the data communication field of LED display screen especially relates to a WIFI circuit. BACKGROUND

[0002] In the existing LED display field, the display control of display panel is the wireless connection mode of single WIFI. The working mode of WIFI is AP (Access Point mode) mode or Station (station) mode. The AP mode is the control of display panel, such as: screen projection, program sending; the Station mode is to surf the Internet by WIFI.

[0003] The AP mode and Station mode of the WIFI circuit of the existing display panel can only select one mode to run alone. UTILITY MODEL CONTENTS

[0004] The utility model provides a WIFI circuit to solve the problem of single data transmission link and poor flexibility in the current LED display field.

[0005] The utility model provides a WIFI circuit, it includes: first WiFi module, second WIFI module and control module,

[0006] The first WIFI module is connected with the control module through high -speed PCIE interface, and the second WIFI module is connected with the control module through SDIO interface,

[0007] The first WIFI module includes bluetooth communication end and voice communication end, and the bluetooth communication end and voice communication end of the first WIFI module are connected with the control module.

[0008] Optionally, it further includes a power module, the first end of the power module is connected with the first power supply, the second end of the power module is connected with the first power -on end of the first WIFI module, and the control end of the power module is connected with the control module.

[0009] The power module includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor and a first field effect transistor.

[0010] The source of the first field effect transistor is connected with the first end of the first capacitor, the first end of the second capacitor, the first end of the first resistor and the first power supply, and the drain of the first field effect transistor is connected with the first end of the third capacitor, the first end of the fourth capacitor and the first power -on end of the first WIFI module.

[0011] The second end of the first capacitor, the second end of the third capacitor and the second end of the fourth capacitor are grounded; the second end of the second capacitor, the second end of the first resistor and the first end of the second resistor are connected with the gate of the first field effect tube, and the second end of the second resistor serves as the control end of the upper power module.

[0012] Optionally, the Bluetooth communication end of the first WIFI module comprises: a Bluetooth serial port sending end, a Bluetooth serial port receiving end, a Bluetooth permission sending end and a Bluetooth request sending end.

[0013] The Bluetooth serial port sending end of the first WIFI module is connected with the first end of the first level conversion module, and the second end of the first level conversion module is connected with the control module.

[0014] The Bluetooth serial port receiving end of the first WIFI module is connected with the first end of the second level conversion module, and the second end of the second level conversion module is connected with the control module.

[0015] The Bluetooth permission sending end of the first WIFI module is connected with the first end of the third level conversion module, and the second end of the third level conversion module is connected with the control module.

[0016] The Bluetooth request sending end of the first WIFI module is connected with the first end of the fourth level conversion module, and the second end of the fourth level conversion module is connected with the control module.

[0017] The first level conversion module comprises: a third resistor, a fourth resistor and a second field effect tube.

[0018] The Bluetooth serial port sending end of the first WIFI module is connected with the first end of the third resistor and the source of the second field effect tube; the gate of the second field effect tube is connected with the second end of the third resistor and a second power supply end; the drain of the second field effect tube is connected with the first end of the fourth resistor and the control module; and the second end of the fourth resistor is connected with the third power supply end.

[0019] The second level conversion module comprises: a fifth resistor, a sixth resistor and a third field effect tube.

[0020] The Bluetooth serial port receiving end of the first WIFI module is connected with the first end of the fifth resistor and the source of the third field effect tube; the gate of the third field effect tube is connected with the second end of the fifth resistor and a second power supply end; the drain of the third field effect tube is connected with the first end of the sixth resistor and the control module; and the second end of the sixth resistor is connected with the third power supply end.

[0021] The third level conversion module comprises: a seventh resistor, an eighth resistor and a fourth field effect tube.

[0022] The Bluetooth of the first WIFI module is connected with the first end of the seventh resistor and the source of the fourth field effect tube; the gate of the fourth field effect tube is connected with the second end of the seventh resistor and the second power supply end; the drain of the fourth field effect tube is connected with the first end of the eighth resistor and the control module; the second end of the eighth resistor is connected with the third power supply end;

[0023] The fourth level conversion module comprises a ninth resistor, a tenth resistor and a fifth field effect tube;

[0024] The Bluetooth request sending port of the first WIFI module is connected with the first end of the ninth resistor and the source of the fifth field effect tube; the gate of the fifth field effect tube is connected with the second end of the ninth resistor and the second power supply end; the drain of the fifth field effect tube is connected with the first end of the tenth resistor and the control module; the second end of the tenth resistor is connected with the third power supply end.

[0025] The voltage of the second power supply is less than the voltage of the third power supply.

[0026] Optionally, the voice communication end of the first WIFI module comprises a voice signal clock port, a voice synchronization signal port, a voice signal input port and a voice signal output port.

[0027] The voice signal clock port is connected with the first end of the first debugging module, and the second end of the first debugging module is connected with the control module.

[0028] The voice synchronization signal port is connected with the first end of the second debugging module, and the second end of the second debugging module is connected with the control module.

[0029] The voice signal input port is connected with the first end of the third debugging module.

[0030] The voice signal output port is connected with the first end of the fourth debugging module, and the second end of the fourth debugging module is connected with the control module.

[0031] Optionally, the high-speed PCIE interface of the first WIFI module comprises a PCIE sending end positive pole and a PCIE sending end negative pole.

[0032] The PCIE sending end positive pole of the first WIFI module is connected with the first end of the first filtering module, and the second end of the first filtering module is connected with the control module.

[0033] The PCIE sending end negative pole of the first WIFI module is connected with the first end of the second filtering module, and the second end of the second filtering module is connected with the control module.

[0034] Optionally, the high-speed PCIE2.0 interface of the first WIFI module further comprises a PCIE receiving end positive pole and a PCIE receiving end negative pole;

[0035] The PCIE receiving end positive pole of the first WIFI module is connected with a first end of a fifth debugging module, and a second end of the fifth debugging module is connected with the control module;

[0036] The PCIE receiving end negative pole of the first WIFI module is connected with a first end of a sixth debugging module, and a second end of the sixth debugging module is connected with the control module.

[0037] Optionally, the WIFI circuit further comprises a first matching circuit and a second matching circuit;

[0038] The first antenna port of the first WIFI module is connected with a first end of the first matching circuit, and a second end of the first matching circuit is connected with a first antenna interface;

[0039] The second antenna port of the first WIFI module is connected with a first end of the second matching circuit, and a second end of the second matching circuit is connected with a second antenna interface;

[0040] The first antenna interface receives a WIFI signal, and the second antenna interface receives a WIFI signal and a Bluetooth signal;

[0041] The first matching circuit comprises an eleventh resistor, a fifth capacitor and a sixth capacitor;

[0042] The first end of the eleventh resistor is connected with the first end of the fifth capacitor and serves as the first end of the first matching circuit, the second end of the eleventh resistor and the first end of the sixth capacitor are connected and serve as the second end of the first matching circuit, and the second end of the fifth capacitor and the second end of the sixth capacitor are grounded;

[0043] The second matching circuit comprises a twelfth resistor, a seventh capacitor and an eighth capacitor;

[0044] The first end of the twelfth resistor is connected with the first end of the seventh capacitor and serves as the first end of the second matching circuit, the second end of the twelfth resistor and the first end of the eighth capacitor are connected and serve as the second end of the second matching circuit, and the second end of the seventh capacitor and the second end of the eighth capacitor are grounded.

[0045] Optionally, the WIFI circuit further comprises a crystal oscillator module;

[0046] The first end of the crystal module is connected with an external crystal input end of the first WIFI module; and the second end of the crystal module is connected with an external crystal output end of the first WIFI module.

[0047] The crystal module comprises a thirteenth resistor, a fourteenth resistor, a ninth capacitor, a tenth capacitor and a first crystal.

[0048] The first end of the thirteenth resistor is the first end of the crystal module; and the second end of the thirteenth resistor is connected with the first end of the ninth capacitor and the first input end of the first crystal.

[0049] The first end of the fourteenth resistor is the second end of the crystal module; and the second end of the fourteenth resistor is connected with the first end of the tenth capacitor and the second input end of the first crystal.

[0050] The second end of the ninth capacitor, the second end of the tenth capacitor, the first ground end of the first crystal and the second ground end of the first crystal are grounded.

[0051] Optionally, the WIFI circuit further comprises an external low-power consumption clock module.

[0052] The power supply end of the external low-power consumption clock module is connected with a second power supply; and the output end of the external low-power consumption clock module is connected with a low-power consumption clock input port of the first WIFI module.

[0053] The external low-power consumption clock module comprises an eleventh capacitor, a fifteenth resistor and a second crystal.

[0054] The first end of the eleventh capacitor is connected with the first end of the fifteenth resistor and serves as the power supply end of the external low-power consumption clock module; and the power supply end of the second crystal serves as the power supply end of the external low-power consumption clock module.

[0055] The second end of the fifteenth resistor is connected with the enable end of the second crystal.

[0056] The output end of the second crystal serves as the output end of the external low-power consumption clock module.

[0057] The ground end of the second crystal and the second end of the eleventh capacitor are grounded.

[0058] Optionally, the first WIFI module comprises an AP6275P chip. BRIEF DESCRIPTION OF DRAWINGS

[0059] In order to more clearly illustrate the technical scheme in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0060] Figure 1 is a structural schematic diagram of a WIFI circuit provided by the embodiment of the present application;

[0061] Figure 2 is a structural schematic diagram of another WIFI circuit provided by the embodiment of the present application;

[0062] Figure 3 is a circuit diagram of a power-on module provided by the embodiment of the present application;

[0063] Figure 4 is a structural schematic diagram of another WIFI circuit provided by the embodiment of the present application;

[0064] Figure 5 is a circuit diagram of a first level conversion module, a second level conversion module, a third level conversion module and a fourth level conversion module provided by the embodiment of the present application;

[0065] Figure 6 is a structural schematic diagram of another WIFI circuit provided by the embodiment of the present application;

[0066] Figure 7 is a structural schematic diagram of another WIFI circuit provided by the embodiment of the present application;

[0067] Figure 8 is a structural schematic diagram of another WIFI circuit provided by the embodiment of the present application;

[0068] Figure 9 is a structural schematic diagram of another WIFI circuit provided by the embodiment of the present application;

[0069] Figure 10 is a circuit diagram of a first matching circuit and a second matching circuit provided by the embodiment of the present application;

[0070] Figure 11 is a structural schematic diagram of another WIFI circuit provided by the embodiment of the present application;

[0071] Figure 12 is a circuit diagram of a crystal oscillator module provided by the embodiment of the present application;

[0072] Figure 13Another structure schematic diagram of WIFI circuit provided by the embodiment of the utility model;

[0073] Figure 14 The circuit diagram of the external low-power clock module provided by the embodiment of the utility model;

[0074] Figure 15 The circuit diagram of the WIFI circuit provided by the embodiment of the utility model. DETAILED DESCRIPTION

[0075] In order to make the person skilled in the art better understand the utility model scheme, the technical scheme in the embodiment of the utility model will be described clearly and completely below in conjunction with the drawings in the embodiment of the utility model, obviously, the described embodiment is only a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment in the utility model, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the utility model.

[0076] It should be noted that the terms "first", "second" and the like in the description and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the utility model described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0077] Figure 1 The structure schematic diagram of the WIFI circuit provided by the embodiment of the utility model, the WIFI circuit of the embodiment of the utility model is applied to the control of LED display screen, as shown in Figure 1 The WIFI circuit includes: first WiFi module 102, second WIFI module 103 and control module 101;The first WiFi module 102 is connected with the control module 101 through high-speed PCIE interface, and the second WIFI module 103 is connected with the control module 101 through SDIO interface;The first WiFi module 102 includes Bluetooth communication end and voice communication end, and the Bluetooth communication end and the voice communication end of the first WiFi module 102 are connected with the control module 101.

[0078] Specifically, the WIFI circuit has two WiFi modules, and the two WiFi modules can simultaneously operate in two different modes. The two modes include an AP (Access Point mode) mode or a Station (station) mode. The AP mode is applied to screen projection: the host computer projects to the LED control card through WIFI, and the projected content is displayed on the LED screen and sent to the program. The Station mode is applied to online: the host computer connects to the router through WIFI to surf the Internet.

[0079] The first WiFi module 102 is connected to the control module 101 through a high-speed PCIE interface. PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. The PCIE interface has a high transmission rate, and the first WiFi module 102 has a faster response rate and lower latency when the WIFI circuit is working.

[0080] The Bluetooth communication end in the first WiFi module 102 is connected to the control module 101. The first WiFi module 102 can communicate through Bluetooth, and the host computer or a separate remote controller can be used to communicate with the first WiFi module 102 through Bluetooth to control the WIFI circuit.

[0081] For example, the WIFI circuit of the embodiment of the utility model is applied to the LED display screen, and the host computer or a separate remote controller is used to communicate with the WiFi module 102 through Bluetooth to control the WIFI circuit, and the host computer or a separate remote controller is used to control the WIFI circuit to switch the working state and the like.

[0082] The voice communication end in the first WiFi module 102 is connected to the control module 101, and the first WiFi module 102 receives the voice data packet, analyzes the control instruction in the data packet, and sends it to the control module 101 for response.

[0083] For example, the voice input end can be a remote controller or a host computer, and voice information is input through the voice input end and sent to the first WiFi module 102. The first WiFi module 102 receives the voice data packet and sends the analyzed control instruction to the control module. Optionally, the control instruction includes operations such as turning off the screen, switching programs, or adjusting the volume of the LED display screen.

[0084] The utility model embodiment provides a kind of WIFI circuit, including two WiFi modules can simultaneously carry out the operation of two kinds of working modes simultaneously.Thereby, first WiFi module is connected with control module by high-speed PCIE interface, and the data exchange rate between first WiFi module and control module is improved.First WiFi module includes Bluetooth communication end and voice communication end and is connected with control module, and the input of control command to WIFI circuit is carried out by Bluetooth communication and voice communication, and the control degree for LED display screen is improved.

[0085] On the basis of each embodiment described above, Figure 2 It is another structure diagram of WIFI circuit provided by the utility model embodiment, Figure 3 It is a circuit diagram of a power-on module provided by the utility model embodiment, as Figure 2 、 Figure 3 As shown in the figure, WIFI circuit further includes:

[0086] Further include power-on module 1021, the first end of power-on module 1021 is connected with first power supply 10221, the second end of power-on module 1021 is connected with the first power-on end of first WiFi module 102, and the control end of power-on module 1021 is connected with control module 101;

[0087] Wherein power-on module 1021 includes: first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, first resistor R1, second resistor R2 and first field effect tube MOS1;

[0088] The source of first field effect tube MOS1 is connected with the first end of first capacitor C1, the first end of second capacitor C2, the first end of first resistor R1 and first power supply, and the drain of first field effect tube MOS1 is connected with the first end of third capacitor C3, the first end of fourth capacitor C4 and the first power-on end VBAT of first WiFi module 102;

[0089] The second end of first capacitor C1, the second end of third capacitor C3 and the second end of fourth capacitor C4 are grounded;The second end of second capacitor C2, the second end of first resistor R1, the first end of second resistor R2 are connected with the gate of first field effect tube MOS1, and the second end of second resistor R2 is as the control end of power-on module 1021.

[0090] Specifically, first WiFi module 102 is connected with power-on module 1021 to control the power-on of first WiFi module 102.Power-on module 1021 controls the on-off between first WiFi module 102 and first power supply 10221 to control whether first power supply 10221 supplies power to first WiFi module 102.

[0091] As Figure 3As shown in the circuit of the power-on module 1021, the first field effect tube MOS1 acts as a switch, and controls whether the first power-on end VBAT and the first power supply end VCC1 are conductive by controlling whether the first field effect tube MOS1 source and drain are conductive. The first power supply end VCC1 is the output end of the first power supply 10221. The first capacitor C1 is used to smooth the power supply fluctuation and reduce the influence of power supply noise on the circuit. The first capacitor C1 helps to stabilize the voltage provided to the MOS1 gate. The second capacitor C2 and the first resistor R1 form an RC delay circuit. When the first field effect tube MOS1 gate receives a control signal, due to the RC delay circuit, the control signal can slowly change the voltage of the MOS1 gate, thereby realizing control of the power-on process of the first WiFi module 102. The third capacitor C3 and the fourth capacitor C4 are used to smooth and decouple the voltage to ensure that the first WiFi module 102 obtains stable power supply. The second resistor R2 acts as a pull-down resistor to ensure that the gate of the first field effect tube MOS1 remains at a low level when there is no control signal, thereby maintaining the off state. Among them, in the power-on circuit, the first port I1 is connected with the control module 101, and is used to accept the power-on control signal from the control module 101.

[0092] For example, when the power-on control signal is low, the first field effect tube MOS1 is conductive, the first power supply end VCC1 and the first power-on end VBAT are conductive, and the first WiFi module is powered on. When the power-on control signal is high, the first field effect tube MOS1 is cut off, and the first WiFi module is powered off. Optionally, the voltage of the first power supply is 3.3V; the first field effect tube MOS1 is a P-channel field effect tube. The capacitance of the first capacitor is 1μF, the capacitance of the second capacitor and the fourth capacitor is 100nF, and the capacitance of the third capacitor is 22μF; the resistance of the first resistor is 100KΩ, and the resistance of the second resistor is 10KΩ.

[0093] On the basis of the above embodiments, Figure 4 Another structure diagram of a WIFI circuit provided by the embodiment of the utility model, Figure 5 is a circuit diagram of a first level conversion module, a second level conversion module, a third level conversion module and a fourth level conversion module provided by the embodiment of the utility model, as Figure 4 、 Figure 5 As shown, the WIFI circuit further comprises: the Bluetooth communication end of the first WiFi module 102 comprises: a Bluetooth serial port sending end port UART_TXD, a Bluetooth serial port receiving end port UART_RXD, a Bluetooth permission sending end port UART_CTS_N and a Bluetooth request sending end port UART_RTS_N.

[0094] The Bluetooth serial port sending end port UART_TXD of the first WiFi module 102 is connected with the first end of the first level conversion module, the second end of the first level conversion module is connected with the control module 101;

[0095] The Bluetooth serial port receiving end port UART_RXD of the first WiFi module 102 is connected with the first end of the second level conversion module, the second end of the second level conversion module is connected with the control module 101;

[0096] The Bluetooth request sending end port UART_RTS_N of the first WiFi module 102 is connected with the first end of the fourth level conversion module, the second end of the fourth level conversion module is connected with the control module 101;

[0097] The Bluetooth request sending end port UART_RTS_N of the first WiFi module 102 is connected with the first end of the fourth level conversion module, the second end of the fourth level conversion module is connected with the control module 101;

[0098] The first level conversion module comprises a third resistor R3, a fourth resistor R4 and a second field effect tube MOS2;

[0099] The Bluetooth serial port sending end port UART_TXD of the first WiFi module 102 is connected with the first end of the third resistor R3 and the source of the second field effect tube MOS2; the gate of the second field effect tube MOS2 is connected with the second end of the third resistor R3 and the second power supply end VCC2; the drain of the second field effect tube MOS2 is connected with the first end of the fourth resistor R4 and the control module 101; the second end of the fourth resistor R4 is connected with the third power supply end VCC3;

[0100] The second level conversion module comprises a fifth resistor R5, a sixth resistor R6 and a third field effect tube MOS3;

[0101] The Bluetooth serial port receiving end port UART_RXD of the first WiFi module 102 is connected with the first end of the fifth resistor R5 and the source of the third field effect tube MOS3; the gate of the third field effect tube MOS3 is connected with the second end of the fifth resistor R5 and the second power supply end VCC2; the drain of the third field effect tube MOS3 is connected with the first end of the sixth resistor R6 and the control module 101; the second end of the sixth resistor R6 is connected with the third power supply end VCC3;

[0102] The third level conversion module comprises a seventh resistor R7, an eighth resistor R8 and a fourth field effect tube MOS4;

[0103] The Bluetooth of the first WiFi module 102 allows the sending port UART_CTS_N to be connected with the first end of the seventh resistor R7 and the source of the fourth field effect tube MOS4; the gate of the fourth field effect tube MOS4 is connected with the second end of the seventh resistor R7 and the second power supply end VCC2; the drain of the fourth field effect tube MOS4 is connected with the first end of the eighth resistor R8 and the control module 101; and the second end of the eighth resistor R8 is connected with the third power supply end VCC3.

[0104] The fourth level conversion module comprises a ninth resistor R9, a tenth resistor R10 and a fifth field effect tube MOS5.

[0105] The Bluetooth request sending port UART_RTS_N of the first WiFi module 102 is connected with the first end of the ninth resistor R9 and the source of the fifth field effect tube MOS5; the gate of the fifth field effect tube MOS5 is connected with the second end of the ninth resistor R9 and the second power supply end VCC2; the drain of the fifth field effect tube MOS5 is connected with the first end of the tenth resistor R10 and the control module 101; and the second end of the tenth resistor R10 is connected with the third power supply end VCC3.

[0106] The voltage of the second power supply end VCC2 is less than the voltage of the third power supply end VCC3.

[0107] Specifically, the first WiFi module 102 includes a Bluetooth communication end: a Bluetooth serial port sending end port UART_TXD, a Bluetooth serial port receiving end port UART_RXD, a Bluetooth permission sending end port UART_CTS_N and a Bluetooth request sending end port UART_RTS_N. Among them, the Bluetooth serial port sending end port UART_TXD is used to send Bluetooth data in the first WiFi module 102 to an external device. The Bluetooth serial port receiving end port UART_RXD is used to receive serial data from an external device. When the control module 101 sends data to the first WiFi module 102 through Bluetooth, the data will be received through the Bluetooth serial port receiving end port UART_RXD and stored in the internal buffer of the first WiFi module 102 for subsequent processing. The Bluetooth permission sending end port UART_CTS_N is used to send a level signal by the control module 101 through the Bluetooth permission sending end port UART_CTS_N when the control module 101 is ready to receive data, indicating "permission to send". After detecting this signal, the first WiFi module 102 will start sending data through the Bluetooth serial port sending end port UART_TXD. When the first WiFi module 102 is ready to send data to the control module 101, the first WiFi module 102 will send a "request to send" level signal to the control module 101 through the Bluetooth request sending end port UART_RTS_N. When the control module 101 can accept Bluetooth data, the control module 101 will send a "permission to send" signal to the first WiFi module 102 through the Bluetooth permission sending end port UART_CTS_N, and then the first WiFi module 102 starts data transmission.

[0108] In the first level conversion circuit, level conversion from the Bluetooth serial port sending end port UART_TXD to the second port I2 of the control module 101 can be performed.

[0109] When the Bluetooth serial port sending end port UART_TXD signal outputs a high level, the gate-source voltage of the second field effect tube MOS2 is Vgs = 0, the second field effect tube MOS2 is cut off, and the voltage value of the signal at the second port I2 is pulled up to the voltage of the third power supply end VCC3 by the fourth resistor. Therefore, the signal at the second port I2 is high level.

[0110] When the signal at the second port I2 outputs a low level, the gate-source voltage Vgs of the second field effect tube MOS2 is the voltage value of the second power supply end VCC2, the second field effect tube MOS2 is turned on, and the voltage value of the signal at the second port I2 is pulled down by the second field effect tube MOS2. Therefore, the signal at the second port I2 is low level.

[0111] For the second level conversion circuit, when the signal output by the third port I3 is high, the gate-source voltage of the third field effect transistor MOS3 is unchanged, the third field effect transistor MOS3 is cut off, and the signal at the Bluetooth serial port sending end port UART_RXD is pulled up to the second power supply end VCC2 by the fifth resistor R5, so that the signal accepted by the Bluetooth serial port receiving end port UART_RXD is high.

[0112] When the signal output by the third port I3 is low, the gate-source voltage of the third field effect transistor MOS3 is unchanged, so that the third field effect transistor MOS3 is cut off. The signal at the Bluetooth serial port receiving end port UART_RXD is pulled to low by the parasitic diode of the third field effect transistor MOS3, so that the signal at the Bluetooth serial port receiving end port UART_RXD is low. Optionally, the models of the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor are SOT23.

[0113] The principles of the third level conversion circuit and the fourth level conversion circuit are the same as those of the first level conversion circuit, and will not be repeated here.

[0114] On the basis of the above embodiments, Figure 6 Another structure diagram of a WIFI circuit provided by the embodiment of the utility model is shown in the figure, and the WIFI circuit comprises: Figure 6 The voice communication end of the first WiFi module 102 comprises a voice signal clock port BT_PCM_CLK, a voice synchronization signal port BT_PCM_SYNC, a voice signal input port BT_PCM_IN and a voice signal output port BT_PCM_OUT. The voice signal clock port BT_PCM_CLK is connected with the first end of the first debugging module 10241, the second end of the first debugging module 10241 is connected with the control module 101. The voice synchronization signal port BT_PCM_SYNC is connected with the first end of the second debugging module 10242, the second end of the second debugging module 10242 is connected with the control module 101. The voice signal input port BT_PCM_IN is connected with the first end of the third debugging module 10243. The voice signal output port BT_PCM_OUT is connected with the first end of the fourth debugging module 10244, and the second end of the fourth debugging module 10244 is connected with the control module 101.

[0115] Specifically, the voice signal clock port BT_PCM_CLK is used to provide a clock signal of pulse code modulation (PCM) voice signal, and the voice signal clock port BT_PCM_CLK provides a stable clock reference for received and transmitted PCM voice data, thereby ensuring the accuracy and integrity of the data.

[0116] The voice synchronization signal port BT_PCM_SYNC is used to provide a synchronization signal for voice data, ensuring that the sent and received data frames are correctly aligned, thereby avoiding data loss or misalignment.

[0117] The voice signal input port BT_PCM_IN is used to receive PCM voice signals from external devices. The voice signal input port BT_PCM_IN is connected to the first terminal of the third debugging module 10243, and the second terminal of the third debugging module 10243 receives voice data signals from external devices. The first WiFi module receives the voice data signals from the external devices and parses them. Optionally, the external device is a remote control, which inputs voice signals through a microphone or audio codec module and sends them to the control module 101.

[0118] The voice signal output port BT_PCM_OUT is used to send the voice data signal parsed internally by the first WiFi module to the control module 101. Optionally, the parsed voice data signal includes control commands for the LED display screen, such as turning off the LED display screen, switching programs, or adjusting the volume.

[0119] Optionally, the first, second, third, and fourth debugging modules are 0Ω resistors.

[0120] Based on the above embodiments, Figure 7 This is a schematic diagram of another WIFI circuit provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of another WIFI circuit provided in an embodiment of the present invention, as shown below. Figure 7 , 8 As shown, the high-speed PCIe interface of the first WiFi module 102 includes: a positive PCIe transmitter terminal PCIe_TDP and a negative PCIe transmitter terminal PCIe_TDN;

[0121] The positive terminal PCIE_TDP of the first WiFi module 102 is connected to the first terminal of the first filter module 10251, and the second terminal of the first filter module 10251 is connected to the control module 101.

[0122] The negative terminal PCIE_TDN of the PCIE transmitter of the first WiFi module 102 is connected to the first terminal of the second filter module 10252, and the second terminal of the second filter module 10252 is connected to the control module 101.

[0123] The high-speed PCIE 2.0 interface of the first WiFi module 102 also includes: PCIE receiver positive terminal PCIE_RDP and PCIE receiver negative terminal PCIE_RDN;

[0124] The positive terminal PCIE_RDP of the first WiFi module 102 is connected to the first terminal of the fifth debugging module 10245, and the second terminal of the fifth debugging module 10245 is connected to the control module 101.

[0125] The negative terminal PCIE_RDN of the PCIE receiver of the first WiFi module 102 is connected to the first terminal of the sixth debugging module 10246, and the second terminal of the sixth debugging module 10246 is connected to the control module 101.

[0126] Specifically, the positive terminal of the PCIe transmitter, PCIE_TDP, is the positive terminal used to transmit data signals in the PCIe interface, and the negative terminal, PCIE_TDN, is also the positive terminal used to transmit data signals in the PCIe interface. Both the positive and negative terminals of the PCIe transmitter (PCIE_TDP and PCIE_TDN) are used to transmit data signals to the control module 101. The first filtering module 10251 and the second filtering module 10252 are used to reduce noise and interference in the signal, ensuring clear data signal transmission. Optionally, the first filtering module 10251 and the second filtering module 10252 are 0.1μF capacitors.

[0127] The positive terminal (PCIE_RDP) of the PCIE receiver is used to receive data signals in the PCIE interface; the negative terminal (PCIE_RDN) is used to receive data signals in the PCIE interface. Both the positive and negative terminals (PCIE_RDP and PCIE_RDN) are used to receive data signals from control module 101. Optionally, the fifth and sixth debugging modules are equipped with 0Ω resistors.

[0128] Based on the above embodiments, Figure 9 This is a schematic diagram of another WIFI circuit provided in an embodiment of the present invention. Figure 10 The circuit diagrams of the first matching circuit and the second matching circuit provided in the embodiments of this utility model are as follows: Figure 9 , 10 As shown, the WIFI circuit further includes: a first matching circuit 10261 and a second matching circuit 10262; the first antenna port ANT1 of the first WiFi module 102 is connected to the first end of the first matching circuit 10261, and the second end of the first matching circuit 10261 is connected to the first antenna interface I4; the second antenna port WL_BT_ANT0 of the first WiFi module 102 is connected to the first end of the second matching circuit 10262, and the second end of the second matching circuit 10262 is connected to the second antenna interface I5; wherein, the first antenna interface I4 receives WIFI signals, and the second antenna interface I5 receives WIFI signals and Bluetooth signals;

[0129] The first matching circuit 10261 comprises an eleventh resistor R11, a fifth capacitor C5 and a sixth capacitor C6; a first end of the eleventh resistor R11 is connected with a first end of the fifth capacitor C5 and serves as a first end of the first matching circuit 10261, a second end of the eleventh resistor R11 and a first end of the sixth capacitor C6 are connected and serve as a second end of the first matching circuit 10261; a second end of the fifth capacitor C5 and a second end of the sixth capacitor C6 are grounded.

[0130] The second matching circuit 10262 comprises a twelfth resistor R12, a seventh capacitor C7 and an eighth capacitor C8; a first end of the twelfth resistor R12 is connected with a first end of the seventh capacitor C7 and serves as a first end of the second matching circuit 10262, a second end of the twelfth resistor R12 and a first end of the eighth capacitor C8 are connected and serve as a second end of the second matching circuit 10262; a second end of the seventh capacitor C7 and a second end of the eighth capacitor C8 are grounded.

[0131] Specifically, the first WiFi module 102 comprises double-antenna ports, wherein a first antenna port ANTI receives a WIFI signal, and a second antenna port WL_BT_ANT0 receives a WIFI signal and a Bluetooth signal. The antenna ports and the antenna interfaces are connected through the first matching circuit 10261 and the second matching circuit 10262.

[0132] In the first matching circuit 10261, the eleventh resistor R11 and the fifth capacitor C5 and the sixth capacitor C6 are used for adjusting the signal impedance between the first antenna port ANTI and the first antenna interface I4.

[0133] In the second matching circuit 10262, the twelfth resistor R12 and the seventh capacitor C7 and the eighth capacitor C8 are used for adjusting the signal impedance between the second antenna port WL_BT_ANT0 and the second antenna interface I5.

[0134] Optionally, the eleventh resistor R11 and the twelfth resistor R12 are 0Ω resistors, and the eleventh resistor R11 and the twelfth resistor R12 serve as debugging modules of the first matching circuit 10261 and the second matching circuit 10262.

[0135] On the basis of the above-mentioned embodiments, Figure 11 a structure diagram of another WIFI circuit provided by the embodiments of the utility model, Figure 12 As shown in the circuit diagram of the crystal oscillator module, Figure 11 、 12 The WIFI circuit further comprises a crystal oscillator module 1028.

[0136] The first end of the crystal module 1028 is connected with an external crystal input end Xtal_IN of the first WIFI module; and the second end of the crystal module 1028 is connected with an external crystal output end Xtal_OUT of the first WIFI module.

[0137] The crystal module 1028 comprises a thirteenth resistor R13, a fourteenth resistor R14, a ninth capacitor C9, a tenth capacitor C10 and a first crystal Y1.

[0138] The first end of the thirteenth resistor R13 is the first end of the crystal module 1028; and the second end of the thirteenth resistor R13 is connected with the first end of the ninth capacitor C9 and the first input end of the first crystal Y1.

[0139] The first end of the thirteenth resistor R13 is the first end of the crystal module 1028; and the second end of the thirteenth resistor R13 is connected with the first end of the ninth capacitor C9 and the first input end of the first crystal Y1.

[0140] The second end of the ninth capacitor C9, the second end of the tenth capacitor C10, the first ground end of the first crystal Y1 and the second ground end of the first crystal Y1 are grounded.

[0141] Specifically, the crystal module 1028 provides a stable clock frequency for the WIFI module. When the thirteenth resistor R13 and the fourteenth resistor R14 are zero resistors, the thirteenth resistor R13 and the fourteenth resistor R14 are used as test ports to test the input and output of the crystal module 1028. When the thirteenth resistor R13 and the fourteenth resistor R14 are not zero resistors, the thirteenth resistor R13 and the fourteenth resistor R14 are used to limit the current and protect the first crystal Y1 from damage by excessive current, while also helping to stabilize the transmission of signals. The ninth capacitor C9 and the tenth capacitor C10 are used to form an oscillation circuit with the crystal to help stabilize the oscillation frequency of the crystal and reduce the influence of external interference on the crystal. Optionally, the capacitance values of the ninth capacitor C9 and the tenth capacitor C10 are 20 pF. The first crystal Y1 is the core element for generating a clock signal, which oscillates according to its inherent frequency to provide an accurate clock signal for the WIFI module.

[0142] On the basis of the above-mentioned embodiments, Figure 13 A structure diagram of another WIFI circuit provided by the embodiments of the present application is shown in the figure, Figure 14 A circuit diagram of an external low-power clock module provided by the embodiments of the present application is shown in the figure, Figure 13 、 14As shown, the WIFI circuit further comprises: an external low-power clock module 1029; a power supply end of the external low-power clock module 1029 is connected to the second power supply 10222, and an output end OUT1 of the external low-power clock module is connected to a low-power clock input port LPO of the first WIFI module; the external low-power clock module 1029 comprises: an eleventh capacitor C11, a fifteenth resistor R15 and a second crystal oscillator Y2; a first end of the eleventh capacitor C11 is connected to a first end of the fifteenth resistor R15 and serves as a power supply end of the external low-power clock module 1029; a power supply end VCC0 of the second crystal oscillator serves as a power supply end of the external low-power clock module; a second end of the fifteenth resistor R15 is connected to an enable end OE of the second crystal oscillator; an output end OUT1 of the second crystal oscillator serves as an output end of the external low-power clock module 1029; a ground end GND3 of the second crystal oscillator and a second end of the eleventh capacitor C11 are grounded.

[0143] Specifically, the eleventh capacitor C11 and the fifteenth resistor R15 are used for filtering and stabilizing the power supply, so as to ensure that the clock module can operate stably. Among them, the eleventh capacitor C11 is used for isolating alternating voltage through direct voltage, and the fifteenth resistor R15 is used for limiting current or voltage division. The power supply end VCC0 of the second crystal oscillator Y2 is connected to the second power supply end VCC2 to provide working voltage for the crystal oscillator. The enable end OE of the second crystal oscillator Y2 is grounded through the fifteenth resistor R15, and is used for controlling the opening and closing of the crystal oscillator. In the circuit as shown in Figure 14 , the enable end OE of the second crystal oscillator Y2 is configured in a normally open state. Optionally, the capacitance of the eleventh capacitor C11 is 0.1 mu F, and the resistance of the fifteenth resistor R15 is 470KΩ.

[0144] On the basis of the above-mentioned embodiments, Figure 15 a circuit diagram of the WIFI circuit provided by the embodiments of the present application is as shown in Figure 15 As shown, the first WIFI module comprises: an AP6275P chip.

[0145] Specifically, in the AP6275P chip, the AP6275P chip comprises a Bluetooth communication end and a voice communication end.

[0146] The Bluetooth serial port sending port UART_TXD, the Bluetooth serial port receiving port UART_RXD, the Bluetooth permission sending port UART_CTS_N and the Bluetooth request sending port UART_RTS_N in the Bluetooth communication end are connected to the control module 101 through a level conversion circuit. Optionally, in the level conversion circuit: the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 have a resistance of 10K; the second field effect tube MOS2, the third field effect tube MOS3, the fourth field effect tube MOS4 and the fifth field effect tube MOS5 are N-type field effect tubes.

[0147] The voice signal clock port BT_PCM_CLK, the voice synchronization signal port BT_PCM_SYNC, the voice signal input port BT_PCM_IN and the voice signal output port BT_PCM_OUT in the voice communication end are connected to the control module 101 through a debugging module. The debugging module is a 0Ω resistor.

[0148] In the AP6275P chip, the PCIE sending end positive pole PCIE_TDP and the PCIE sending end negative pole PCIE_TDN are further included, and the PCIE sending end positive pole PCIE_TDP and the PCIE sending end negative pole PCIE_TDN are connected to the control module 101 through a filtering module; in the AP6275P chip, the PCIE receiving end positive pole PCIE_RDP and the PCIE receiving end negative pole PCIE_RDN are connected to the control module 101 through a debugging module.

[0149] In the AP6275P chip, two antenna connection ports are further included, wherein the first antenna port ANT1 receives a WIFI signal, and the second antenna port WL_BT_ANT0 receives a WIFI signal and a Bluetooth signal. The two antenna connection ports are connected to an antenna interface through a first matching circuit and a second matching circuit. Optionally, in the first matching circuit, the eleventh resistor R11 is a 0Ω resistor, and the twelfth resistor R12 is a 0Ω resistor.

[0150] In the AP6275P chip, an external crystal oscillator input end Xtal_IN and an external crystal oscillator output end Xtal_OUT are further included. The two ends are respectively connected to the first end X1 of the first crystal oscillator Y1 and the second end X2 of the crystal oscillator module circuit through the thirteenth resistor R13 and the fourteenth resistor R14. Optionally, the thirteenth resistor R13 and the fourteenth resistor R14 are debugging resistors or current limiting resistors, and the ninth capacitor C9 and the tenth capacitor C10 have a capacitance of 20pF.

[0151] In the AP6275P chip, a low-power clock input port LPO is further included, the low-power clock input port LPO is connected with an output end OUT1 of a second crystal oscillator Y2 in an external low-power clock circuit, an eleventh capacitor C11 and a fifteenth resistor R15 are used for filtering and stabilizing a power supply, the capacitance of the eleventh capacitor C11 is 0.1 mu F, and the resistance of the fifteenth resistor R15 is 470K omega.

[0152] With reference to the foregoing Figure 15 In the AP6275P chip, a PCIE reset port PCIE_PERST_L is further included, which is used for triggering a reset operation of a PCIE function and ensuring that the chip can start to work again from a known state. The PCIE reset port PCIE_PERST_L is connected with the control module through a level conversion module. A WiFi core reset port WL_REG_ON is connected with the control module through a debugging module, which is used for resetting the WiFi core module in the AP6275P chip to an initial state, so as to solve possible faults, errors or performance problems. A WiFi host wake-up port WL_HOST_WAKE is connected with the control module through the debugging module, which is used for notifying or waking up the WiFi host when the chip receives WiFi data, so that the WiFi host can process the data in time. A Bluetooth core reset port BT_REG_ON is connected with the control module through the level conversion module, which is used for resetting the Bluetooth core module to an initial state. A Bluetooth host wake-up port BT_HOST_WAKE is connected with the control module through the level conversion module, which is used for notifying or waking up the control module 101 when the chip receives Bluetooth data. A Bluetooth device wake-up port BT_WAKE is connected with the control module through the level conversion module, which is used for the control module 101 to wake up the AP6275P chip.

[0153] In the AP6275P chip, a PCI power management event output port PCIE_PME_L is connected with the control module through the debugging module, which is used for notifying the control module 101 about a change or request of a power supply state by a power management controller. A PCIE differential clock input positive port PCIE_REFCLKP and a PCIE differential clock input negative port PCIE_REFCLKN are connected with the control module through the debugging module, which jointly input a differential clock signal. A PCIe clock request port PCIE_CLKREQ_L is connected with the control module through the debugging module, which is used for sending a request clock signal to the control module.

[0154] In the AP6275P chip, an IO power port VDIO is used for connecting an external power supply to supply power to the IO port, and optionally, the IO power port VDIO is externally connected with a 1.8V power supply; a power-on port VBAT is used for connecting an external power supply to supply power to the chip, and optionally, the power-on port VBAT is externally connected with a 3.3V power supply.

[0155] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, the steps described in the present application can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0156] The above specific embodiments do not constitute a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A WIFI circuit, characterized in that, Comprise: The first WIFI module, the second WIFI module and the control module; The first WIFI module is connected with the control module through the high-speed PCIE interface, and the second WIFI module is connected with the control module through the SDIO interface; The first WIFI module includes a Bluetooth communication end and a voice communication end, and the Bluetooth communication end and the voice communication end of the first WIFI module are connected with the control module.

2. The WIFI circuit of claim 1, wherein, It also includes a power-on module, the first end of the power-on module is connected with the first power supply, the second end of the power-on module is connected with the first power-on end of the first WIFI module, and the control end of the power-on module is connected with the control module; The power-on module includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor and a first field effect tube; The source of the first field effect tube is connected with the first end of the first capacitor, the first end of the second capacitor, the first end of the first resistor and the first power supply, and the drain of the first field effect tube is connected with the first end of the third capacitor, the first end of the fourth capacitor and the first power-on end of the first WIFI module; The second end of the first capacitor, the second end of the third capacitor and the second end of the fourth capacitor are grounded, the second end of the second capacitor, the second end of the first resistor and the first end of the second resistor are connected with the gate of the first field effect tube, and the second end of the second resistor serves as the control end of the power-on module.

3. The WIFI circuit of claim 1, wherein, The Bluetooth communication end of the first WIFI module includes a Bluetooth serial port sending end, a Bluetooth serial port receiving end, a Bluetooth permission sending end and a Bluetooth request sending end; The Bluetooth serial port sending end of the first WIFI module is connected with the first end of the first level conversion module, and the second end of the first level conversion module is connected with the control module; The Bluetooth serial port receiving end of the first WIFI module is connected with the first end of the second level conversion module, and the second end of the second level conversion module is connected with the control module; The Bluetooth permission sending end of the first WIFI module is connected with the first end of the third level conversion module, and the second end of the third level conversion module is connected with the control module; The Bluetooth request sending end of the first WIFI module is connected with the first end of the fourth level conversion module, and the second end of the fourth level conversion module is connected with the control module; The first level conversion module includes a third resistor, a fourth resistor and a second field effect tube; The Bluetooth serial port sending end of the first WIFI module is connected with the first end of the third resistor and the source of the second field effect tube, the gate of the second field effect tube is connected with the second end of the third resistor and a second power supply end, the drain of the second field effect tube is connected with the first end of the fourth resistor and the control module, and the second end of the fourth resistor is connected with a third power supply end; The second level conversion module includes a fifth resistor, a sixth resistor and a third field effect tube; The Bluetooth serial port receiving end of the first WIFI module is connected with the first end of the fifth resistor and the source of the third field effect tube, the gate of the third field effect tube is connected with the second end of the fifth resistor and a third power supply end, the drain of the third field effect tube is connected with the first end of the sixth resistor and the control module, and the second end of the sixth resistor is connected with a fourth power supply end. The Bluetooth serial port receiving end of the first WIFI module is connected with the first end of the fifth resistor and the source of the third field effect tube; the gate of the third field effect tube is connected with the second end of the fifth resistor and the second power supply end; the drain of the third field effect tube is connected with the first end of the sixth resistor and the control module; and the second end of the sixth resistor is connected with the third power supply end; The third level conversion module comprises a seventh resistor, an eighth resistor and a fourth field effect tube; The Bluetooth allowed sending port of the first WIFI module is connected with the first end of the seventh resistor and the source of the fourth field effect tube; the gate of the fourth field effect tube is connected with the second end of the seventh resistor and the second power supply end; the drain of the fourth field effect tube is connected with the first end of the eighth resistor and the control module; and the second end of the eighth resistor is connected with the third power supply end; The fourth level conversion module comprises a ninth resistor, a tenth resistor and a fifth field effect tube; The Bluetooth request sending port of the first WIFI module is connected with the first end of the ninth resistor and the source of the fifth field effect tube; the gate of the fifth field effect tube is connected with the second end of the ninth resistor and the second power supply end; the drain of the fifth field effect tube is connected with the first end of the tenth resistor and the control module; and the second end of the tenth resistor is connected with the third power supply end; The voltage of the second power supply is less than the voltage of the third power supply.

4. The WIFI circuit of claim 1, wherein, The voice communication end of the first WIFI module comprises a voice signal clock port, a voice synchronization signal port, a voice signal input port and a voice signal output port; The voice signal clock port is connected with the first end of a first debugging module, and the second end of the first debugging module is connected with the control module; The voice synchronization signal port is connected with the first end of a second debugging module, and the second end of the second debugging module is connected with the control module; The voice signal input port is connected with the first end of a third debugging module; The voice signal output port is connected with the first end of a fourth debugging module, and the second end of the fourth debugging module is connected with the control module.

5. The WIFI circuit of claim 1, wherein, The high-speed PCIE interface of the first WIFI module comprises a PCIE sending end positive pole and a PCIE sending end negative pole; The PCIE sending end positive pole of the first WIFI module is connected with the first end of a first filtering module, and the second end of the first filtering module is connected with the control module; The PCIE sending end negative pole of the first WIFI module is connected with the first end of a second filtering module, and the second end of the second filtering module is connected with the control module.

6. The WIFI circuit of claim 1, wherein, The high-speed PCIE 2.0 interface of the first WIFI module further comprises a PCIE receiving end positive pole and a PCIE receiving end negative pole; The PCIE receiving end positive pole of the first WIFI module is connected with the first end of a fifth debugging module, and the second end of the fifth debugging module is connected with the control module; The PCIE receiving end negative pole of the first WIFI module is connected with the first end of a sixth debugging module, and the second end of the sixth debugging module is connected with the control module.

7. The WIFI circuit of claim 1, wherein, The WIFI circuit further comprises a first matching circuit and a second matching circuit; a first end of the first antenna port of the first WIFI module is connected with a first end of the first matching circuit, and a second end of the first matching circuit is connected with a first antenna interface; a second end of the second antenna port of the first WIFI module is connected with a first end of the second matching circuit, and a second end of the second matching circuit is connected with a second antenna interface; The first antenna interface receives WIFI signals, and the second antenna interface receives WIFI signals and Bluetooth signals. The first matching circuit comprises an eleventh resistor, a fifth capacitor and a sixth capacitor. A first end of the eleventh resistor is connected with a first end of the fifth capacitor and serves as a first end of the first matching circuit, and a second end of the eleventh resistor and a first end of the sixth capacitor are connected and serve as a second end of the first matching circuit; a second end of the fifth capacitor and a second end of the sixth capacitor are grounded. The second matching circuit comprises a twelfth resistor, a seventh capacitor and an eighth capacitor. A first end of the twelfth resistor is connected with a first end of the seventh capacitor and serves as a first end of the second matching circuit, and a second end of the twelfth resistor and a first end of the eighth capacitor are connected and serve as a second end of the second matching circuit; a second end of the seventh capacitor and a second end of the eighth capacitor are grounded.

8. The WIFI circuit of claim 1, wherein, The WIFI circuit further comprises a crystal oscillator module; a first end of the crystal oscillator module is connected with an external crystal oscillator input end of the first WIFI module, and a second end of the crystal oscillator module is connected with an external crystal oscillator output end of the first WIFI module; The crystal oscillator module comprises a thirteenth resistor, a fourteenth resistor, a ninth capacitor, a tenth capacitor and a first crystal oscillator. A first end of the thirteenth resistor serves as a first end of the crystal oscillator module, and a second end of the thirteenth resistor is connected with a first end of the ninth capacitor and a first input end of the first crystal oscillator. A first end of the fourteenth resistor serves as a second end of the crystal oscillator module, and a second end of the fourteenth resistor is connected with a first end of the tenth capacitor and a second input end of the first crystal oscillator. A second end of the ninth capacitor, a second end of the tenth capacitor, a first ground end of the first crystal oscillator and a second ground end of the first crystal oscillator are grounded.

9. The WIFI circuit of claim 1, wherein, The WIFI circuit further comprises an external low-power-consumption clock module; a power supply end of the external low-power-consumption clock module is connected with a second power supply, and an output end of the external low-power-consumption clock module is connected with a low-power-consumption clock input port of the first WIFI module; The external low-power-consumption clock module comprises an eleventh capacitor, a fifteenth resistor and a second crystal oscillator. A first end of the eleventh capacitor is connected with a first end of the fifteenth resistor and serves as a power supply end of the external low-power-consumption clock module; a power supply end of the second crystal oscillator serves as a power supply end of the external low-power-consumption clock module; A second end of the fifteenth resistor is connected with an enable end of the second crystal oscillator. An output end of the second crystal oscillator serves as an output end of the external low-power-consumption clock module; A ground end of the second crystal oscillator and a second end of the eleventh capacitor are grounded.

10. The WIFI circuit of claim 1, wherein, The first WIFI module comprises an AP6275P chip.

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