Debugger

Abstract

An embodiment of the utility model provides a debugger, and relates to the technical field of mainboard debugging, a first acquisition module acquires a first voltage corresponding to a first connecting end of a first connector, then a main control chip determines that the first connector is vacant under the condition that the first voltage is a first preset value, and the first connector is connected with the first connector. And determining that the first connector is correctly connected with a second connector of the external mainboard under the condition that the first voltage is a second preset value, and determining that the first connector is wrongly connected with the second connector under the condition that the first voltage is other values except the first preset value and the second preset value. The first connector and the second connector of the external mainboard are connected by the debugger, so that a worker can timely know that the connection between the first connector and the second connector of the external mainboard is wrong, then the first connector and the second connector are reconnected, and the debugger is used for debugging the external mainboard under the condition that the connection between the first connector and the second connector is correct, so that the debugging success rate is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the mainboard debugging technical field especially, and it relates to a kind of debuggers. BACKGROUND

[0002] In order to use the debugger to debug the mainboard, the debugger needs to be electrically connected with the mainboard, specifically, by electrically connecting the connector of the debugger with the connector of the mainboard.

[0003] However, since the staff cannot know the correctness of the connection between the connector of the debugger and the connector of the mainboard, in the case of incorrect connection between the connector of the debugger and the connector of the mainboard, the staff uses the debugger to debug the mainboard, resulting in debugging failure. UTILITY MODEL CONTENTS

[0004] The utility model provides a kind of debugger to at least solve the problem of prior art in that staff cannot know the correctness of the connection between the connector of the debugger and the connector of the mainboard, in the case of incorrect connection between the connector of the debugger and the connector of the mainboard, the staff uses the debugger to debug the mainboard, resulting in debugging failure.

[0005] The utility model embodiment provides a kind of debugger, comprising: main control chip, first connector and first acquisition module;

[0006] The first connector includes a first connection end, and the first connection end is electrically connected with the input end of the first acquisition module;The first connector is used to be electrically connected with the second connector of external mainboard;The second connector includes a second connection end, and the first connection end is used to be electrically connected with the second connection end;

[0007] The output end of the first acquisition module is electrically connected with the first acquisition end of the main control chip, and the first acquisition module is used to acquire the first voltage corresponding to the first connection end;

[0008] The main control chip is used to determine that the first connector is vacant in the case of the first voltage being first preset value, and determine that the first connector is connected correctly with the second connector in the case of the first voltage being second preset value, and determine that the first connector is connected incorrectly with the second connector in the case of the first voltage being other values outside the first preset value and the second preset value.

[0009] Optionally, the first acquisition module comprises a first resistor, a second resistor and a third resistor; a first end of the first resistor is configured to be electrically connected with a first power supply, a second end of the first resistor is electrically connected with a first end of the second resistor and the first connecting end respectively; a first end of the second resistor is electrically connected with the first connecting end, a second end of the second resistor is electrically connected with a first end of the master control chip and a first end of the third resistor respectively; a second end of the third resistor is grounded.

[0010] Optionally, the debugger further comprises a plurality of second acquisition modules, the first connector comprises a plurality of third connecting ends, the third connecting ends correspond to the second acquisition modules one by one; the master control chip further comprises a plurality of second acquisition ends, the second acquisition modules correspond to the second acquisition ends one by one; the second connector comprises a plurality of fourth connecting ends, at least part of the third connecting ends have corresponding fourth connecting ends; the third connecting end is electrically connected with an input end of the second acquisition module corresponding to the third connecting end; the third connecting end is configured to be electrically connected with the fourth connecting end corresponding to the third connecting end; an output end of the second acquisition module is electrically connected with the second acquisition end corresponding to the second acquisition module, the second acquisition module corresponding to the third connecting end is configured to acquire the second voltage corresponding to the third connecting end; the master control chip is specifically configured to determine that the first connector is vacant or the external mainboard is not powered on in a case where each of the second voltages is a third preset value, and determine that the debugger is in communication with the external mainboard and the external mainboard is powered on in a case where at least one of the second voltages is greater than the third preset value.

[0011] Optionally, each of the second acquisition modules comprises a fourth resistor and a fifth resistor; in the second acquisition module, a first end of the fourth resistor is electrically connected with the third connecting end corresponding to the second acquisition module, a second end of the fourth resistor is electrically connected with the second acquisition end corresponding to the second acquisition module and a first end of the fifth resistor respectively; a first end of the fifth resistor is electrically connected with the second acquisition end corresponding to the second acquisition module, a second end of the fifth resistor is grounded.

[0012] Optionally, the debugger further comprises a voltage output module and a level shift module; the voltage output module comprises a plurality of control input terminals; the master control chip further comprises a plurality of control output terminals and a plurality of first signal terminals, the control output terminals correspond to the control input terminals one by one; the level shift module comprises a first voltage input terminal, a plurality of second signal terminals and a plurality of third signal terminals, the first signal terminals correspond to the second signal terminals one by one, and the second signal terminals correspond to the third signal terminals one by one; the first connector has a plurality of connection terminals, and the third signal terminals have corresponding connection terminals of the first connector; in the master control chip, the control output terminals are electrically connected to the control input terminals corresponding to the control output terminals, and the first signal terminals are electrically connected to the second signal terminals corresponding to the first signal terminals; the master control chip is further configured to control the output terminals of the voltage output module to output a third voltage through the plurality of control output terminals according to the second voltage, the third voltage being matched with the external mainboard; the output terminals of the voltage output module are electrically connected to the first voltage input terminal; in the level shift module, the third signal terminals are electrically connected to the connection terminals of the first connector corresponding to the third signal terminals; the level shift module is configured to set the voltage of the signal input by the first signal terminal to the third voltage and output through the third signal terminal corresponding to the first signal terminal.

[0013] Optionally, the voltage output module comprises a plurality of switching devices and a voltage output submodule, the voltage output submodule comprises a plurality of voltage setting terminals, the switching devices correspond to the voltage setting terminals one by one, and the switching devices correspond to the control output terminals one by one; the control terminals of the switching devices are electrically connected to the control output terminals corresponding to the switching devices, the first ends of the switching devices are electrically connected to the voltage setting terminals corresponding to the switching devices, and the second ends of the switching devices are grounded; the output terminals of the voltage output submodule are electrically connected to the first voltage input terminal.

[0014] Optionally, the voltage output module further comprises a sixth resistor; the voltage output submodule further comprises a first enable terminal; the master control chip further comprises an enable control terminal; the first end of the sixth resistor is electrically connected to the enable control terminal, and the second end of the sixth resistor is electrically connected to the first enable terminal.

[0015] Optionally, the types of the switching devices include MOS tubes and triodes.

[0016] Optionally, the voltage output submodule is a low dropout linear regulator.

[0017] Optionally, the debugger further comprises a plurality of electrostatic discharge protectors, each of the first connectors corresponding to the third signal end has a corresponding electrostatic discharge protector; a first end of the electrostatic discharge protector is electrically connected to the connecting end of the first connector corresponding to the electrostatic discharge protector, and a second end of the electrostatic discharge protector is grounded.

[0018] In the embodiment of the present application, the first acquisition module acquires the first voltage corresponding to the first connecting end of the first connector, and then the main control chip determines that the first connector is vacant when the first voltage is the first preset value, determines that the first connector is correctly connected with the second connector of the external mainboard when the first voltage is the second preset value, and determines that the first connector is incorrectly connected with the second connector when the first voltage is other values than the first preset value and the second preset value, so that the worker can know in time that the first connector is incorrectly connected with the second connector of the external mainboard, and then the first connector and the second connector are reconnected, and the debugger is used to debug the external mainboard when the first connector and the second connector are correctly connected, thereby improving the success rate of debugging. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical scheme of the embodiment of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiment of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0020] Figure 1 is a structural schematic diagram of a debugger provided by the embodiment of the present application;

[0021] Figure 2 is a specific structural schematic diagram of a debugger provided by the embodiment of the present application;

[0022] Figure 3 is another specific structural schematic diagram of a debugger provided by the embodiment of the present application;

[0023] Figure 4 is still another specific structural schematic diagram of a debugger provided by the embodiment of the present application;

[0024] Figure 5 is a structural schematic diagram of a second connector provided by the embodiment of the present application;

[0025] Figure 6 is a structural schematic diagram of another second connector provided by the embodiment of the present application;

[0026] Figure 7Is a structure diagram of a second connector provided by the embodiment of the utility model.

[0027] Reference signs:

[0028] 10 - first connector; 101 - first connection end; 102 - third connection end; 103 - fifth connection end; 111 - internal connection port; 20 - first acquisition module; 201 - input end of first acquisition module; 202 - output end of first acquisition module; 30 - main control chip; 301 - first acquisition end; 302 - second acquisition end; 303 - control output end; 304 - first signal end; 305 - enable control end; 40 - second acquisition module; 401 - input end of second acquisition module; 402 - output end of second acquisition module; 50 - voltage output module; 501 - control input end; 502 - output end of voltage output module; 503 - second enable end; 51 - voltage output submodule; 511 - voltage setting end; 512 - first enable end; 513 - output end of voltage output submodule; 514 - input end of voltage output submodule; 515 - power good indication end; 516 - bias supply voltage end; 517 - feedback voltage end; 518 - output voltage sensing end; 519 - soft start end; 520 - second ground end; 521 - pad end; 60 - level shift module; 601 - first voltage input end; 602 - second signal end; 603 - third signal end; 604 - second voltage input end; 605 - third enable end; 606 - first ground end; R1 - first resistance; R2 - second resistance; R3 - third resistance; R4 - fourth resistance; R5 - fifth resistance; R6 - sixth resistance; R7 - seventh resistance; R8 - eighth resistance; R9 - ninth resistance; R10 - tenth resistance; C1 - first capacitor; C2 - second capacitor; C3 - third capacitor; C4 - fourth capacitor; C5 - fifth capacitor; C6 - sixth capacitor; C7 - seventh capacitor; C8 - eighth capacitor; Q1 - switch device; D1 - electrostatic discharge protector. DETAILED DESCRIPTION

[0029] In order to make the above-mentioned purpose, features and advantages of the utility model more obvious and easy to understand, the utility model is further explained in detail below by combining with the drawings and specific embodiments.

[0030] Reference Figure 1The utility model embodiment provides a kind of debugger, it include: main control chip 30, first connector 10 and first acquisition module 20;The first connector 10 includes first connection end 101, the input end 201 of the first acquisition module 20 is electrically connected with the first connection end 101;The first connector 10 is used to be electrically connected with the second connector of external mainboard;The second connector includes second connection end, and the first connection end 101 is used to be electrically connected with the second connection end;The output end 202 of the first acquisition module 20 is electrically connected with the first acquisition end 301 of the main control chip 30, and the first acquisition module 20 is used to collect the first voltage corresponding to the first connection end 101;The main control chip 30 is used to determine that the first connector 10 is vacant in the case where the first voltage is first preset value, and in the case where the first voltage is second preset value, it is determined that the first connector 10 is connected correctly with the second connector, and in the case where the first voltage is other value outside the first preset value and the second preset value, it is determined that the first connector 10 is connected with the second connector incorrectly.

[0031] It needs to be explained that the connection end of first connector 10 is multiple, and the first connection end 101 is one connection end of first connector 10;The connection end of second connector is multiple, and the second connection end is one connection end of second connector;Each connection end of second connector has corresponding connection end of first connector 10, and the first connection end 101 corresponds to the second connection end.

[0032] The first connector 10 is vacant, which is called that external mainboard is not in place, i.e. the first connector 10 is not electrically connected with the second connector, and at this time, the first voltage is the first preset value;External mainboard is in place, i.e. the first connector 10 is electrically connected with the second connector;The first connector 10 is connected correctly with the second connector, i.e. the connection end of second connector and the connection end of first connector 10 are all connected correctly, specifically, the connection end of second connector is electrically connected with the connection end of first connector 10 corresponding to the connection end of second connector, and at this time, the first voltage is the second preset value;

[0033] The first connector 10 is connected to the second connector incorrectly, that is, the connection end of the second connector is connected to the connection end of the first connector 10 incorrectly, specifically, the connection end of one second connector is electrically connected to the connection end of another second connector corresponding to the first connector 10, at this time, the first voltage is a value other than the first preset value and the second preset value, for example, the connection end of the second connector is arranged in a matrix form, the matrix includes n rows and m columns, the second connection end is located in the first row and the first column of the matrix, and in the case of reverse connection between the first connector 10 and the second connector, the first connection end 101 is electrically connected to the connection end of the second connector located in the nth row and the mth column of the matrix, at this time, the first connector 10 is connected to the second connector incorrectly, and the first voltage is a value other than the first preset value and the second preset value, wherein n and m are positive integers.

[0034] The main control chip 30 is electrically connected to the first connector 10, and in the case of correct connection between the first connector 10 and the second connector, the external mainboard is debugged using the debugger; specifically, in some embodiments, the main control chip 30 is a system on chip (SoC).

[0035] The debugger is used to be electrically connected to the debugging interface on the external mainboard, wherein the debugging interface on the external mainboard is the second connector of the external mainboard, specifically, the first connector 10 of the debugger is electrically connected to the second connector of the external mainboard.

[0036] In some embodiments, the second connector of the external mainboard is a Joint Test Action Group (JTAG) connector, an Embedded JTAG (EJTAG) connector or other types of connectors, that is, the debugging interface on the external mainboard is a JTAG debugging interface or an EJTAG debugging interface, and the debugging interface on the external mainboard can also be other types of debugging interfaces, which are not limited here; the debugger is a JTAG debugger, an EJTAG debugger or other types of debuggers, and the first connector 10 of the debugger is a JTAG connector, an EJTAG connector or other types of connectors, which are not limited here.

[0037] In the embodiment of the utility model, through the first acquisition module 20 gathers the first voltage corresponding to the first connecting end 101 of the first connector 10, then through the main control chip 30, in the case that the first voltage is the first preset value, determine that the first connector 10 is vacant, and in the case that the first voltage is the second preset value, determine that the first connector 10 is connected correctly with the second connector of the external mainboard, and in the case that the first voltage is the first preset value and the second preset value outside other values, determine that the first connector 10 is connected incorrectly with the second connector, so that the staff can know that the first connector 10 is connected incorrectly with the second connector of the external mainboard in time, and then reconnect the first connector 10 with the second connector, and in the case that the first connector 10 is connected correctly with the second connector, use the debugger to debug the external mainboard, improve the success rate of debugging.

[0038] Optionally, referring to Figure 3 In some embodiments, the first acquisition module 20 includes a first resistor R1, a second resistor R2 and a third resistor R3; a first end of the first resistor R1 is configured to be electrically connected with a first power supply, a second end of the first resistor R1 is electrically connected with a first end of the second resistor R2 and the first connecting end 101 respectively; the first end of the second resistor R2 is electrically connected with the first connecting end 101, and a second end of the second resistor R2 is electrically connected with a first end of the main control chip 30 and a first end of the third resistor R3 respectively; a second end of the third resistor R3 is grounded.

[0039] It should be noted that the first resistor R1, the second resistor R2 and the third resistor R3 are all voltage dividing resistors; the first voltage is the voltage of the third resistor R3.

[0040] The first preset value is the voltage value of the first voltage in the case that the first connector 10 is vacant, and the expression of the first preset value is:

[0041]

[0042] Wherein, u1 is the first preset value, U1 is the voltage value of the first power supply, r1 is the resistance value of the first resistor R1, r2 is the resistance value of the second resistor R2, and r3 is the resistance value of the third resistor R3.

[0043] In some embodiments, in the external mainboard, the second connecting end is electrically connected with a first end of a tenth resistor R10, a second end of the tenth resistor R10 is electrically connected with a second power supply, and the tenth resistor R10 is a pull-up resistor; the second preset value is the voltage value of the first voltage in the case that the first connector 10 is connected correctly with the second connector, and the expression of the second preset value is:

[0044]

[0045] Wherein, u2 is the first preset value, U2 is the voltage value of the second power supply, and U2 is equal to U1;r 10 is the resistance value of the tenth resistor R10.

[0046] In some embodiments, in the external mainboard, the second connection end is electrically connected with the first end of the eleventh resistor, the second end of the eleventh resistor is grounded, and the eleventh resistor is a pull-down resistor;The second preset value is the voltage value of the first voltage in the case that the first connector 10 is correctly connected with the second connector, and the expression of the second preset value is:

[0047]

[0048] Wherein, r 11 is the resistance value of the eleventh resistor.

[0049] In some embodiments, in the case that the first connector 10 is incorrectly connected with the second connector, the first connection end 101 is electrically connected with the VCC end of the second connector, the VCC end of the second connector is one connection end of the second connector, and the VCC end of the second connector is electrically connected with the third power supply;The expression of other values except the first preset value and the second preset value is:

[0050]

[0051] Wherein, u3 is other values except the first preset value and the second preset value, U3 is the voltage value of the third power supply, and U3 is equal to U1.

[0052] In the embodiment of the utility model, the voltage of the third resistor R3 is collected by the main control chip 30, so as to realize the collection of the first voltage corresponding to the first connection end 101.

[0053] Optionally, referring to Figure 2In some embodiments, the debugger further comprises a plurality of second acquisition modules 40, the first connector 10 comprises a plurality of third connection ends 102, the third connection ends 102 correspond to the second acquisition modules 40 one by one; the master control chip 30 further comprises a plurality of second acquisition ends 302, the second acquisition modules 40 correspond to the second acquisition ends 302 one by one; the second connector comprises a plurality of fourth connection ends, at least part of the number of third connection ends 102 has a corresponding fourth connection end; the third connection end 102 is electrically connected with the input end 401 of the second acquisition module 40 corresponding to the third connection end 102; the third connection end 102 is used for being electrically connected with the fourth connection end corresponding to the third connection end 102; the output end 402 of the second acquisition module 40 is electrically connected with the second acquisition end 302 corresponding to the second acquisition module 40, and the second acquisition module 40 corresponding to the third connection end 102 is used for acquiring the second voltage corresponding to the third connection end 102; the master control chip 30 is specifically used for determining that the first connector 10 is empty or the external mainboard is not powered on in the case that each of the second voltages is a third preset value, and determining that the debugger is in communication with the external mainboard and the external mainboard is powered on in the case that at least one of the second voltages is greater than the third preset value.

[0054] It should be noted that the external mainboard not being powered on means that the external mainboard is in a power-off state, and the external mainboard being powered on means that the external mainboard is in a power-on state.

[0055] Specifically, in some embodiments, the third preset value is 0 volt.

[0056] In the embodiment of the utility model, the second acquisition module 40 is used for acquiring the second voltage corresponding to the third connection end 102, and then the master control chip 30 is used for determining that the first connector 10 is empty or the external mainboard is not powered on in the case that each of the second voltages is a third preset value, and determining that the debugger is in communication with the external mainboard and the external mainboard is powered on in the case that at least one of the second voltages is greater than the third preset value.

[0057] Optionally, in some embodiments, each of the second acquisition modules 40 comprises a fourth resistor R4 and a fifth resistor R5; in the second acquisition module 40, a first end of the fourth resistor R4 is electrically connected with the third connection end 102 corresponding to the second acquisition module 40, a second end of the fourth resistor R4 is respectively electrically connected with the second acquisition end 302 corresponding to the second acquisition module 40 and a first end of the fifth resistor R5; the first end of the fifth resistor R5 is electrically connected with the second acquisition end 302 corresponding to the second acquisition module 40, and a second end of the fifth resistor R5 is grounded.

[0058] It should be noted that the fourth resistor R4 and the fifth resistor R5 are voltage dividing resistors; the second voltage collected by the second collection module 40 is the voltage of the fifth resistor R5 in the second collection module 40.

[0059] Specifically, the third preset value is 0 volt; in some embodiments, in the external mainboard, one of the fourth connection terminals is the VCC terminal of the second connector, and the fourth connection terminals other than the VCC terminal of the second connector have corresponding twelfth resistors, the fourth connection terminal is electrically connected with the first end of the twelfth resistor corresponding to the fourth connection terminal, the second end of the twelfth resistor is electrically connected with the fourth power supply, and the twelfth resistor is a pull-up resistor; in other embodiments, in the external mainboard, each fourth connection terminal has a corresponding twelfth resistor, the fourth connection terminal is electrically connected with the first end of the twelfth resistor corresponding to the fourth connection terminal, the second end of the twelfth resistor is electrically connected with the fourth power supply, and the twelfth resistor is a pull-up resistor.

[0060] In the embodiment of the utility model, the voltage of the fifth resistor R5 is collected to realize the collection of the second voltage corresponding to the third connection terminal 102.

[0061] Optionally, referring to Figure 2In some embodiments, the debugger further comprises a voltage output module 50 and a level shift module 60; the voltage output module 50 comprises a plurality of control input terminals 501; the master control chip 30 further comprises a plurality of control output terminals 303 and a plurality of first signal terminals 304, the control output terminals 303 correspond to the control input terminals 501 one by one; the level shift module 60 comprises a first voltage input terminal 601, a plurality of second signal terminals 602 and a plurality of third signal terminals 603, the first signal terminals 304 correspond to the second signal terminals 602 one by one, and the second signal terminals 602 correspond to the third signal terminals 603 one by one; the first connector 10 has a plurality of connection ends, and the third signal terminals 603 have corresponding connection ends of the first connector 10; in the master control chip 30, the control output terminals 303 are electrically connected to the control input terminals 501 corresponding to the control output terminals 303, and the first signal terminals 304 are electrically connected to the second signal terminals 602 corresponding to the first signal terminals 304; the master control chip 30 is further configured to control an output terminal 502 of the voltage output module 50 to output a third voltage according to the second voltage through the plurality of control output terminals 303, the third voltage being matched with the external mainboard; the output terminal 502 of the voltage output module 50 is electrically connected to the first voltage input terminal 601; in the level shift module 60, the third signal terminals 603 are electrically connected to the connection ends of the first connector 10 corresponding to the third signal terminals 603; and the level shift module 60 is configured to set the voltage of the signal input by the first signal terminals 304 to the third voltage and output through the third signal terminals 603 corresponding to the first signal terminals 304.

[0062] In some embodiments, the debugger further comprises a plurality of internal connection ports 111, the third signal terminals 603 correspond to the internal connection ports 111 one by one, and the internal connection ports 111 have corresponding connection ends of the first connector 10; in the level shift module 60, the third signal terminals 603 are electrically connected to the internal connection ports 111 corresponding to the third signal terminals 603, and the internal connection ports 111 are electrically connected to the connection ends of the first connector 10 corresponding to the internal connection ports 111.

[0063] In some embodiments, the third voltage is equal to the voltage of the third power supply.

[0064] In some embodiments, the master control chip 30 further comprises 6 first signal terminals 304; the level transfer module 60 comprises a first voltage input terminal 601, 6 second signal terminals 602 and 6 third signal terminals 603, the first signal terminal 304 corresponds to the second signal terminal 602 one by one, and the second signal terminal 602 corresponds to the third signal terminal 603 one by one; the level transfer module 60 is a bidirectional voltage level converter chip, and the level transfer module 60 further comprises a second voltage input terminal 604, a third enable terminal 605 and a first ground terminal 606; the debugger further comprises a first capacitor C1, a second capacitor C2, a tenth resistor R10 and 6 internal connection ports 111, the third signal terminal 603 corresponds to the internal connection port 111 one by one, and the internal connection port 111 has a connecting end of the corresponding first connector 10; the second voltage input terminal 604 is used for electrical connection with the fifth power supply; a first end of the first capacitor C1 is electrically connected with the first voltage input terminal 601, and a second end of the first capacitor C1 is grounded; a first end of the second capacitor C2 is electrically connected with the second voltage input terminal 604, and a second end of the second capacitor C2 is grounded; a first end of the tenth resistor R10 is electrically connected with the output terminal 513 of the voltage output sub-module 51, and a second end of the tenth resistor R10 is electrically connected with the third enable terminal 605; the first signal terminal 304 is electrically connected with the second signal terminal 602 corresponding to the first signal terminal 304; the third signal terminal 603 is electrically connected with the internal connection port 111 corresponding to the third signal terminal 603, and the internal connection port 111 is electrically connected with the connecting end of the first connector 10 corresponding to the internal connection port 111; wherein the first capacitor C1 and the second capacitor C2 are filter capacitors, and the tenth resistor R10 is a current limiting resistor.

[0065] In the embodiment of the utility model, through the master control chip 30 according to second voltage, through multiple control output terminals 303 control voltage output module 50's output terminal 502 output third voltage, wherein, third voltage is matched with external mainboard, then through level transfer module 60, the voltage of the signal of first signal terminal 304 input is set to third voltage, and is exported through the third signal terminal 603 corresponding to the first signal terminal 304, then the voltage of the signal of the connecting end of first connector 10 exported to external mainboard is third voltage, so that the voltage of the signal of the connecting end of first connector 10 exported to external mainboard is matched with external mainboard.

[0066] Optionally, referring to Figure 4In some embodiments, the voltage output module 50 comprises a plurality of switch devices Q1 and a voltage output submodule 51, the voltage output submodule 51 comprises a plurality of voltage setting ends 511, the switch devices Q1 correspond to the voltage setting ends 511 one by one, and the switch devices Q1 correspond to the control output ends 303 one by one; the control end of the switch device Q1 is electrically connected with the control output end 303 corresponding to the switch device Q1, the first end of the switch device Q1 is electrically connected with the voltage setting end 511 corresponding to the switch device Q1, and the second end of the switch device Q1 is grounded; and the output end 513 of the voltage output submodule 51 is electrically connected with the first voltage input end 601.

[0067] It should be noted that each voltage setting end 511 has a corresponding preset voltage value; the sum of the corresponding preset voltage value of each grounded voltage setting end 511 and the preset basic voltage value is the voltage value output by the voltage output submodule 51, for example, the preset basic voltage value is 0.8 volts, the voltage output submodule 51 comprises four voltage setting ends 511, the corresponding preset voltage value of the first voltage setting end 511 is 1.6 volts, the corresponding preset voltage value of the second voltage setting end 511 is 800 millivolts, the corresponding preset voltage value of the third voltage setting end 511 is 400 millivolts, and the corresponding preset voltage value of the fourth voltage setting end 511 is 200 millivolts; in the case that the first voltage setting end 511 is grounded and the fourth voltage setting end 511 is grounded, the voltage value output by the voltage output submodule 51 is 2.6 volts.

[0068] In the embodiment of the utility model, through the control output end 303 of the main control chip 30, the conduction and disconnection of the switch device Q1 corresponding to the control output end 303 can be controlled, in the case that the switch device Q1 is conducted, the voltage setting end 511 corresponding to the switch device Q1 is grounded; in the case that the switch device Q1 is disconnected, the voltage setting end 511 corresponding to the switch device Q1 is vacant.

[0069] Optionally, in some embodiments, the voltage output module 50 further comprises a sixth resistor R6; the voltage output submodule 51 further comprises a first enable end 512; the main control chip 30 further comprises an enable control end 305; the first end of the sixth resistor R6 is electrically connected with the enable control end 305, and the second end of the sixth resistor R6 is electrically connected with the first enable end 512.

[0070] It should be noted that the first end of the sixth resistor R6 is the second enable end 503 of the voltage output module 50.

[0071] In the embodiment of the utility model, through the enable control end 305 of the main control chip 30, the opening and closing of the voltage output submodule 51 can be controlled.

[0072] Optionally, in some embodiments, the type of the switching device Q1 includes MOS tube and triode.

[0073] It should be noted that the MOS tube is a Metal-Oxide-Semiconductor Field-Effect Transistor.

[0074] Specifically, in some embodiments, the switching device Q1 is an NMOS tube or an NPN triode, wherein the NMOS tube is a Negative channel-Metal-Oxide-Semiconductor, and the NPN triode is composed of three semiconductor blocks, including two N (Negative Electricity) type semiconductor blocks (electron type semiconductor) and one P (Positive Electricity) type semiconductor block (hole type semiconductor), with the P type semiconductor in the middle and the two N type semiconductors on both sides.

[0075] In the embodiment of the utility model, the switching device Q1 is an NMOS tube or an NPN triode, and the switching device Q1 corresponding to the control output end 303 is turned on when the control output end 303 of the master control chip 30 is at a high level, and the switching device Q1 corresponding to the control output end 303 is turned off when the control output end 303 of the master control chip 30 is at a low level.

[0076] Optionally, in some embodiments, the voltage output sub-module 51 is a low dropout linear regulator.

[0077] In some embodiments, the voltage output sub-module 51 further includes a power good indication end 515, a bias supply voltage end 516, a feedback voltage end 517, an output voltage sensing end 518, a soft start end 519, a pad end 521, two second ground ends 520, and three input ends 514 of the voltage output sub-module 51, and the number of output ends 513 of the voltage output sub-module 51 is three; the voltage output module 50 further includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a third capacitor C3, three fourth capacitors C4, three fifth capacitors C5, a sixth capacitor C6, and a seventh capacitor C7; the input end 514 of each voltage output sub-module 51 is electrically connected to the sixth power supply; the first end of the seventh resistor R7 is electrically connected to the second end of the sixth resistor R6 and the first enable end 512, and the second end of the seventh resistor R7 is grounded; the first end of the eighth resistor R8 is electrically connected to the sixth power supply, and the second end of the eighth resistor R8 is electrically connected to the power good indication end 515;

[0078] A first end of a ninth resistor R9 is electrically connected with an output end 513 of each voltage output sub-module 51, and a second end of the ninth resistor R9 is electrically connected with an output voltage sensing end 518; a first end of a third capacitor C3 is electrically connected with a bias supply voltage end 516, and a second end of the third capacitor C3 is grounded; a first end of each fourth capacitor C4 is electrically connected with a sixth power supply, and a second end of each fourth capacitor C4 is grounded; a first end of a fifth capacitor C5 is electrically connected with the output end 513 of the voltage output sub-module 51, and a second end of the fifth capacitor C5 is grounded; a first end of a sixth capacitor C6 is electrically connected with the output end 513 of the voltage output sub-module 51, and a second end of the sixth capacitor C6 is electrically connected with a feedback voltage end 517; a first end of a seventh capacitor C7 is electrically connected with a soft start end 519, and a second end of the seventh capacitor C7 is grounded; each second ground end 520 and pad end 521 are grounded; wherein the seventh resistor R7 is a pull-down resistor, the eighth resistor R8 is a pull-up resistor, the ninth resistor R9 is a current limiting resistor, each fourth capacitor C4, each fifth capacitor C5 and the sixth capacitor C6 are filter capacitors, the seventh capacitor C7 is a slow start capacitor, and the third capacitor C3 is a bias capacitor.

[0079] In the embodiment of the utility model, voltage output sub-module 51 is low dropout linear regulator, through multiple control output ends 303 of main control chip 30, can set the output voltage of voltage output sub-module 51.

[0080] Optionally, in some embodiments, the debugger further comprises a plurality of electrostatic discharge protectors D1, each of the third signal terminals 603 corresponding to the connection end of the first connector 10 has a corresponding electrostatic discharge protector D1; the first end of the electrostatic discharge protector D1 is electrically connected with the connection end of the first connector 10 corresponding to the electrostatic discharge protector D1, and the second end of the electrostatic discharge protector D1 is grounded.

[0081] In the embodiment of the utility model, through electrostatic discharge protector D1, the connection end of first connector 10 is protected from electrostatic discharge, and the signal transmission quality of the first connector 10 is improved.

[0082] In some embodiments, the debugger further comprises 3 second acquisition modules 40, 6 electrostatic discharge protectors D1, an eighth capacitor C8 and 6 internal connection ports 111; the number of connection ends of the first connector 10 is 8, the connection ends of the first connector 10 include a first connection end 101, 3 third connection ends 102 and 4 fifth connection ends 103, the first connection end 101 is the TRST end of the first connector 10, that is, the test reset input signal end of the first connector 10; the first third connection end 102 is the TCK end of the first connector 10, that is, the test clock input end of the first connector 10; the second third connection end 102 is the TDO end of the first connector 10, that is, the test data output end of the first connector 10; the third third connection end 102 is the VCC end of the first connector 10, that is, the connection power input end of the first connector 10; the first fifth connection end 103 is the TMS end of the first connector 10, that is, the test mode selection input end of the first connector 10; the second fifth connection end 103 is the TDI end of the first connector 10, that is, the test data input end of the first connector 10; the third fifth connection end 103 is the DEST end of the first connector 10, that is, the other connection end of the first connector 10; the fourth fifth connection end 103 is the GND end of the first connector 10, that is, the ground end of the first connector 10;

[0083] The first connection end 101 is electrically connected with the second end of the first resistor R1, the first end of the second resistor R2, the first end of the first electrostatic discharge protector D1 and the first internal connection port 111 respectively; the first third connection end 102 is electrically connected with the second internal connection port 111, the input end 401 of the first second acquisition module 40 and the first end of the first electrostatic discharge protector D1 respectively; the second third connection end 102 is electrically connected with the third internal connection port 111, the input end 401 of the second second acquisition module 40 and the first end of the third electrostatic discharge protector D1 respectively; the third third connection end 102 is electrically connected with the first end of the eighth capacitor C8 and the input end 401 of the third second acquisition module 40 respectively, the second end of the eighth capacitor C8 is grounded, and the eighth capacitor C8 is a filter capacitor;

[0084] The first fifth connecting end 103 is electrically connected with the fourth internal connecting port 111 and the first end of the fourth electrostatic discharge protector D1 respectively; the second fifth connecting end 103 is electrically connected with the fifth internal connecting port 111 and the first end of the fifth electrostatic discharge protector D1 respectively; the third fifth connecting end 103 is electrically connected with the sixth internal connecting port 111 and the first end of the sixth electrostatic discharge protector D1 respectively; the fourth fifth connecting end 103 is grounded.

[0085] Referring to Figure 5 In some embodiments, the second connector is a 2*7 connector, the connecting ends of the second connector are arranged in a matrix form, the matrix includes 7 rows and 2 columns, that is, each column includes 7 connecting ends of the second connector, the first column includes the connecting end A1, the connecting end A2, the connecting end A3, the connecting end A4, the connecting end A5, the connecting end A6 and the connecting end A7, and the second column includes the connecting end A8, the connecting end A9, the connecting end A10, the connecting end A11, the connecting end A12, the connecting end A13 and the connecting end A14, wherein the connecting end A1 is a second connecting end, the connecting end A1 is a TRST end of the second connector, and the TRST end of the second connector is a test reset input signal end of the second connector; the connecting end A2 is a TDI end of the second connector, the TDI end of the second connector is a test data input end of the second connector, and the connecting end A2 is used for being electrically connected with the second fifth connecting end 103; the connecting end A3 is a second fourth connecting end, the second fourth connecting end is a TDO end of the second connector, the TDO end of the second connector is a test data output end of the second connector, and the second fourth connecting end is used for being electrically connected with the second third connecting end 102; the connecting end A4 is a TMS end of the second connector, the TMS end of the second connector is a test mode selection input end of the second connector, and the connecting end A4 is used for being electrically connected with the first fifth connecting end 103;

[0086] The connecting end A5 is a first fourth connecting end, the connecting end A5 is a TCK end of the second connector, the TCK end of the second connector is a test clock input end of the second connector, and the first fourth connecting end is used for being electrically connected with the first third connecting end 102; the connecting end A6 is vacant; the connecting end A7 is a DEST end of the second connector, the DEST end of the second connector is an other connecting end of the second connector, and the connecting end A7 is used for being electrically connected with the third fifth connecting end 103; the connecting end A8, the connecting end A9, the connecting end A10, the connecting end A11 and the connecting end A12 are all GND ends of the second connector, the GND end of the second connector is a ground end of the second connector, and the ground end of the second connector is used for being grounded; the connecting end A13 is vacant; the connecting end A14 is a third fourth connecting end, the third fourth connecting end is a VCC end of the second connector, the VCC end of the second connector is a connection power input end of the second connector, and the third fourth connecting end is used for being electrically connected with the third third connecting end 102.

[0087] For example, in the case of the first connector 10 being connected to the second connector incorrectly, the connection end A1 is electrically connected to the third third connection end 102, and the connection end A14 is electrically connected to the first first connection end 101, that is, the first connector 10 is connected to the second connector in reverse, at this time, the first voltage corresponding to the first connection end 101 is:

[0088]

[0089] Therefore, it is determined that the first connector 10 is connected to the second connector incorrectly.

[0090] Referring to Figure 6 In some embodiments, the second connector is a 2 by 5 connector, and the connection ends of the second connector are arranged in a matrix form, the matrix including 5 rows and 2 columns, that is, each column includes 5 connection ends of the second connector, the first column includes the connection end B1, the connection end B2, the connection end B3, the connection end B4 and the connection end B5, and the second column includes the connection end B6, the connection end B7, the connection end B8, the connection end B9 and the connection end B10, wherein the connection end B1 is a second connection end, the connection end B1 is a TRST end of the second connector, and the TRST end of the second connector is a test reset input signal end of the second connector; the connection end B2 is a TDI end of the second connector, the TDI end of the second connector is a test data input end of the second connector, and the connection end B2 is used for electrical connection with the second fifth connection end 103; the connection end B3 is a second fourth connection end, the second fourth connection end is a TDO end of the second connector, the TDO end of the second connector is a test data output end of the second connector, and the second fourth connection end is used for electrical connection with the second third connection end 102; the connection end B4 is a TMS end of the second connector, the TMS end of the second connector is a test mode selection input end of the second connector, and the connection end B4 is used for electrical connection with the first fifth connection end 103; the connection end B5 is a first fourth connection end, the connection end B5 is a TCK end of the second connector, the TCK end of the second connector is a test clock input end of the second connector, and the first fourth connection end is used for electrical connection with the first third connection end 102; the connection end B6, the connection end B7, the connection end B8, the connection end B9 and the connection end B10 are all GND ends of the second connector, the GND end of the second connector is a ground end of the second connector, and the ground end of the second connector is used for grounding.

[0091] For example, other values than the first preset value and the second preset value are 0 volts, in the case that the first connector 10 is connected to the second connector incorrectly, the connection end B 10 is electrically connected to the first connection end 101, that is, the first connector 10 is connected to the second connector reversely, at this time, the first connection end 101 is grounded, and the first voltage corresponding to the first connection end 101 is 0 volts, therefore, in the case that the first voltage is 0 volts, it is determined that the first connector 10 is connected to the second connector incorrectly.

[0092] With reference to Figure 7 In some embodiments, the second connector is a 2*4 connector, the connection ends of the second connector are arranged in a matrix form, the matrix includes 4 rows and 2 columns, each column includes 4 connection ends of the second connector, the first column includes the connection end E1, the connection end E2, the connection end E3 and the connection end E4, and the second column includes the connection end E5, the connection end E6, the connection end E7 and the connection end E8, wherein the connection end E1 is a second connection end, the connection end E1 is a TRST end of the second connector, and the TRST end of the second connector is a test reset input signal end of the second connector; the connection end E2 is a TDI end of the second connector, the TDI end of the second connector is a test data input end of the second connector, and the connection end E2 is used for electrical connection with the second fifth connection end 103; the connection end E3 is a second fourth connection end, the second fourth connection end is a TDO end of the second connector, the TDO end of the second connector is a test data output end of the second connector, and the second fourth connection end is used for electrical connection with the second third connection end 102; the connection end E4 is a TMS end of the second connector, the TMS end of the second connector is a test mode selection input end of the second connector, and the connection end E4 is used for electrical connection with the first fifth connection end 103.

[0093] The connection end E5 is a third fourth connection end, the third fourth connection end is a VCC end of the second connector, the VCC end of the second connector is a connection power input end of the second connector, and the third fourth connection end is used for electrical connection with the third third connection end 102; the connection end E6 is a first fourth connection end, the connection end E5 is a TCK end of the second connector, the TCK end of the second connector is a test clock input end of the second connector, and the first fourth connection end is used for electrical connection with the first third connection end 102; the connection end E7 is a DEST end of the second connector, the DEST end of the second connector is another connection end of the second connector, and the connection end E7 is used for electrical connection with the third fifth connection end 103; and the connection end E8 is a GND end of the second connector, the GND end of the second connector is a grounding end of the second connector, and the grounding end of the second connector is used for grounding.

[0094] For example, in the case that the first connector 10 is connected to the second connector incorrectly, the connection end E8 is electrically connected to the first connection end 101, that is, the first connector 10 is reversely connected to the second connector, at this time, the first connection end 101 is grounded, and the first voltage corresponding to the first connection end 101 is 0 volt, therefore, in the case that the first voltage is 0 volt, it is determined that the first connector 10 is connected to the second connector incorrectly.

[0095] In some embodiments, the detection process of the debugger includes: X1, starting; X2, powering on the debugger, that is, the debugger is powered on to work, wherein the debugger is electrically connected to the host computer; X3, judging whether the mainboard is in place or whether the mainboard is powered on, that is, judging whether the first connector 10 is empty or whether the external mainboard is powered on; X4, judging whether the mainboard is reversely connected, that is, judging whether the first connector 10 is connected to the second connector incorrectly; X5, acquiring the second voltage, that is, the second acquisition module 40 corresponding to the third connection end 102 is used to acquire the second voltage corresponding to the third connection end 102; X6, outputting the third voltage, that is, the host chip 30 acquires the third voltage according to the second voltage, and controls the output end 502 of the voltage output module 50 to output the third voltage through the plurality of control output ends 303; X7, loading the configuration file, that is, the debugger reads the identity recognition code (ID, Identity document) of the chip on the mainboard, and loads the configuration file of the chip on the mainboard according to the identity recognition code of the chip on the mainboard; X8, entering the debugging state, that is, the debugger enters the debugging state; X9, whether hot plug occurs, that is, judging whether the first connector 10 and the second connector occur hot plug, the host chip 30 acquires the first voltage every preset time, in the case that the first voltage remains the second preset value, it is determined that the first connector 10 and the second connector do not occur hot plug, in the case that the first voltage changes from the second preset value to the first preset value, it is determined that the first connector 10 and the second connector occur hot plug; X10, the debugging is completed and the debugger is in an idle state, that is, the debugger completes the debugging of the external mainboard, and the debugger is in the idle state; X11, whether hot plug occurs, that is, judging whether the first connector 10 and the second connector occur hot plug; X12, the terminal displays that the mainboard is not powered on or not in place, that is, the terminal of the host computer displays that the mainboard is not powered on or not in place; X13, the terminal displays that the mainboard is reversely connected, please re-plug, that is, the terminal of the host computer displays that the mainboard is reversely connected, please re-plug; X14, ending.

[0096] In the related art, the connection of the connector of the debugger and the connector of the mainboard is avoided to be incorrect by using the foolproof connector, however, when the connector of the mainboard does not use the foolproof connector, the connection of the connector of the debugger and the connector of the mainboard cannot be avoided to be incorrect, and the user matches the level of the connector of the debugger and the mainboard in an artificial way, which causes the user to debug complicatedly.

[0097] The embodiment of the utility model can realize the functions of level self -adaptation, anti -reversing, hot plug detection, automatic loading of the configuration file of the chip on the mainboard of the input and output of the debugger, adapt to different mainboards and connectors of the mainboard, improve the flexibility and safety of the debugger, simplify the debugging process and improve the debugging efficiency; through displaying the power -on or in -position state of the mainboard and connection error information, the user can conveniently troubleshoot and optimize debugging.

[0098] To sum up, in the embodiment of the utility model, through the first acquisition module 20 gathers the first voltage corresponding to the first connecting end 101 of the first connector 10, then through the main control chip 30, in the case that the first voltage is the first preset value, it is determined that the first connector 10 is vacant, and in the case that the first voltage is the second preset value, it is determined that the first connector 10 is connected correctly with the second connector of the external mainboard, and in the case that the first voltage is other values except the first preset value and the second preset value, it is determined that the first connector 10 is connected incorrectly with the second connector, so that the staff can know that the first connector 10 is connected incorrectly with the second connector of the external mainboard in time, and then the first connector 10 is reconnected with the second connector, and in the case that the first connector 10 is connected correctly with the second connector, the debugger is used to debug the external mainboard, and the success rate of debugging is improved.

[0099] Finally, it also needs to be explained that in this paper, relationship terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between the entities or operations. Moreover, the term "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or terminal device.

[0100] The above is only the preferred embodiment of the utility model, and does not limit the utility model, and any modification, equivalent replacement and improvement made within the spirit and principle of the utility model should be included in the protection scope of the utility model.

[0101] The above is only the specific implementation of the utility model, but the protection scope of the utility model is not limited to this, and any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be subject to the protection scope of the claims.

Claims

1. A debugger, characterized by The device comprises a main control chip (30), a first connector (10) and a first acquisition module (20). The first connector (10) comprises a first connecting end (101) which is electrically connected with an input end (201) of the first acquisition module (20); the first connector (10) is used for being electrically connected with a second connector of an external mainboard; the second connector comprises a second connecting end, and the first connecting end (101) is used for being electrically connected with the second connecting end; An output end (202) of the first acquisition module (20) is electrically connected with a first acquisition end (301) of the main control chip (30), and the first acquisition module (20) is used for acquiring a first voltage corresponding to the first connecting end (101); The main control chip (30) is used for determining that the first connector (10) is vacant when the first voltage is a first preset value, determining that the first connector (10) is correctly connected with the second connector when the first voltage is a second preset value, and determining that the first connector (10) is incorrectly connected with the second connector when the first voltage is a value other than the first preset value and the second preset value. The first acquisition module (20) comprises a first resistor (R1), a second resistor (R2) and a third resistor (R3); 2. The debugger of claim 1, wherein, A first end of the first resistor (R1) is used for being electrically connected with a first power supply, and a second end of the first resistor (R1) is electrically connected with a first end of the second resistor (R2) and the first connecting end (101) respectively; A first end of the second resistor (R2) is electrically connected with the first connecting end (101), and a second end of the second resistor (R2) is electrically connected with a first end of the main control chip (30) and a first end of the third resistor (R3) respectively; A second end of the third resistor (R3) is grounded. The debugger further comprises a plurality of second acquisition modules (40), the first connector (10) comprises a plurality of third connecting ends (102), the third connecting ends (102) correspond to the second acquisition modules (40) one by one; the main control chip (30) further comprises a plurality of second acquisition ends (302), the second acquisition modules (40) correspond to the second acquisition ends (302) one by one; the second connector comprises a plurality of fourth connecting ends, and at least part of the third connecting ends (102) have corresponding fourth connecting ends; 3. The debugger of claim 1, wherein, The third connecting end (102) is electrically connected with an input end (401) of the second acquisition module (40) corresponding to the third connecting end (102); the third connecting end (102) is used for being electrically connected with a fourth connecting end corresponding to the third connecting end (102); An output end (402) of the second acquisition module (40) is electrically connected with a second acquisition end (302) corresponding to the second acquisition module (40), and the second acquisition module (40) corresponding to the third connecting end (102) is used for acquiring a second voltage corresponding to the third connecting end (102). ​ The master chip (30) is specifically configured to determine that the first connector (10) is empty or the external mainboard is not powered on when each of the second voltages is a third preset value, and determine that the debugger is in communication with the external mainboard and the external mainboard is powered on when at least one of the second voltages is greater than the third preset value.

4. The debugger of claim 3, wherein, Each of the second acquisition modules (40) comprises a fourth resistor (R4) and a fifth resistor (R5); In the second acquisition module (40), the first end of the fourth resistor (R4) is electrically connected with the third connection end (102) corresponding to the second acquisition module (40), the second end of the fourth resistor (R4) is electrically connected with the second acquisition end (302) corresponding to the second acquisition module (40) and the first end of the fifth resistor (R5) respectively; the first end of the fifth resistor (R5) is electrically connected with the second acquisition end (302) corresponding to the second acquisition module (40), and the second end of the fifth resistor (R5) is grounded.

5. The debugger of claim 3, wherein, The debugger further comprises a voltage output module (50) and a level transfer module (60); the voltage output module (50) comprises a plurality of control input ends (501); the master chip (30) further comprises a plurality of control output ends (303) and a plurality of first signal ends (304), the control output ends (303) correspond to the control input ends (501) one by one; the level transfer module (60) comprises a first voltage input end (601), a plurality of second signal ends (602) and a plurality of third signal ends (603), the first signal ends (304) correspond to the second signal ends (602) one by one, and the second signal ends (602) correspond to the third signal ends (603) one by one; the connection end of the first connector (10) is a plurality of, and the third signal end (603) has a corresponding connection end of the first connector (10); In the master chip (30), the control output ends (303) are electrically connected with the control input ends (501) corresponding to the control output ends (303), and the first signal ends (304) are electrically connected with the second signal ends (602) corresponding to the first signal ends (304); the master chip (30) is further configured to control the output end (502) of the voltage output module (50) to output a third voltage through the plurality of control output ends (303) according to the second voltage, and the third voltage matches the external mainboard; The output end (502) of the voltage output module (50) is electrically connected with the first voltage input end (601); In the level transfer module (60), the third signal ends (603) are electrically connected with the connection ends of the first connectors (10) corresponding to the third signal ends (603); the level transfer module (60) is configured to set the voltage of the signal input by the first signal ends (304) as the third voltage, and output the signal through the third signal ends (603) corresponding to the first signal ends (304).

6. The debugger of claim 5, wherein, The voltage output module (50) comprises a plurality of switch devices (Q1) and a voltage output submodule (51), the voltage output submodule (51) comprises a plurality of voltage setting ends (511), the switch device (Q1) corresponds to the voltage setting end (511) one by one, and the switch device (Q1) corresponds to the control output end (303) one by one. The control end of the switch device (Q1) is electrically connected with the control output end (303) corresponding to the switch device (Q1), the first end of the switch device (Q1) is electrically connected with the voltage setting end (511) corresponding to the switch device (Q1), and the second end of the switch device (Q1) is grounded. The output end (513) of the voltage output submodule (51) is electrically connected with the first voltage input end (601).

7. The debugger of claim 6, wherein, The voltage output module (50) further comprises a sixth resistor (R6), the voltage output submodule (51) further comprises a first enable end (512), and the master control chip (30) further comprises an enable control end (305). The first end of the sixth resistor (R6) is electrically connected with the enable control end (305), and the second end of the sixth resistor (R6) is electrically connected with the first enable end (512).

8. The debugger of claim 6, wherein, The type of the switch device (Q1) comprises a MOS tube and a triode.

9. The debugger of claim 6, wherein, The voltage output submodule (51) is a low dropout linear regulator.

10. The debugger of claim 5, wherein, The debugger further comprises a plurality of electrostatic discharge protectors (D1), and the connection end of the first connector (10) corresponding to each third signal end (603) is provided with a corresponding electrostatic discharge protector (D1). The first end of the electrostatic discharge protector (D1) is electrically connected with the connection end of the first connector (10) corresponding to the electrostatic discharge protector (D1), and the second end of the electrostatic discharge protector (D1) is grounded.

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