Analog-to-digital converter, signal processing circuit, chip and electronic device

Abstract

The embodiment of the utility model provides an analog-to-digital converter, a signal processing circuit, a chip and electronic equipment, the analog-to-digital converter comprises an integration module, a quantization module and an isolation module, the integration module outputs an integration voltage according to a conversion digital signal, an input voltage and a first reference voltage of a previous measurement period in each measurement period; the quantization module outputs a conversion digital signal of the current measurement period according to the integral voltage, the input voltage and the second reference voltage in each measurement period; wherein an isolation module is arranged between the quantization module and the voltage input end. The quantization module and the pre-stage circuit connected to the voltage input end are isolated through the isolation module, and the problem that the power consumption of the pre-stage circuit is increased due to the fact that the load capacitance of the pre-stage circuit is increased due to the capacitance in the quantization module can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to an analog-to-digital converter, a signal processing circuit, a chip and an electronic device. BACKGROUND

[0002] At present, analog-to-digital converters can be divided into Nyquist analog-to-digital converters and oversampling analog-to-digital converters according to sampling rates, wherein the Nyquist analog-to-digital converters mainly include Flash analog-to-digital converters (Flash ADCs), successive approximation register analog-to-digital converters (SAR ADCs) and pipeline analog-to-digital converters, and the oversampling analog-to-digital converters mainly include Sigma-delta analog-to-digital converters (Sigma-delta ADCs). The incremental Sigma-delta ADC is a new type of analog-to-digital converter, which is improved on the basis of the traditional Sigma-delta ADC. It inherits all the advantages of the traditional Sigma-delta ADC and adopts the working mode of the Nyquist analog-to-digital converter, so it can have the advantages of both the Nyquist analog-to-digital converter and the oversampling analog-to-digital converter.

[0003] In related technologies, the incremental Sigma-delta ADC usually adopts a Cascade of Intergrators Feed Forward (CIFF) structure. In the CIFF structure, there is an input feedforward path connecting a front-stage circuit (such as a signal amplification circuit) and a quantizer. The connection of the capacitor in the quantizer and the front-stage circuit will cause the problem of increased load capacitance of the front-stage circuit. In order to ensure the Gain Bandwidth Product (GBW) of the operational amplifier circuit, it is usually necessary to increase the power consumption to meet the system establishment requirements, which leads to the problem of increased power consumption of the front-stage circuit of the existing CIFF structure type analog-to-digital converter. CONTENT OF THE UTILITY MODEL

[0004] In view of the above problems, the embodiments of the present application provide an analog-to-digital converter, a signal processing circuit, a chip and an electronic device to solve the above technical problems.

[0005] In a first aspect, the embodiments of the present application provide an analog-to-digital converter, comprising:

[0006] an integration module, the integration module being connected with a voltage input end for providing an input voltage, and the voltage input end being connected with a front-stage circuit;

[0007] a quantization module, the quantization module being connected with the integration module and the voltage input end;

[0008] The isolation module is arranged between the quantization module and the voltage input end, so as to isolate the front-stage circuit connected to the voltage input end and the quantization module.

[0009] In a second aspect, an embodiment of the present application provides a signal processing circuit, comprising:

[0010] The signal amplification circuit is connected to the to-be-converted signal, so as to amplify the to-be-converted signal and output the amplified input signal.

[0011] The analog-to-digital converter is connected to the signal amplification circuit, so as to perform analog-to-digital conversion on the input signal and output the converted digital signal.

[0012] In a third aspect, an embodiment of the present application further provides a chip, comprising the analog-to-digital converter.

[0013] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising the chip or the analog-to-digital converter.

[0014] The integral module outputs the integral voltage according to the converted digital signal of the last measurement period, the input voltage and the first reference voltage in each measurement period, and the quantization module outputs the converted digital signal of the current measurement period according to the integral voltage, the input voltage and the second reference voltage in each measurement period, so that the analog-to-digital conversion process of the digital signal converted from the input signal can be realized. Since the isolation module is arranged between the quantization module and the voltage input end, the capacitor in the quantization module and the front-stage circuit connected to the voltage input end can be isolated through the isolation module, so that the problem that the load capacitance of the front-stage circuit increases due to the capacitor in the quantization module, and the power consumption of the front-stage circuit of the integrator cascade feedforward structure type analog-to-digital converter increases, can be avoided.

[0015] These and other aspects of the present application will become more apparent from the following description of some embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0017] Figure 1 A schematic diagram of a Sigma-delta ADC in the related art is shown.

[0018] Figure 2 A schematic diagram of a CIFF Sigma-delta ADC in the related art is shown.

[0019] Figure 3 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0020] Figure 4 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0021] Figure 5 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0022] Figure 6 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0023] Figure 7 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0024] Figure 8 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0025] Figure 9 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0026] Figure 10 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0027] Figure 11 A schematic diagram of an analog-to-digital converter in an embodiment of the application is shown.

[0028] Figure 12 A schematic diagram of a signal processing circuit in an embodiment of the application is shown.

[0029] wherein, 1 a pre-stage circuit, 100 an analog-to-digital converter, 101 a voltage input end, 102 a first reference end, 103 a second reference end, 10 an integration module, 11 a sampling unit, 12 a feedback unit, 13 an integrator, 20 a quantization module, 21 an analog operation unit, 22 a comparator, 30 an isolation module;

[0030] an input voltage VI, a first reference voltage Vref1, a second reference voltage Vref2, an integration voltage VO, a first voltage signal V01, a converted digital signal Dout, a sampling charge signal QS, a feedback charge signal QR, a common-mode voltage VCM;

[0031] a sampling capacitor CS, a feedback capacitor CF, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6;

[0032] A first operational amplifier OP1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first total switch S0, a first sub-switch S01, a second sub-switch S02, a third sub-switch S03, a fourth sub-switch S04, a fifth sub-switch S05, a sixth sub-switch S06, and a seventh sub-switch S07. DETAILED DESCRIPTION

[0033] Embodiments of the present application are described below in detail with reference to the accompanying drawings, in which like or similar elements are denoted by the same or similar reference numerals, and of which examples are shown in the drawings. The embodiments described below are exemplary only, and are not intended to limit the present application.

[0034] In order to make the persons skilled in the art better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, and cannot be understood as limiting the present application.

[0035] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between or among the entities or actions.

[0036] Moreover, the terms "comprising", "comprises", "including", "includes" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article or apparatus that comprises the element.

[0037] In the description of the embodiments of the present application, the words "example" or "for example" are used to mean "an example of" or "for example". Any embodiment or design scheme described as "example" or "for example" in the embodiments of the present application is not interpreted as being more preferred or having more advantages than another embodiment or design scheme. The words "example" or "for example" are intended to present a relative concept in a clear manner.

[0038] In addition, "multiple" in the embodiments of the present application refers to two or more, and therefore, "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, "including at least one" means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C means that A, B, C, A and B, A and C, B and C, or A and B and C can be included.

[0039] It should be noted that "connection" in the embodiments of the present application can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0040] At present, oversampling analog-to-digital converters are mainly Sigma-delta ADCs, refer to Figure 1 , Figure 1 A schematic diagram of a Sigma-delta ADC in the related art is shown, wherein a pre-amplification circuit specifically amplifies a sensor signal, thereby providing an input voltage signal Vin to a Sigma-delta analog-to-digital converter, the Sigma-delta ADC mainly includes a sampling circuit, a feedback circuit, an integrator and a quantizer, the sampling circuit can sample the input voltage signal Vin and output an input charge signal VinxC, the feedback circuit can output a corresponding feedback charge signal VdacxC according to a reference voltage signal Vdac, the integrator can charge integrate the input charge signal VinxC and the feedback charge signal VdacxC, and the quantizer can compare a reference voltage VR with an output voltage of the integrator, thereby outputting a digital signal.

[0041] In each measurement period of the Sigma-delta ADC, the output result of the quantizer can control the positive and negative of the feedback charge signal VdacxC, so that the output result of the integrator is always near the reference voltage VR in multiple measurement periods. For example, in a measurement period, when the output voltage of the integrator is greater than the reference voltage VR, the quantizer controls the feedback circuit to output a positive feedback charge signal +VdacxC in the next measurement period, so that the output voltage of the integrator decreases; on the contrary, in a measurement period, when the output voltage of the integrator is less than the reference voltage VR, the quantizer controls the feedback circuit to output a negative feedback charge signal -VdacxC in the next measurement period, so that the output voltage of the integrator increases.

[0042] Since the output result of the integrator is negligible around the reference voltage VR in multiple measurement periods, the number of times of the input voltage signal V0, the reference voltage signal Vdac, the feedback positive charge signal +VdacxC, and the feedback negative charge signal -VdacxC satisfy the following relationship:

[0043] VinxC(X1+X2)=(VdacxCX1)-(VdacxCX2)

[0044] where C is a unit capacitance, X1 is the number of times of the feedback positive charge signal +VdacxC, and X2 is the number of times of the feedback negative charge signal -VdacxC.

[0045] Therefore, the input voltage signal Vin can be calculated as follows:

[0046]

[0047] It can be seen that the quantizer outputs a code value (for example, 011100..1100) in multiple measurement periods, where 1 represents the number of times of the feedback positive charge signal +VdacxC, and 0 represents the number of times of the feedback negative charge signal -VdacxC, and thus a digital signal corresponding to the input voltage signal Vin can be finally obtained according to the signal output by the quantizer.

[0048] In the related art, a Sigma-delta ADC can adopt an integrator cascade feed forward (CIFF) structure, refer to Figure 2 , Figure 2 FIG. 1 shows a schematic diagram of a CIFF Sigma-delta ADC in the related art. Compared with a traditional Sigma-delta ADC, the CIFF Sigma-delta ADC has an input feed forward path connecting a pre-stage amplification circuit and a quantizer, and thus in the CIFF Sigma-delta ADC, the pre-stage amplification circuit is connected to not only a capacitor in a sampling circuit but also a capacitor C0 in the quantizer, which causes a problem of an increased load capacitance of the pre-stage amplification circuit. In order to ensure a gain-bandwidth product of the pre-stage amplification circuit, it is usually necessary to increase power consumption to meet system establishment requirements, which finally causes a problem of increased power consumption of a pre-stage circuit of an existing integrator cascade feed forward structure type analog-to-digital converter.

[0049] To this end, the present application provides an analog-to-digital converter, a signal processing circuit, a chip, and an electronic device, which are described in detail below.

[0050] First, refer to Figure 3 , Figure 3Fig. 1 shows a schematic diagram of an analog-to-digital converter 100 according to an embodiment of the present application, wherein the analog-to-digital converter 100 comprises an integrating module 10, a quantizing module 20 and an isolating module 30.

[0051] In particular, the integrating module 10 is connected with a voltage input terminal 101 for providing an input voltage VI, and generally, the integrating module 10 is also connected with a first reference terminal 102 for providing a first reference voltage Vrefi, so as to output an integrating voltage VO according to a converted digital signal Dout of a last measurement period, the input voltage VI and the first reference voltage Vrefi in each measurement period. For example, the integrating module 10 can sample the input voltage VI in each measurement period, and the integrating module 10 can feedback according to the converted digital signal Dout of the last measurement period and the first reference voltage Vrefi in each measurement period, so that after integrating the sampled charge signal and the feedback charge signal, the integrating voltage VO of the current measurement period can be outputted.

[0052] It should be noted that the voltage input terminal 101 is connected with a pre-stage circuit 1, which can include but is not limited to a PGA amplifier or a TIA amplifier, so as to amplify and output the input voltage VI by amplifying the weak signal outputted by a sensor through the amplifying circuit, thereby improving the signal-to-noise ratio of the signal.

[0053] In some embodiments of the present application, referring to Figure 4 , Figure 4 Fig. 2 shows another schematic diagram of the analog-to-digital converter 100 according to an embodiment of the present application, wherein the integrating module 10 comprises a sampling unit 11, a feedback unit 12 and an integrator 13; the sampling unit 11 is connected with the voltage input terminal 101 and can sample and accumulate a sampling charge signal QS of the input voltage VI in a sampling stage of each measurement period, the feedback unit 12 is connected with the first reference terminal 102 for providing the first reference voltage Vrefi and can output a feedback charge signal QR according to the converted digital signal Dout of the last measurement period and the first reference voltage Vrefi in each measurement period, the integrator 13 is connected with the sampling unit 11 and the feedback unit 12, and the integrating module 10 can integrate and output the integrating voltage VO of the sampling charge signal QS and the feedback charge signal QR in a conversion stage of each measurement period.

[0054] As an example, referring to Figure 5 , Figure 5Another schematic diagram of the analog-to-digital converter 100 in the embodiment of the present application is shown, wherein the sampling unit 11 includes a first switch S1, a second switch S2, a sampling capacitor CS, a third switch S3 and a fourth switch S4. One end of the first switch S1 is connected to the voltage input end 101 to access the input voltage VI, and the other end of the first switch S1 is connected to a first plate of the sampling capacitor CS. One end of the second switch S2 is connected to the first plate of the sampling capacitor CS, and the other end of the second switch S2 is connected to the common-mode voltage VCM. One end of the third switch S3 is connected to a second plate of the sampling capacitor CS, and the other end of the third switch S3 is connected to the common-mode voltage VCM. One end of the fourth switch S4 is connected to the second plate of the sampling capacitor CS, and the other end of the fourth switch S4 is connected to a non-inverting input end of the operational amplifier OP0.

[0055] During the sampling phase of each measurement period, the first switch S1 and the third switch S3 are closed, and the second switch S2 and the fourth switch S4 are open. At this time, the amount of charge accumulated by the sampling capacitor CS is CS*(VI-VCM). During the conversion phase of each measurement period, the first switch S1 and the third switch S3 are open, and the second switch S2 and the fourth switch S4 are closed. Due to the virtual short and virtual open characteristics of the operational amplifier OP0, the voltage at the non-inverting input end of the operational amplifier is the common-mode voltage VCM. At this time, the amount of charge accumulated by the sampling capacitor CS is 0. Therefore, during the switching process of the above switches, the amount of charge of the sampling charge signal QS output by the sampling unit 11 to the integrator 13 is CS*(VI-VCM).

[0056] The feedback unit 12 includes a plurality of feedback capacitors CF, a plurality of fifth switches S5 and a plurality of sixth switches S6. The feedback capacitors CF, the fifth switches S5 and the sixth switches S6 are one-to-one corresponding. A first plate of each feedback capacitor CF is connected to the second plate of the sampling capacitor CS. One end of each fifth switch S5 is connected to the first reference end 102 to access the first reference voltage Vref1, and the other end of each fifth switch S5 is connected to a second plate of a corresponding feedback capacitor CF. One end of each sixth switch S6 is connected to the common-mode voltage VCM, and the other end of each sixth switch S6 is connected to the second plate of the corresponding feedback capacitor CF.

[0057] In the sampling phase of a measurement cycle, assuming N sixth switches S6 are closed and M fifth switches S5 are opened, and since the third switch S3 is closed, the amount of charge accumulated by all feedback capacitors CF is M*(Vref1-VCM)*CF; in the conversion phase of the measurement cycle, then corresponding M sixth switches S6 are opened and N fifth switches S5 are closed, and since the fourth switch S4 is closed, the amount of charge accumulated by all feedback capacitors CF is N*(Vref1-VCM)*CF, thus in the above switching process, the feedback unit 12 outputs a feedback charge signal QR to the integrator 13, and the amount of charge of the feedback charge signal QR is (N-M)*(Vref1-VCM)*CF.

[0058] The integrator 13 includes an operational amplifier OP0 and an integration capacitor CI, one end of the integration capacitor CI is connected to the non-inverting input terminal of the operational amplifier OP0, and the other end is connected to the output terminal of the operational amplifier OP0, the inverting input terminal of the operational amplifier OP0 is connected to the common-mode voltage VCM, the integration capacitor CI can integrate the charge input to the non-inverting input terminal of the operational amplifier OP0, the amount of charge of the sampling charge signal QS output by the sampling unit 11 to the integrator 13 in the above conversion phase is CS*(VI-VCM), and the amount of charge of the feedback charge signal QR output by the feedback unit 12 to the integrator 13 is (N-M)*(Vref1-VCM)*CF, for example, after the integration capacitor CI accumulates the sampling charge signal QS and the feedback charge signal QR, the output integration voltage VO satisfies the following formula:

[0059] VO=(CS*(VI-VCM)+(N-M)*(Vref1-VCM)*CF) / CI

[0060] As can be seen, after the integration capacitor CI accumulates the sampling charge signal QS and the feedback charge signal QR, the integrator 13 can output the integration voltage VO, so that the quantization module 20 outputs a conversion digital signal Dout according to the integration voltage VO.

[0061] It should be noted that the above content about the integration module 10 is only an exemplary embodiment of the present application, and those skilled in the art can make equivalent modifications and designs without departing from the basis of the present application, for example, those skilled in the art can modify the above single-ended integration module 10 circuit structure to a fully differential circuit structure, for example, refer to Figure 6 , Figure 6Another schematic diagram of the analog-to-digital converter 100 in the embodiments of the present application is shown, the input voltage VI includes differential signals Vip and Vin, the first reference voltage Vref1 includes differential signals Vref1n and Vref1p, the second reference voltage Vref2 includes differential signals Vref2p and Vref1n, and the integral voltage VO output by the integrator includes differential signals VOp and VOn. Meanwhile, the above-mentioned sampling unit 11, feedback unit 12 and integrator 13 are adaptively modified into a fully differential circuit structure.

[0062] The quantization module 20 is connected with the integral module 10, and the quantization module 20 is connected with the voltage input end 101 and the second reference end 103 providing the second reference voltage Vref2, so as to output the conversion digital signal Dout of the current measurement period according to the integral voltage VO, input voltage VI and second reference voltage Vref2 in each measurement period. Generally, the quantization module 20 can judge the size of the sum of two of the integral voltage VO, input voltage VI and second reference voltage Vref2 and the other one, and output the conversion digital signal Dout of the current measurement period according to the judgment result. For example, the quantization module 20 can judge the size of the sum of the integral voltage VO and input voltage VI relative to the second reference voltage Vref2. When the sum of the integral voltage VO and input voltage VI is greater than the second reference voltage Vref2, the digital signal of "1" can be output. Conversely, when the sum of the integral voltage VO and input voltage VI is less than the second reference voltage Vref2, the digital signal of "0" can be output.

[0063] It should be noted that the quantization module 20 generally includes at least one first capacitor C1, which can be charged based on the input voltage VI to save information related to the size of the input voltage VI, so that the quantization module 20 outputs the conversion digital signal Dout according to the charge stored in the first capacitor C1 in combination with the integral voltage VO and the second reference voltage Vref2.

[0064] It can be understood that in some possible embodiments, the quantization module 20 can further include a second capacitor C2 charged based on the integral voltage VO and a third capacitor C3 charged based on the second reference voltage Vref2, so that the quantization module 20 outputs the conversion digital signal Dout according to the charges stored in the first capacitor C1, second capacitor C2 and third capacitor C3; or in some possible embodiments, the quantization module 20 can further include a second capacitor C2 charged based on the integral voltage VO, so that the quantization module 20 outputs the conversion digital signal Dout according to the charges stored in the first capacitor C1 and second capacitor C2 in combination with the second reference voltage Vref2.

[0065] In some embodiments of the present application, the isolation module 30 is connected between the voltage input terminal 101 and the first capacitor C1, and the isolation module 30 can isolate the first capacitor C1 from the preceding circuit 1 (e.g., a PGA amplifier circuit or a TIA amplifier circuit, etc.) connected to the voltage input terminal 101, so as to avoid the influence of the first capacitor C1 on the preceding circuit 1.

[0066] In some embodiments of the present application, the parasitic capacitance of the isolation module 30 has a capacitance value smaller than that of the at least one first capacitor C1, so as to avoid the phenomenon that the load capacitance of the preceding circuit 1 increases due to the parasitic capacitance of the isolation module 30 after the isolation module 30 is set.

[0067] In some embodiments of the present application, the isolation module 30 can provide a charging voltage to the first capacitor C1 at a ratio of 1:1, that is, the ratio of the output voltage of the isolation module 30 to the input voltage VI is equal to 1:1. In some embodiments of the present application, the isolation module 30 can also provide a charging voltage to the first capacitor C1 at a ratio of N:1 (N>1), that is, the ratio of the output voltage of the isolation module 30 to the input voltage VI is equal to N:1.

[0068] As an example, refer to Figure 7 , Figure 7 Another schematic diagram of the analog-to-digital converter 100 in the embodiments of the present application is shown, in which the isolation module 30 includes a first operational amplifier OP1, the first input terminal of the first operational amplifier OP1 is connected to the preceding circuit 1, the second input terminal of the first operational amplifier OP1 is connected to the output terminal of the first operational amplifier OP1, and the output terminal of the first operational amplifier OP1 is connected to the first capacitor C1 of the quantization module 20. At this time, the connection mode of the first operational amplifier OP1 constitutes a voltage follower, and due to the virtual short and virtual open characteristics of the first operational amplifier OP1, the voltage at the first input terminal of the first operational amplifier OP1 is equal to the voltage at the second input terminal. Therefore, the voltage at the output terminal of the first operational amplifier OP1 connected to the second input terminal is equal to the input voltage VI, that is, at this time, the isolation module 30 can provide a charging voltage to the first capacitor C1 at a ratio of 1:1. At the same time, since the first input terminal of the first operational amplifier OP1 is connected to the voltage input terminal 101, the capacitance of the capacitor connected to the preceding circuit 1 is only the input tube capacitance of the first operational amplifier OP1, which is obviously smaller than the first capacitor C1 in the quantization module 20 (e.g., a bit quantizer), so as to effectively reduce the load capacitance of the preceding circuit 1.

[0069] It can be understood that the above is only an exemplary embodiment of the isolation module 30 of the present application, and in some possible embodiments, the isolation module 30 can also use a current mirror to isolate the front-end circuit 1 connected to the voltage input terminal 101 from the first capacitor C1.

[0070] In the embodiments of the present application, the present application outputs the integral voltage VO according to the converted digital signal Dout of the last measurement period, the input voltage VI and the first reference voltage Vref1 in each measurement period through the integration module 10, and outputs the converted digital signal Dout of the current measurement period according to the integral voltage VO, the input voltage VI and the second reference voltage Vref2 in each measurement period through the quantization module 20, so as to realize the analog-to-digital conversion process of the digital signal converted from the input signal. Since the isolation module 30 is arranged between the quantization module 20 and the voltage input terminal 101, the capacitor (for example, the first capacitor C1) in the quantization module 20 can be isolated from the front-end circuit 1 connected to the voltage input terminal 101 through the isolation module 30, so as to avoid the problem that the load capacitance of the front-end circuit 1 is increased due to the capacitor in the quantization module 20, and the power consumption of the front-end circuit of the integrator cascade feedforward structure type analog-to-digital converter is increased.

[0071] In some embodiments of the present application, for example, for the embodiment in which the quantization module 20 further includes the second capacitor C2 charged based on the integral voltage VO and the third capacitor C3 charged based on the second reference voltage Vref2, refer to Figure 8 , Figure 8 Another schematic diagram of the analog-to-digital converter 100 in the embodiments of the present application is shown, in which the quantization module 20 includes at least one analog operation unit 21 and at least one comparator 22; the analog operation unit 21 is connected to the integration module 10, the analog operation unit 21 is connected to the voltage input terminal 101, and the analog operation unit 21 is connected to the second reference terminal 103 providing the second reference voltage Vref2; the analog operation unit 21 outputs the first voltage signal V01 according to the integral voltage VO output by the integration module 10, the input voltage VI and the second reference voltage Vref2, and the comparator 22 outputs the converted digital signal Dout according to the first voltage signal V01; wherein the analog operation unit 21 includes the first capacitor C1 charged based on the input voltage VI, the second capacitor C2 charged based on the integral voltage VO and the third capacitor C3 charged based on the second reference voltage Vref2.

[0072] It should be noted that since the analog operation unit 21 includes the first capacitor C1 charged based on the input voltage VI, the second capacitor C2 charged based on the integral voltage VO, and the third capacitor C3 charged based on the second reference voltage Vref2, the first capacitor C1 can store a charge signal related to the input voltage VI, the second capacitor C2 can store a charge signal related to the integral voltage VO, and the third capacitor C3 can store a charge signal related to the second reference voltage Vref2, ultimately enabling the analog operation unit 21 to output a first voltage signal V01 that is the difference between the sum of two of the integral voltage VO, the input voltage VI, and the second reference voltage Vref2 and the other one.

[0073] For example, taking the example of the quantization module 20 judging the magnitude of the sum of the integral voltage VO and the input voltage VI relative to the second reference voltage Vref2, the first voltage signal V01 output by the analog operation unit 21 can satisfy the following relationship:

[0074] V01 = VO + VI - VR

[0075] After inputting the first voltage signal V01 into the comparator 22, the comparator 22 is actually judging the positive and negative of the first voltage signal V01, i.e., the comparator 22 can judge the magnitude of the sum of the integral voltage VO and the input voltage VI relative to the second reference voltage Vref2, and ultimately output a conversion digital signal Dout according to the first voltage signal V01.

[0076] As an exemplary embodiment, reference is made to Figure 9 , Figure 9Another schematic diagram of the analog-to-digital converter 100 in the embodiment of the present application is shown, wherein the analog operation unit 21 further comprises a first total switch S0, a first sub-switch S01, a second sub-switch S02, a third sub-switch S03, a fourth sub-switch S04, a fifth sub-switch S05, a sixth sub-switch S06, and a seventh sub-switch S07; the first plates of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are connected to each other, one end of the first total switch S0 is connected to the input end of the comparator 22, and the other end is connected to the first plate of the first capacitor C1; one end of the first sub-switch S01 is connected to the isolation module 30 to access the input voltage VI, and the other end is connected to the second plate of the first capacitor C1; one end of the second sub-switch S02 accesses the common-mode voltage VCM, and the other end is connected to the second plate of the first capacitor C1; one end of the third sub-switch S03 is connected to the integration module 10 to access the integration voltage VO, and the other end is connected to the second plate of the second capacitor C2; one end of the fourth sub-switch S04 accesses the common-mode voltage VCM, and the other end is connected to the second plate of the second capacitor C2; one end of the fifth sub-switch S05 is connected to the second reference end 103 to access the second reference voltage Vref2, and the other end is connected to the second plate of the third capacitor C3; one end of the sixth sub-switch S06 accesses the common-mode voltage VCM, and the other end is connected to the second plate of the third capacitor C3; one end of the seventh sub-switch S07 accesses the common-mode voltage VCM, and the other end is connected to the first plate of the first capacitor C1.

[0077] Specifically, when the first total switch S0, the first sub-switch S01, the third sub-switch S03, and the sixth sub-switch S06 are open, and the second sub-switch S02, the fourth sub-switch S04, the fifth sub-switch S05, and the seventh sub-switch S07 are closed, the amount of charge accumulated by the first capacitor C1, the second capacitor C2, and the third capacitor C3 is:

[0078] Q = (Vref2-VCM)*C

[0079] wherein C is the capacitance value of the first capacitor C1, the second capacitor C2, and the third capacitor C3.

[0080] When the first total switch S0, the first sub-switch S01, the third sub-switch S03, and the sixth sub-switch S06 are closed, and the second sub-switch S02, the fourth sub-switch S04, the fifth sub-switch S05, and the seventh sub-switch S07 are open, according to the law of conservation of charge:

[0081] (Vref2-VCM)*C = (VCM-VX)*C + (VI-VX)*C + (VO-VX)*C

[0082] wherein VX is the voltage of the first plate of the first capacitor C1.

[0083] Taking VCM=0V as an example, the voltage inputted into the non-inverting input terminal of the comparator 22 is:

[0084] VX=(VO+VI-Vref2) / 3

[0085] It can be seen that, through the above switch control process, the comparator 22 is judging the positive and negative of VO+VI-V3 at this time, that is, judging the size of the sum of the integral voltage VO and the input voltage VI relative to the second reference voltage Vref2, and finally outputting the converted digital signal Dout according to the comparison result.

[0086] It should be pointed out that the above content about the analog-to-digital converter 100 is intended to clearly illustrate the implementation process of the present application, and those skilled in the art can make equivalent modifications and designs under the guidance of the present application, for example, referring to Figure 10 , Figure 10 Another schematic diagram of the analog-to-digital converter 100 in the embodiment of the present application is shown, when the integral module 10 adopts a fully differential circuit structure, the analog operation unit 21 can also be modified into a fully differential circuit structure adaptively.

[0087] For another example, referring to Figure 11 , Figure 11 Another schematic diagram of the analog-to-digital converter 100 in the embodiment of the present application is shown, the analog operation unit 21 includes a first capacitor C1 charged based on the input voltage VI and a second capacitor C2 charged based on the integral voltage VO, and the second input terminal of the comparator 22 is directly connected with the second reference terminal 103 to access the second reference voltage Vref2.

[0088] When the first total switch S0, the first sub-switch S01, and the third sub-switch S03 are opened, and the second sub-switch S02, the fourth sub-switch S04, the fifth sub-switch S05, and the seventh sub-switch S07 are closed, the charge amount accumulated by the first capacitor C1 and the second capacitor C2 is 0.

[0089] And when the first total switch S0, the first sub-switch S01, and the third sub-switch S03 are closed, and the second sub-switch S02, the fourth sub-switch S04, the fifth sub-switch S05, and the seventh sub-switch S07 are opened, according to the charge conservation:

[0090] 0=(VI-VX)*C+(VO-VX)*C

[0091] At this time, the first voltage signal V01 inputted into the non-inverting input terminal of the comparator 22 is:

[0092] VX=(VO+VI) / 2

[0093] Since the second input end of the comparator 22 is connected to the second reference voltage Vref2, the comparator 22 can compare the size of (VO+VI) / 2 and Vref2, and finally output the converted digital signal Dout.

[0094] In order to better implement the analog-to-digital converter 100 in the embodiments of the present application, on the basis of the analog-to-digital converter 100, the present application further provides a signal processing circuit, which is described with reference to Figure 12 , Figure 12 A schematic diagram of the signal processing circuit in the embodiments of the present application is shown, wherein the signal processing circuit comprises the signal amplification circuit 200 and the analog-to-digital converter 100 described in any of the above embodiments, the signal amplification circuit 200 is connected to the signal to be converted to amplify the signal to be converted and output the amplified input signal VI; the analog-to-digital converter 100 is connected to the signal amplification circuit 200 to perform analog-to-digital conversion on the input signal and output the converted digital signal Dout.

[0095] Exemplarily, the signal amplification circuit 200 can include but is not limited to a PGA programmable amplifier, a TIA amplifier, an inverting amplifier, a non-inverting amplifier, etc.

[0096] The embodiments of the present application further provide a chip, which comprises the analog-to-digital converter 100 described above. The chip (Integrated Circuit, IC) is also called a chip, which can be but is not limited to a SOC (System on Chip) chip, a SIP (system in package) chip. Since the chip of the present application has the analog-to-digital converter 100 described in the above embodiments, it has all the beneficial effects of the analog-to-digital converter 100 in the above embodiments, which will not be repeated here.

[0097] The embodiments of the present application further provide an electronic device, which comprises a device main body and a chip as described above arranged in the device main body. The electronic device can be but is not limited to a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car control panel, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes but is not limited to a smart watch, a smart bracelet, a cervical vertebra massage instrument. The mobile terminal includes but is not limited to a smart phone, a notebook computer, a tablet computer, a POS (point of sales terminal) machine. The smart home device includes but is not limited to a smart socket, a smart rice cooker, a smart sweeper, a smart lamp.

[0098] The above merely describes the preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some more changes or modifications to the equivalent embodiments with the disclosed technical content, as long as the changes or modifications do not deviate from the technical solution of the present application. Any brief modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still falls within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital converter, characterized by The application relates to an integrated module for converting an input voltage into a digital signal, comprising: an integration module connected to a voltage input terminal for providing an input voltage, said voltage input terminal being connected to a pre-stage circuit; a quantization module connected to said integration module, said quantization module being connected to said voltage input terminal; wherein an isolation module is arranged between said quantization module and said voltage input terminal for isolating said pre-stage circuit connected to said voltage input terminal from said quantization module.

2. The analog-to-digital converter of claim 1, wherein, The ratio of the output voltage of said isolation module to said input voltage is equal to 1:

1.

3. The analog-to-digital converter of claim 2, wherein, Said isolation module comprises a first operational amplifier; a first input terminal of said first operational amplifier is connected to said pre-stage circuit, a second input terminal of said first operational amplifier is connected to an output terminal of said first operational amplifier, and said output terminal of said first operational amplifier is connected to said quantization module.

4. The analog-to-digital converter of claim 1, wherein, Said quantization module comprises at least one first capacitor charged by said input voltage; said isolation module is connected between said voltage input terminal and said first capacitor, and the parasitic capacitance of said isolation module is smaller than the capacitance of said at least one first capacitor.

5. The analog-to-digital converter of claim 1, wherein, Said quantization module comprises at least one analog operation unit and at least one comparator; said analog operation unit is connected to said integration module, said analog operation unit is connected to said voltage input terminal, and said analog operation unit is connected to a second reference terminal for providing a second reference voltage; said analog operation unit outputs a first voltage signal according to an integration voltage output by said integration module, said input voltage and said second reference voltage, and said comparator outputs a converted digital signal according to said first voltage signal; wherein said analog operation unit comprises a first capacitor charged by said input voltage, a second capacitor charged by said integration voltage and a third capacitor charged by said second reference voltage.

6. The analog-to-digital converter of claim 5, wherein, Said analog operation unit further comprises a first main switch, a first sub-switch, a second sub-switch, a third sub-switch, a fourth sub-switch, a fifth sub-switch, a sixth sub-switch and a seventh sub-switch; first poles of said first capacitor, said second capacitor and said third capacitor are connected to each other, one end of said first main switch is connected to an input terminal of said comparator, and the other end of said first main switch is connected to a first pole of said first capacitor; one end of said first sub-switch is connected to said isolation module for accessing said input voltage, and the other end of said first sub-switch is connected to a second pole of said first capacitor; one end of said second sub-switch is connected to a common mode voltage, and the other end of said second sub-switch is connected to a second pole of said first capacitor; one end of said third sub-switch is connected to said integration module for accessing said integration voltage, and the other end of said third sub-switch is connected to a second pole of said second capacitor; one end of said fourth sub-switch is connected to said common mode voltage, and the other end of said fourth sub-switch is connected to a second pole of said second capacitor; one end of said fifth sub-switch is connected to said second reference terminal for accessing said second reference voltage, and the other end of said fifth sub-switch is connected to a second pole of said third capacitor; one end of said sixth sub-switch is connected to said common mode voltage, and the other end of said sixth sub-switch is connected to a second pole of said third capacitor; One end of the seventh sub-switch is connected to the common-mode voltage, and the other end is connected to the first plate of the first capacitor.

7. The analog-to-digital converter of claim 1, wherein, The integration module comprises a sampling unit, a feedback unit and an integrator. The sampling unit is connected to the voltage input end to sample the input voltage and accumulate a sampling charge signal in a sampling stage of each measurement period. The feedback unit is connected to a first reference end providing a first reference voltage to output a feedback charge signal according to the converted digital signal of a previous measurement period and the first reference voltage in each measurement period. The integrator is connected to the sampling unit and the feedback unit to integrate the sampling charge signal and the feedback charge signal and output an integrated voltage in a conversion stage of each measurement period.

8. A signal processing circuit, characterized by comprising: Comprising: a signal amplification circuit connected to a signal to be converted to amplify the signal to be converted and output an amplified input signal; an analog-to-digital converter according to any one of claims 1 to 7 connected to the signal amplification circuit to convert the input signal into a digital signal and output the converted digital signal.

9. A chip, characterized by Comprising an analog-to-digital converter according to any one of claims 1 to 7.

10. An electronic device, comprising: Comprising a chip according to claim 9.

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