A stable bootstrap potential circuit applied in a FET operating point circuit
By designing a stable bootstrap potential circuit and utilizing the combination of resistors R1, R7, and MOSFET T4, the problems of low sensitivity and high distortion caused by capacitor leakage in humid environments were solved, thereby improving the stability of the FET operating point circuit and signal quality.
Patent Information
- Application Number
- CN202423247508.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2034-12-27
AI Technical Summary
In humid environments, the surface resistance between the two electrodes of capacitor C5 decreases, causing the +60V voltage to leak into the gate of the T4FET device, affecting VGS and resulting in low sensitivity, no signal, and high distortion.
Design a stable bootstrap potential circuit that directly powers the microphone MK through resistors R1 and R7. The AC signal is coupled to MOSFET T4 through C5 for signal amplification. The gate power supply of MOSFET T4 is provided with a stable -60V polarization voltage through R6, R4, and R5 to ensure that the gate operating point is not affected by moisture.
In humid environments, the offset of the gate operating point of MOSFET T4 is avoided, preventing problems such as low sensitivity, no signal, and high distortion, thus improving the stability and applicability of the circuit.
Smart Images
Figure CN223613467U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of bootstrap circuit, especially relates to a stable bootstrap potential circuit applied to FET operating point circuit. BACKGROUND
[0002] In the analysis and processing condenser microphone failure fault time, found that part of the product appears temporarily low sensitivity or no signal, distortion, etc. The utility model discloses a stable bootstrap potential circuit applied to FET operating point circuit. UTILITY MODEL CONTENTS
[0003] In order to solve above -mentioned problem, the utility model provides a kind of stable bootstrap potential circuit applied to FET operating point circuit.The utility model solves the problem that in the humid environment, due to the reason of moisture between the two poles of C5 capacitor, surface resistance between the two poles reduces and changes, with the reduction of surface resistance of C5 component, +60V voltage leaks to T4 FET element gate, +60V leakage voltage is higher than gate working voltage, changes gate voltage, influences VGS, causes T4 component operating point to shift, causes low sensitivity, no signal, distortion, etc.
[0004] The utility model discloses a kind of stable bootstrap circuit applied to FET working point circuit, including resistance R1, R2, R3, R4, R5, R6, R7, capacitor C1, C2, C3, C4, C5, C6, C7, C8, diode D1, D2, D3, D4, MOS tube T4 and sound head MK, diode D1, diode D2, diode D3, diode D4 are connected in series in sequence, diode D4 is away from the one end of diode D3 and connects polarization voltage, C8 is connected in parallel between diode D1 and diode D4, capacitor C1 is connected between diode D2 and diode D3, capacitor C1 is away from the one end of diode D2 and connects ground, capacitor C2 is connected in parallel between the one end of diode D1 away from diode D2 and the one end of capacitor C1 close to diode D2, resistance R1 is connected in series between the one end of diode D1 away from diode D1, resistance R1 is connected with resistance R7, resistance R7 is connected with sound head MK at the one end away from resistance R1, the drain of MOS tube T4 is connected with resistance R2, the drain of MOS tube T4 is connected with resistance R3, resistance R2 is connected with input power supply VCC at the one end away from the drain of MOS tube T4, capacitor C6 is connected between the drain of MOS tube T4 and resistance R2, resistance R3 is connected with ground at the one end away from the source of MOS tube T4, capacitor C7 is connected between the source of MOS tube T4 and resistance R3, resistance R4 and R5 are connected in parallel between the source of MOS tube T4 and resistance R3 away from capacitor C7, the gate of MOS tube T4 is connected with capacitor C5, capacitor C5 is connected with sound head MK at the one end away from the gate of MOS tube T4, resistance R6 is connected in parallel between the gate of MOS tube T4 and resistance R4 and R5.
[0005] In the above scheme, the one end of diode D4 away from diode D3 connects ground.
[0006] In the above scheme, capacitor C3 and capacitor C4 are arranged between resistance R1 and resistance R7, and the other ends of capacitor C3 and capacitor C4 are connected with ground.
[0007] In the above scheme, input power supply VCC is 15V.
[0008] In the above scheme, MOS tube T4 is N-channel FET element.
[0009] The utility model discloses a kind of stable bootstrap potential circuits applied to FET working point circuit, -60V polarization voltage is directly supplied to sound head MK by resistance R1 and resistance R7, alternating current signal is coupled in through C5 after MOS tube T4 FET element carries out signal amplification final output, MOS tube T4 element gate supply is supplied to T4 gate by R6, R4, R5, polarization voltage is changed to -60V, even in humid environment, the surface resistance of C5 capacitor both ends reduces, gate working point potential is higher than -60V polarization voltage potential, so it will not cause too much change to the working point of gate, will not cause low sensitivity, no signal, distortion big phenomenon, this kind of bootstrap potential circuit structure is simple, applicability is strong, can effectively avoid the phenomenon that sensitivity appears bad, improve the practicality of bootstrap potential circuit. BRIEF DESCRIPTION OF DRAWINGS
[0010] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the utility model.
[0011] Figure 1 It is the circuit diagram of the utility model. DETAILED DESCRIPTION
[0012] The specific embodiments of the utility model will be further described below with reference to the drawings and embodiments. The following embodiments are only used to more clearly illustrate the technical solutions of the utility model, and cannot limit the protection scope of the utility model.
[0013] As Figure 1The utility model discloses a kind of stable bootstrap potential circuits applied to FET working point circuit in the above-mentioned scheme, including resistance R1, R2, R3, R4, R5, R6, R7, capacitor C1, C2, C3, C4, C5, C6, C7, C8, diode D1, D2, D3, D4, MOS tube T4 and sound head MK, diode D1, diode D2, diode D3, diode D4 are in series in turn, diode D4 is away from the one end of diode D3 and connects polarization voltage, polarization voltage is-60V, C8 is connected in parallel between diode D1 and diode D4, capacitor C1 is connected between diode D2 and diode D3, the one end of capacitor C1 is away from diode D2 and diode D3 and connects ground, the one end of diode D1 is away from diode D2 and capacitor C1 is close to the one end of diode D2 and connects capacitor C2, resistance R1 is connected in series to the one end of diode D1, resistance R1 is connected to diode D1 and resistance R7, resistance R7 is connected to sound head MK to the one end of resistance R1, the drain of MOS tube T4 is connected to resistance R2, the drain of MOS tube T4 is connected to resistance R3, resistance R2 is connected to input power supply VCC to the one end of the drain of MOS tube T4, capacitor C6 is connected between the drain of MOS tube T4 and resistance R2, resistance R3 is connected to ground to the one end of the source of MOS tube T4, capacitor C7 is connected between the source of MOS tube T4 and resistance R3, resistance R4 and R5 are connected in parallel to the source of MOS tube T4 and resistance R3 to the one end of capacitor C7, the gate of MOS tube T4 is connected to capacitor C5, capacitor C5 is connected to sound head MK to the one end of the gate of MOS tube T4, resistance R6 is connected in parallel between the gate of MOS tube T4 and resistance R4 and R5.
[0014] The one end of diode D4 is away from diode D3 and connects ground.
[0015] Resistance R1 and resistance R7 are equipped with capacitor C3, capacitor C4, the other end of capacitor C3, capacitor C4 connects ground.
[0016] Input power supply VCC is 15V.
[0017] MOS tube T4 is N channel FET element.
[0018] Specifically, in the utility model, -60V polarization voltage is directly supplied to the sound head MK through the resistor R1 and the resistor R7, the alternating current signal is coupled through C5 and is finally output after signal amplification through the MOS tube T4 FET element, the MOS tube T4 element gate supply is supplied to the T4 gate through R6, R4, R5, the polarization voltage is changed to -60V, even if the surface resistance of the two poles of the C5 capacitor is reduced in a humid environment, the gate working point potential is higher than the -60V polarization voltage potential, so that the gate working point will not change too much, and the low sensitivity, no signal and large distortion phenomenon will not be caused.
[0019] The above merely describes the preferred embodiments of the utility model and is not intended to limit the utility model, and any modification, equivalent replacement, improvement, etc. within the spirit and principle of the utility model should be included in the protection scope of the utility model.
Claims
1. A stable bootstrap potential circuit applied in a FET operating point circuit, comprising resistors R1, R2, R3, R4, R5, R6, R7, capacitors C1, C2, C3, C4, C5, C6, C7, C8, diodes D1, D2, D3, D4, a MOS transistor T4 and a tone head MK, characterized in that, The diode D1, diode D2, diode D3, diode D4 are connected in series, the diode D4 is connected to a polarized voltage away from one end of diode D3, the diode D1 and diode D4 are connected in parallel with C8, the diode D2 and diode D3 are connected with a capacitor C1, the capacitor C1 is connected to ground away from one end of diode D2 and diode D3, the diode D1 is connected in parallel with a capacitor C2 away from one end of diode D2 and one end of capacitor C1, the diode D1 is connected in series with a resistor R1 away from one end of diode D1, the resistor R1 is connected with a resistor R7 away from one end of resistor R1, the resistor R7 is connected with a sound head MK away from one end of resistor R1, the MOS tube T4 drain is connected with a resistor R2, the MOS tube T4 drain is connected with a resistor R3, the resistor R2 is connected with an input power supply VCC away from one end of MOS tube T4 drain, the MOS tube T4 drain is connected with a capacitor C6 between the MOS tube T4 drain and the resistor R2, the resistor R3 is connected to ground away from one end of MOS tube T4 source, the MOS tube T4 source is connected with a capacitor C7 between the MOS tube T4 source and the resistor R3, the MOS tube T4 source is connected in parallel with a resistor R4 and R5 away from one end of capacitor C7, the MOS tube T4 gate is connected with a capacitor C5, the capacitor C5 is connected with a sound head MK away from one end of MOS tube T4 gate, the MOS tube T4 gate is connected in parallel with a resistor R6 between the MOS tube T4 gate and the resistor R4 and R5.
2. A stable bootstrap potential circuit for use in an FET operating point circuit according to claim 1, wherein, The diode D4 is connected to ground away from one end of diode D3.
3. A stable bootstrap potential circuit for use in an FET operating point circuit according to claim 1, wherein The resistor R1 and resistor R7 are provided with a capacitor C3 and a capacitor C4, and the other end of the capacitor C3 and the capacitor C4 is connected to ground.
4. The bootstrap circuit for use in a FET operating point circuit according to claim 1, wherein, The input power supply VCC is 15V.
5. A stable bootstrap potential circuit for use in an FET operating point circuit according to claim 1, wherein, The MOS tube T4 is an N-channel FET element.