Multi-channel data analysis equipment based on FPGA (Field Programmable Gate Array)

Abstract

The utility model relates to the technical field of communication, in particular to multi-channel data analysis equipment based on an FPGA (Field Programmable Gate Array), which is characterized in that an FPGA (Field Programmable Gate Array) 1 comprises a 1XSRIO interface, a serial port module and a 4XSRIO interface, an FPGA 2 comprises a 1XSRIO interface, a serial port module and a 4XSRIO interface, an FPGA 3 comprises two 4XSRIO interfaces, a serial port module and an algorithm core, the FPGA 1 is connected with one 4XSRIO interface in the FPGA 3 through the 4XSRIO interface, and the FPGA 2 is connected with the other 4XSRIO interface in the FPGA 3 through the 4XSRIO interface. According to the device, data synchronization processing of a plurality of external channels can be realized, the FPGA1 and the FPGA2 receive external multi-channel data to be analyzed through the 1XSRIO interface and send the analyzed data to the outside, and the FPGA3 is used for analyzing and sending the received data.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, specifically to a multi-channel data parsing device based on FPGA. Background Technology

[0002] Currently, in modern industry, scientific research and other fields, the requirements for the accuracy and efficiency of data processing and analysis are getting higher and higher. Common analysis equipment uses microcontrollers for software design to process data, but it cannot obtain accurate clock signals and the processor speed is insufficient. Summary of the Invention

[0003] This invention addresses the problem of low data parsing efficiency in current parsing devices by providing a multi-channel data parsing device based on FPGA, which can achieve high-speed data processing and transmission.

[0004] This utility model is implemented using the following technical solution: A multi-channel data parsing device based on FPGA, comprising three FPGA chips, namely FPGA1, FPGA2, and FPGA3. FPGA1 includes a 1XSRIO interface, a serial port module, and a 4XSRIO interface; FPGA2 includes a 1XSRIO interface, a serial port module, and a 4XSRIO interface; FPGA3 includes two 4XSRIO interfaces, a serial port module, and an algorithm core. Internally, the 1XSRIO interface of FPGA1 is connected to the serial port module, and the serial port module is connected to the 4XSRIO interface. Externally, the 1XSRIO interface serves as the input and output interface of FPGA1, and the 4XSRIO interface also serves as the output interface of FPGA1. The input and output interfaces are as follows: On FPGA2, the 1XSRIO interface is connected to the serial port module, which in turn is connected to the 4XSRIO interface. On the outside of FPGA2, the 1XSRIO interface serves as both the input and output interface, as does the 4XSRIO interface. On FPGA3, the 4XSRIO interface is connected to the serial port module, which is connected to the algorithm core. On the outside of FPGA3, the 4XSRIO interface serves as both the input and output interface. FPGA1 connects to one of the 4XSRIO interfaces in FPGA3 via the 4XSRIO interface, and FPGA2 connects to the other 4XSRIO interface in FPGA3 via the 4XSRIO interface.

[0005] This invention enables synchronous data processing from multiple external channels. FPGA1 and FPGA2 receive external multi-channel data to be parsed and send the parsed data back to the external system via a 1XSRIO interface. FPGA3 parses the received data and sends it back. FPGA1 and FPGA2 receive and send data from external channels via the 1XSRIO interface, while FPGA3 communicates with FPGA1 and FPGA2 via two 4XSRIO interfaces. After receiving the data, FPGA3 parses it and sends it to the corresponding channel's algorithm core for computation.

[0006] FPGA1 and FPGA2 are used for receiving and transmitting multi-channel data without performing data parsing. The XC7K325TFFG900-2 chip is selected for this purpose due to its relatively high performance and low cost, offering excellent value. FPGA3 needs to handle the synchronous processing of data from multiple channels. The XC7VX690TFFG1761-2L chip is selected for this purpose. Compared to the XC7K325TFFG900-2 chip, this chip offers significantly improved performance and meets the functional requirements of this device.

[0007] Both FPGA1 and FPGA2 have 8 1XSRIO interfaces. Both FPGA1 and FPGA2 can connect to 8 external devices simultaneously through the 8 1XSRIO interfaces to achieve synchronous data processing of 8 external channels.

[0008] This invention provides a multi-channel data parsing device based on FPGA, comprising three FPGA chips, which can realize synchronous data processing of eight external channels and has high data parsing and processing efficiency. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the composition structure of this utility model.

[0010] Figure 2 This is a schematic diagram of the internal connection relationship of FPGA1 in the figure.

[0011] Figure 3 This is a schematic diagram of the internal connection relationship of FPGA2 in the figure.

[0012] Figure 4 This is a schematic diagram of the internal connection relationship of FPGA3 in the figure. Detailed Implementation

[0013] The present invention will now be described in further detail with reference to the accompanying drawings, so that those skilled in the art can implement it based on the description.

[0014] This invention provides a multi-channel data parsing device based on FPGA, comprising three FPGA chips. FPGA1 and FPGA2 are used to receive external multi-channel data to be parsed and to send the parsed data to the corresponding channels. FPGA3 is used to parse the received data and send it back. FPGA1 and FPGA2 receive data from eight external channels via a 1xSRIO interface, while FPGA3 communicates with FPGA1 and FPGA2 via two 4xSRIO interfaces respectively. After receiving the data, FPGA3 parses it according to the protocol, determines the source channel of the data packet, and sends the data to the corresponding algorithm core for processing.

[0015] The serial port module configures channel information for the FPGA. When FPGA1 or FPGA2 receives data to be parsed, it fills the SRIO data packet header with a channel identifier based on the data's source channel. When sending parsed data, it sends the data out through the corresponding channel according to the channel identifier in the data packet. After receiving the data, FPGA3 matches the channel identifier in the data packet with the serial port's configured channel information to determine the source channel of the data packet and sends the data to the corresponding algorithm core for processing.

[0016] Figure 1 This is a schematic diagram of the composition structure of this utility model. The data to be parsed from the 8 channels received by FPGA1 is sent to FPGA3 for parsing, and then sent out through the 8 channels of FPGA2 after parsing. The data to be parsed from the 8 channels received by FPGA2 is sent to FPGA3 for parsing, and then sent out through the 8 channels of FPGA1 after parsing.

[0017] Figure 2 This diagram illustrates the internal connections of FPGA1. The eight channels can simultaneously receive eight external channels of data to be parsed. After receiving the data, each channel fills the header of the SRIO data packet with the channel information corresponding to the current channel according to the serial port configuration, and buffers the data of each channel. FPGA1 polls the data of the eight channels, sends the data received by the 1XSRIO interface to the 4XSRIO interface and outputs it to FPGA3 for processing. By increasing the bandwidth, the latency in data transmission is reduced.

[0018] Additionally, FPGA1 can receive parsed data sent by FPGA3. Data to be parsed received by FPGA2 is sent to FPGA3 and then sent to FPGA1 after parsing. FPGA1 then sends the data packet outward from the corresponding channel according to the channel identifier in the header of the received SRIO data packet.

[0019] Figure 3The diagram shows the internal connection of FPGA2. The eight channels can simultaneously receive eight channels of data to be parsed from the outside. After receiving the data, each channel fills the header of the SRIO data packet with the channel information corresponding to the current channel according to the serial port configuration, and buffers the data of each channel. FPGA1 polls the data of the eight channels and sends the data currently received from the 1XSRIO interface to the 4XSRIO interface for output to FPGA3 for processing. By increasing the bandwidth, the latency in data transmission is reduced.

[0020] In addition, FPGA2 can receive parsed data sent by FPGA3, and the data to be parsed sent by FPGA1 is sent out through FPGA2 after being parsed by FPGA3.

[0021] Figure 4 This is a schematic diagram of the internal connection relationship of FPGA3. The eight independent algorithm cores correspond to channels 1 to 8 of the side FPGA. When FPGA3 receives service data from FPGA1 or FPGA2, it parses the packet header, determines the source channel of the packet data based on the channel information configured in the serial port, and then sends the packet data to the corresponding algorithm core for parsing. After the corresponding algorithm core has completed parsing, it fills the parsed data with the channel position information configured in the serial port according to the position of the algorithm core, and then sends it to the 4XSRIO interface through the AXI4 bus, and then to FPGA2 or FPGA1.

[0022] The algorithm core in FPGA3 can load filtering algorithms such as IIR digital filtering or median filtering to filter and analyze the input data. In addition, it can also load algorithms such as binarization or Fourier transform to process the input digital signal. Only one algorithm is loaded at a time in FPGA3, and the loaded algorithms are all well known to those skilled in the art.

Claims

1. A multi-channel data parsing device based on FPGA, characterized in that: The system comprises three FPGA chips: FPGA1, FPGA2, and FPGA3. FPGA1 includes a 1XSRIO interface, a serial port module, and a 4XSRIO interface. FPGA2 includes a 1XSRIO interface, a serial port module, and a 4XSRIO interface. FPGA3 includes two 4XSRIO interfaces, a serial port module, and an algorithm core. Internally, the 1XSRIO interface connects to the serial port module, and the serial port module connects to the 4XSRIO interface. Externally, the 1XSRIO interface and the 4XSRIO interface serve as input and output interfaces for FPGA1. The RIO interface connects to the serial port module, which in turn connects to the 4XSRIO interface. On the outside of FPGA2, the 1XSRIO interface serves as both input and output for FPGA2, as do the 4XSRIO interfaces. Inside FPGA3, the 4XSRIO interface connects to the serial port module, which in turn connects to the algorithm core. On the outside of FPGA3, the 4XSRIO interface serves as both input and output for FPGA3. FPGA1 connects to one of the 4XSRIO interfaces in FPGA3 via its own 4XSRIO interface, and FPGA2 connects to the other 4XSRIO interface in FPGA3 via its own 4XSRIO interface.

2. The FPGA-based multi-channel data parsing device according to claim 1, characterized in that: The FPGA1 and FPGA2 are equipped with the xc7k325tffg900-2 chip, and the FPGA3 is equipped with the xc7vx690tffg1761-2L chip.

3. The FPGA-based multi-channel data parsing device according to claim 2, characterized in that: Both FPGA1 and FPGA2 have 8 XSRIO interfaces.

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