Calculating device capable of expanding computing power
By using discrete resistor-capacitor devices to isolate DC crosstalk in the computing device, high-speed signal interaction between the computing chip and external modules is achieved, solving the problem of insufficient computing power configuration in the autonomous driving platform and realizing flexible computing power expansion and reliable signal transmission.
Patent Information
- Application Number
- CN202423196676.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2034-12-24
AI Technical Summary
Existing autonomous driving computing platforms lack flexibility in computing power configuration, failing to meet the ever-increasing computing resource demands of deep learning algorithms. This leads to decreased system performance and insufficient reliability, and circuit boards and chips require complete replacement and redesign when expanding computing power.
The first, second, and third discrete RC components within the package are used to isolate DC crosstalk and enable high-speed signal interaction between computing chips. They are also connected to external computing power expansion modules via wires, supporting flexible configuration and expansion of computing power.
It enables flexible computing power configuration of computing devices, supports the expansion of future computing power needs, avoids signal crosstalk, and improves the reliability and security of the system.
Smart Images
Figure CN223624606U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of computer technology, and in particular relates to a computing device with scalable computing power. Background Technology
[0002] With the rapid development of autonomous driving technology, the computing power of computing platforms has become a key factor restricting technological progress. Existing autonomous driving computing platforms generally rely on pre-set computing power values, which are derived from theoretical learning, practical data, and computational design.
[0003] However, with the development of autonomous driving technology, especially the continuous evolution of deep learning algorithms at the software level, the demand for computing resources from these algorithms is increasing, often exceeding the expected range of computing power. This insufficient computing power can lead to a decline in system performance, and in some cases, even fail to meet the needs of real-time processing, thus limiting the reliability and safety of autonomous driving systems.
[0004] Furthermore, the existing platform was not designed to fully account for the changes in computing power requirements that may arise from future technological developments. Its circuit boards and chips need to be completely replaced and redesigned when computing power is expanded.
[0005] Therefore, existing platforms lack flexibility in computing power configuration. Utility Model Content
[0006] In response to the aforementioned shortcomings or disadvantages, this application provides a computing device that facilitates flexible configuration of computing power.
[0007] This application provides a scalable computing device, including a circuit board and a first computing chip, a second computing chip, a first resistor-capacitor discrete device, a second resistor-capacitor discrete device, a third resistor-capacitor discrete device, a package housing, a first wire, and a second wire mounted on the circuit board.
[0008] The first, second, and third discrete RC devices are used to isolate DC crosstalk and are located within the package housing.
[0009] The first terminal of the first RC discrete device is connected to the first computing chip, and the second terminal is connected to the first terminal of the first wire. The first terminal of the second RC discrete device is connected to the second computing chip, and the second terminal is connected to the second terminal of the second wire. The first terminal of the third RC discrete device is connected to the first terminal of the first RC discrete device, and the second terminal is connected to the first terminal of the second RC discrete device.
[0010] The outer casing of the package has: a first solder joint connected to the second end of the first RC discrete device, a second solder joint connected to the first end of the third RC discrete device, a third solder joint connected to the second end of the third RC discrete device, and a fourth solder joint connected to the second end of the second RC discrete device.
[0011] The second end of the first wire and the second end of the second wire are used to connect to an external computing power expansion module.
[0012] In some embodiments, the first RC discrete device, the second RC discrete device, and the third RC discrete device are each independent capacitor elements.
[0013] In some embodiments, the first RC discrete device, the second RC discrete device and the third RC discrete device are each independent zero-ohm resistors.
[0014] In some embodiments, the scalable computing device further includes a high-speed external interface. A first end of the high-speed external interface is connected to a second end of a first wire, a second end is connected to a second end of a second wire, and a third end is used to interface with an external computing power expansion module to transmit high-speed signals.
[0015] In some embodiments, the external high-speed interface is a Coolink high-speed interface or a gold finger interface.
[0016] In some embodiments, the third end of the external high-speed interface is not connected to the computing power expansion module interface, the second solder point is soldered to the third solder point, so that the computing device with expandable computing power is in a non-expansion state, the third resistor-capacitor discrete device is in an AC conduction state, and the first resistor-capacitor discrete device and the second resistor-capacitor discrete device are in an open circuit state.
[0017] The third discrete resistor-capacitor device is used to isolate DC crosstalk when the first computing chip and the second computing chip interact with each other.
[0018] In some embodiments, when the third end of the external high-speed interface is connected to the computing power expansion module interface, the first solder joint is soldered to the second solder joint, and the third solder joint is soldered to the fourth solder joint, so that the computing device with expandable computing power is in an expanded state, the third RC discrete device is in an open-circuit state, and the first RC discrete device and the second RC discrete device are in an AC conducting state. The first RC discrete device is used to isolate DC crosstalk during signal interaction between the first computing chip and the computing power expansion module, and the second RC discrete device is used to isolate DC crosstalk during signal interaction between the second computing chip and the computing power expansion module.
[0019] In some embodiments, the circuit board includes a multi-layered board structure with no less than four layers, and the first layer of the board structure near the package housing is used for soldering a first solder joint, a second solder joint, a third solder joint, and a fourth solder joint.
[0020] In some embodiments, the second layer board structure near the package housing serves as the ground reference layer of the first layer board structure, the second layer board structure is in a hollow state, the third layer board structure serves as the ground reference layer of the first RC discrete device, the second RC discrete device and the third RC discrete device, respectively, and the fourth layer board structure and the second layer board structure serve as the upper reference layer and lower reference layer of the third layer board structure, respectively.
[0021] In some embodiments, the length of the package housing projected onto the circuit board is 0.95–1.05 mm, and the width is 0.475–0.525 mm.
[0022] In some embodiments, the first, second, and third discrete RC devices have the same capacitance value, which is 0.1 to 0.22 microfarads.
[0023] The scalable computing device provided in this application encapsulates a first, second, and third discrete RC device into a single unit using a packaged housing. This facilitates modular docking or assembly with components such as the first and second computing chips on a circuit board, and allows for flexible configuration of computing power. The connection structure of the third discrete RC device meets the high-speed signal interaction requirements between the first and second computing chips, satisfying the user's basic computing power configuration needs while avoiding signal crosstalk. Since the circuit board also has a pre-installed structure for the first and second discrete RC devices, a first wire, and a second wire, it also meets the user's future needs for expanding computing power, providing a docking structure for expanded signal channels. This allows for simple and quick docking of external computing power expansion modules and enables high-speed signal interaction between external computing power expansion modules, the first computing chip, and the second computing chip, while avoiding signal crosstalk. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the structure of a scalable computing device according to one or more embodiments of this application;
[0025] Figure 2 This is a schematic diagram of the structure of a computing device with a connected computing power expansion module in one or more embodiments of this application;
[0026] Figure 3 This is a schematic diagram showing the location of the solder joints of a packaging housing in one or more embodiments of this application;
[0027] Figure 4 This is a schematic diagram of the circuit board structure of a computing device with scalable computing power according to one or more embodiments of this application. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0029] It should be noted that when a part or component is considered to be "connected to," "located on," or "assembled" to another part or component, it can be directly mounted on the other part or component, or it may be located in an intermediate part or component. The terms "left," "right," "upper," "lower," and similar expressions used in this document are for illustrative purposes only.
[0030] This application provides a computing device with scalable computing power, such as Figure 1-3 As shown, it includes a circuit board 9 and a first computing chip 1, a second computing chip 2, a first resistor-capacitor discrete device 4, a second resistor-capacitor discrete device 5, a third resistor-capacitor discrete device 3, a package housing 8, a first wire 61, and a second wire 62 mounted on the circuit board 9.
[0031] The first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 are used to isolate DC crosstalk and are located within the package housing 8. The first terminal of the first RC discrete device 4 is connected to the first computing chip 1, and the second terminal is connected to the first terminal of the first wire 61. The first terminal of the second RC discrete device 5 is connected to the second computing chip 2, and the second terminal is connected to the second terminal of the second wire 62. The first terminal of the third RC discrete device 3 is connected to the first terminal of the first RC discrete device 4, and the second terminal is connected to the first terminal of the second RC discrete device 5.
[0032] The outer casing 8 is provided with: a first solder joint 41 connected to the second end of the first RC discrete device 4, a second solder joint 31 connected to the first end of the third RC discrete device 3, a third solder joint 32 connected to the second end of the third RC discrete device 3, and a fourth solder joint 51 connected to the second end of the second RC discrete device 5.
[0033] The second end of the first wire 61 and the second end of the second wire 62 are used to connect to an external computing power expansion module.
[0034] Specifically, circuit board 9 can be a multilayer PCBA (Printed Circuit Board Assembly) board.
[0035] The first computing chip 1 and the second computing chip 2 can be processor units that provide computing power for autonomous driving, such as SOC (System on Chip) chips, CPUs, or GPUs (Graphics Processing Units). Of course, the first computing chip 1 and the second computing chip 2 can also be computing chips on other types of computing platforms.
[0036] The first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 can each be a separate capacitive reactance device or an impedance device, and are used to isolate DC crosstalk when the first computing chip 1 and the second computing chip 2 perform high-speed signal interaction. The high-speed signal refers to a high-frequency AC signal.
[0037] The first wire 61 and the second wire 62 can be printed wire harnesses on the circuit board 9 or single cable harnesses, respectively, and are used to transmit high-speed signals.
[0038] In some embodiments, such as Figure 3 , 4 As shown, the first discrete RC device 4, the second discrete RC device 5, and the third discrete RC device 3 are packaged within a housing 8. The first solder joint 41, the second solder joint 31, the third solder joint 32, and the fourth solder joint 51 external to the housing 8 can be located on the same end face of the housing 8 or on different end faces. They can also be extended externally via wires at a specific distance from the outside of the housing 8. The housing 8 is a non-sealed housing. The first wire 61 and the second wire 62 extend from the housing 8, and the first computing chip 1 and the second computing chip 2 are also connected to the housing 8 via wire bundles.
[0039] For example, such as Figure 1-3As shown, the two ends of the first RC discrete device 4 are connected to the first computing chip 1 and the first wire 61, respectively; the two ends of the second RC discrete device 5 are connected to the second computing chip 2 and the second wire 62, respectively; and the two ends of the third RC discrete device 3 are connected to the first computing chip 1 and the second computing chip 2, respectively. When the operator needs the first computing chip 1 and the second computing chip 2 to perform high-speed signal interaction, the second solder joint 31 and the third solder joint 32 of the package housing 8 are soldered onto the circuit board 9. At this time, the third RC discrete device 3 is AC conductive and plays a role in isolating DC crosstalk of high-speed signals. Due to the structure of installing the third RC discrete device 3 between the first computing chip 1 and the second computing chip 2, the requirement for high-speed signal interaction between the first computing chip 1 and the second computing chip 2 can be met. Alternatively, when the operator needs to connect the first wire 61 and the second wire 62 to an external computing power expansion module, the first solder joint 41, the second solder joint 31, the third solder joint 32, and the fourth solder joint 51 of the package housing 8 are soldered onto the circuit board 9. At this time, the third discrete RC device 3 is open-circuited, while the first discrete RC device 4 and the second discrete RC device 5 are in AC conduction state. Since it also has a structure with a first wire 61 connected to the first discrete RC device 4 and a second wire 62 connected to the second discrete RC device 5, the first computing chip 1 and the second computing chip 2 can respectively interact with the computing power expansion module through the first wire 61 and the second wire 62, thus avoiding signal interference. The computing power expansion module can be another computing chip used to expand computing power. In this way, a computing device with expandable computing power can connect to the computing power expansion module to expand two signal channels, improve the signal transmission rate, and avoid signal interference.
[0040] In some embodiments, such as Figure 1 , 2 As shown, the first discrete RC device 4, the second discrete RC device 5, and the third discrete RC device 3 are all independent capacitor elements.
[0041] Specifically, due to the limited capacity of the encapsulation housing 8, the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 can only be individual capacitor elements, and should not be a capacitor module composed of multiple capacitor elements connected in parallel. In this case, the encapsulation housing 8 encapsulates the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 into an AC coupling capacitor module. This AC coupling capacitor module is used to connect to the computing power expansion module to expand the two signal channels, and shields the electromagnetic interference caused by high-speed signal transmission, thereby improving the electromagnetic compatibility of the computing device with expandable computing power.
[0042] In some embodiments, the capacitance values of the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 are the same, and the capacitance value is 0.1 to 0.22 microfarads.
[0043] In this design, the capacitance values of the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 are determined by the type of high-speed signal to be transmitted. Preferably, the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 are all selected with a capacitance value of 0.22 microfarads to match PCIe x4 (Peripheral Component Interconnect Express x4) signals. This design enables the matching of various high-speed signals, including PCIe x4, improving the transmission efficiency of high-speed signals.
[0044] In some embodiments, such as Figure 1 , 2 As shown, the length of the package housing 8 projected onto the circuit board 9 is 0.95–1.05 mm, and the width is 0.475–0.525 mm.
[0045] In some embodiments, the package housing 8 has a length of 1 mm, a width of 0.5 mm, and a thickness generally not exceeding the length. The specific dimensions of the package housing 8 can have some tolerance within permissible limits. For example, if surface mount technology (a mounting technology distinct from traditional through-hole mounting, used to mount electronic components on circuit board 9) using 0402 (the size of a 0402 package is approximately 1.02 mm × 0.508 mm, and the thickness is generally not exceeding 0.584 mm) is used to package the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3, then the length of the package housing 8 is 1 ± 0.05 mm as described above, and the width is 0.5 ± 0.025 mm as described above. This package housing 8 design saves space in computing devices with scalable computing power.
[0046] In some embodiments, such as Figure 1 , 2 As shown, the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 are all independent zero-ohm resistors.
[0047] Specifically, due to the limited capacity of the package housing 8, the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 must each be a separate zero-ohm resistor, and should not be a zero-ohm resistor module composed of multiple zero-ohm resistors connected in series. A zero-ohm resistor, also known as a jumper resistor or bridging resistor, is a special-purpose resistor with a very small resistance value, close to zero. Furthermore, when conducting high-speed signals, zero-ohm resistors can be used for impedance matching, reducing signal reflection and improving signal integrity. In this case, the package housing 8 encapsulates the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 into an AC-coupled zero-ohm resistor module. This AC-coupled zero-ohm resistor module is used to connect to the computing power expansion module to expand the two signal channels, and it shields against electromagnetic interference caused by high-speed signal transmission, improving the electromagnetic compatibility of the scalable computing device.
[0048] In some embodiments, such as Figure 2 As shown, the scalable computing device also includes an external high-speed interface 7. The first end of the external high-speed interface 7 is connected to the second end of the first wire 61, the second end of the external high-speed interface 7 is connected to the second end of the second wire 62, and the third end of the external high-speed interface 7 is used to interface with an external computing power expansion module to transmit high-speed signals.
[0049] The third end of high-speed interface 7 is an interface for interfacing with external computing power expansion modules, specifically an interface for transmitting PCIe x4 signals. This design enables compatibility with PCIe x4 signals, improving the transmission efficiency of high-speed signals.
[0050] In some embodiments, such as Figure 2 As shown, the external high-speed interface 7 is either a Coollink high-speed interface or a gold finger interface.
[0051] The choice between the Coolink (a proprietary collaborative work platform developed by Zhongke Fulong) high-speed interface 7 and the gold finger interface is determined by the interface of the computing power expansion module. For example, if the computing power expansion module is a SOC chip with a Coolink high-speed interface, then the Coolink high-speed interface will be used for the external high-speed interface 7. Alternatively, if the computing power expansion module is a GPU (Graphics Processing Unit) with a gold finger interface, then the gold finger interface will be used for the external high-speed interface 7. Generally, regardless of whether the external high-speed interface 7 uses the Coolink high-speed interface or the gold finger interface, it can be used to transmit PCIe x4 signals. This design allows for the matching of different types of computing power expansion module interfaces, improving the flexibility of connecting computing power expansion modules.
[0052] In some embodiments, such as Figure 2 As shown, the third end of the external high-speed interface 7 is not connected to the computing power expansion module interface. The second solder joint 31 is soldered to the third solder joint 32, so that the computing device with expandable computing power is in a non-expanded state. The third RC discrete device 3 is in an AC conducting state, and the first RC discrete device 4 and the second RC discrete device 5 are in an open circuit state, so that the computing device with expandable computing power is in a non-expanded state. Among them, the third RC discrete device 3 is used to isolate DC crosstalk when the first computing chip 1 and the second computing chip 2 interact with signals.
[0053] When the operator needs to enable high-speed signal interaction between the first computing chip 1 and the second computing chip 2, the operator can first disconnect the third end of the external high-speed interface 7 from the computing power expansion module interface, and then solder the second solder point 31 and the third solder point 32 of the peripheral device of the package housing 8 onto the circuit board 9, and connect the second solder point 31 and the third solder point 32 by soldering, so that the computing device with expandable computing power is in a non-expanded state.
[0054] This welding method ensures AC conduction of the third RC discrete device 3 while isolating DC crosstalk of high-speed signals and avoiding signal interference to the other first RC discrete device 4 and second RC discrete device 5.
[0055] In some embodiments, such as Figure 2 As shown, the third end of the external high-speed interface 7 is connected to the computing power expansion module interface. The first solder joint 41 is soldered to the second solder joint 31, and the third solder joint 32 is soldered to the fourth solder joint 51, putting the expandable computing device in an expanded state. The third RC discrete device 3 is in an open-circuit state, while the first RC discrete device 4 and the second RC discrete device 5 are in an AC conducting state. Specifically, the first RC discrete device 4 is used to isolate DC crosstalk during signal interaction between the first computing chip 1 and the external computing power expansion module, and the second RC discrete device 5 is used to isolate DC crosstalk during signal interaction between the second computing chip 2 and the computing power expansion module.
[0056] When the operator needs to connect the first wire 61 and the second wire 62 to an external computing power expansion module, the third end of the external high-speed interface 7 can be connected to the computing power expansion module interface. Then, the operator can first solder the first solder point 41, the second solder point 31, the third solder point 32, and the fourth solder point 51 onto the circuit board 9. Then, the first solder point 41 and the second solder point 31, and the third solder point 32 and the fourth solder point 51 are connected by soldering. At the same time, it should be ensured that the second solder point 31 and the third solder point 32 are not connected by soldering, so that the computing device with expandable computing power is in an expanded state.
[0057] This welding method ensures AC conduction between the first RC discrete device 4 and the second RC discrete device 5, while isolating high-speed DC crosstalk between the two signal channels and avoiding signal interference to the other third RC discrete device 3.
[0058] In some embodiments, the circuit board includes a multilayer board structure with no fewer than four layers. The first layer of the board structure closest to the package housing is used for soldering a first solder joint, a second solder joint, a third solder joint, and a fourth solder joint. The circuit board can be a multilayer PCBA board. This multilayer circuit board design reduces electromagnetic interference and improves the thermal management performance of the first, second, and third discrete resistor-capacitor devices on the board.
[0059] In some embodiments, such as Figure 4 As shown, the circuit board 9 comprises a four-layer board structure. The first layer 91, closest to the package housing 8, is used for soldering the first solder joint 41, the second solder joint 31, the third solder joint 32, and the fourth solder joint 51. The second layer 92 serves as the ground reference layer for the first layer 91 and is partially open. The third layer 93 serves as the ground reference layer for the first resistor-capacitor discrete device 4, the second resistor-capacitor discrete device 5, and the third resistor-capacitor discrete device 3. The fourth layer 94, along with the second layer 92, serves as the upper and lower reference layers for the third layer 93, respectively. Within the second layer 92, the positions directly opposite the first resistor-capacitor discrete device 4, the second resistor-capacitor discrete device 5, and the third resistor-capacitor discrete device 3 are partially open, while the remaining space within the second layer 92 can be solid. By using such a hollow design in the second layer 92 board structure, the impedance deviation inside the circuit board 9 can be optimized, and the integrity of high-speed signal transmission of the first RC discrete device 4, the second RC discrete device 5, and the third RC discrete device 3 can be improved.
[0060] It should be noted that, regarding the various steps included in the scalable computing device provided in any of the above embodiments, unless explicitly stated herein, there is no strict order restriction on the execution of these steps; they can be executed in other orders. Furthermore, at least some of these steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.
[0061] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0062] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A computing device with scalable computing power, characterized in that, It includes a circuit board and a first computing chip, a second computing chip, a first RC discrete device, a second RC discrete device, a third RC discrete device, a package housing, a first wire and a second wire mounted on the circuit board; The first, second, and third discrete resistor-capacitor devices are used to isolate DC crosstalk and are located within the package housing. The first end of the first resistor-capacitor discrete device is connected to the first computing chip, and the second end is connected to the first end of the first wire; the first end of the second resistor-capacitor discrete device is connected to the second computing chip, and the second end is connected to the second end of the second wire; the first end of the third resistor-capacitor discrete device is connected to the first end of the first resistor-capacitor discrete device, and the second end is connected to the first end of the second resistor-capacitor discrete device. The outer surface of the package housing is provided with: a first solder joint connected to the second end of the first resistor-capacitor discrete device, a second solder joint connected to the first end of the third resistor-capacitor discrete device, a third solder joint connected to the second end of the third resistor-capacitor discrete device, and a fourth solder joint connected to the second end of the second resistor-capacitor discrete device. The second end of the first wire and the second end of the second wire are used to connect to an external computing power expansion module.
2. The scalable computing power computing device according to claim 1, characterized in that, The first, second, and third discrete RC devices are all independent capacitor elements.
3. The scalable computing power computing device according to claim 1, characterized in that, The first, second, and third discrete resistor-capacitor devices are all independent zero-ohm resistors.
4. The scalable computing power computing device according to claim 1, characterized in that, It also includes a high-speed external interface; The first end of the external high-speed interface is connected to the second end of the first wire, the second end is connected to the second end of the second wire, and the third end is used to connect to the interface of an external computing power expansion module to transmit high-speed signals.
5. The scalable computing power computing device according to claim 4, characterized in that, The external high-speed interface is either a Cooling high-speed interface or a gold finger interface.
6. The computing device with scalable computing power according to claim 4, characterized in that, The third end of the external high-speed interface is not connected to the computing power expansion module interface. The second solder joint is soldered to the third solder joint, so that the computing device is in a non-expansion state. The third resistor-capacitor discrete device is in an AC conduction state, and the first resistor-capacitor discrete device and the second resistor-capacitor discrete device are in an open circuit state. The third discrete resistor-capacitor device is used to isolate DC crosstalk when the first computing chip and the second computing chip interact with each other.
7. The scalable computing power computing device according to claim 4, characterized in that, The third end of the external high-speed interface is connected to the computing power expansion module interface. The first solder point is welded to the second solder point, and the third solder point is welded to the fourth solder point, so that the computing device with expandable computing power is in an expanded state, the third resistor-capacitor discrete device is in an open circuit state, and the first resistor-capacitor discrete device and the second resistor-capacitor discrete device are in an AC conducting state. The first discrete resistor-capacitor device is used to isolate DC crosstalk when the first computing chip and the computing power expansion module interact with each other, and the second discrete resistor-capacitor device is used to isolate DC crosstalk when the second computing chip and the computing power expansion module interact with each other.
8. The computing apparatus with scalable computing power according to any one of claims 6 or 7, characterized in that, The circuit board includes a multi-layered board structure with no less than four layers. The first layer of the board structure closest to the package housing is used to solder the first solder joint, the second solder joint, the third solder joint, and the fourth solder joint.
9. The computing device with scalable computing power according to claim 8, characterized in that, The circuit board has a four-layer multi-layer board structure. The second layer of the board structure near the packaging shell serves as the ground reference layer of the first layer of the board structure. The second layer of the board structure is in a hollow state. The third layer of the board structure serves as the ground reference layer for the first, second, and third discrete resistor-capacitor devices, respectively. The fourth layer of the board structure and the second layer of the board structure serve as the upper and lower reference layers of the third layer of the board structure, respectively.
10. The computing device with scalable computing power according to claim 2, characterized in that, The first, second, and third discrete resistor-capacitor devices have the same capacitance value, which is 0.1 to 0.22 microfarads.