Package assembly

Abstract

Some embodiments of the utility model relate to a packaging assembly. The packaging assembly comprises an insulating substrate, a semiconductor structure, a first conductive wire and a conductive pad. The semiconductor structure is placed in and separated from the insulating substrate. The first conductive line is disposed on a first side of the insulating substrate. The conductive pad is placed on a first side of the semiconductor structure. The first conductive line and the conductive pad comprise the same material. The surface roughness of the conductive pad is greater than the surface roughness of the first conductive line.

Description

Technical Field

[0001] This utility model relates to a packaging component. Background Technology

[0002] The semiconductor industry has experienced rapid development due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. These improvements in integration density stem from iterative reductions in the minimum component size, allowing more components to be integrated into a given area. The growing demand for smaller electronic devices has led to a need for smaller and more innovative semiconductor die packaging technologies. Printed circuit boards (PCBs) are used to electrically connect electronic components and mechanically hold them in place. Utility Model Content

[0003] An embodiment of this utility model discloses a packaging component comprising: an insulating substrate; a semiconductor structure disposed in and separated from the insulating substrate; a first conductive line disposed on a first side of the insulating substrate; and a conductive pad disposed on a first side of the semiconductor structure, wherein the first conductive line and the conductive pad are made of the same material, and the surface roughness of the conductive pad is greater than the surface roughness of the first conductive line.

[0004] An embodiment of this utility model discloses an encapsulation component, which further includes: a first insulating layer covering a first portion of the conductive pad; and a second insulating layer covering a second portion of the conductive pad, the first insulating layer, and a portion of the first conductive wire.

[0005] An embodiment of this utility model discloses a packaging component, which further includes: a second conductive line disposed on a second side of the insulating substrate, wherein the second side of the insulating substrate is opposite to the first side of the insulating substrate.

[0006] An embodiment of this utility model discloses a packaging component, which further includes: at least one third conductive line located on the first side of the insulating substrate and electrically connected to the first conductive line; and at least one fourth conductive line located on the second side of the insulating substrate and electrically connected to the second conductive line.

[0007] An embodiment of this utility model discloses a packaging component, wherein the semiconductor structure is separated from the insulating substrate by an insulating wall.

[0008] An embodiment of this utility model discloses a packaging assembly comprising: a substrate including an insulating portion and a semiconductor portion; a first conductive line disposed on the insulating portion on a first side of the substrate; a second conductive line disposed on the insulating portion on a second side of the substrate, wherein the second side is opposite to the first side; a conductive pad disposed on the semiconductor portion on the first side of the substrate; a conductive path disposed in the insulating portion of the substrate, wherein the conductive path electrically connects the first conductive line to the second conductive line; and an insulating wall disposed between the insulating portion and the semiconductor portion, wherein the surface roughness of the conductive pad is greater than the surface roughness of the first conductive line and the second conductive line.

[0009] An embodiment of this utility model discloses a packaging component, wherein the first conductive line, the second conductive line, and the conductive pad are made of the same material.

[0010] An embodiment of this utility model discloses a packaging component, wherein the thickness of the conductive pad is different from the thickness of the first conductive wire.

[0011] An embodiment of this utility model discloses a packaging component, which further includes: a capacitor placed in the semiconductor portion of the substrate.

[0012] An embodiment of this utility model discloses a packaging component, which further includes: at least one conductive path placed on the first side of the substrate and electrically connected to the first conductive line.

[0013] An embodiment of this utility model discloses a method for fabricating a packaged component, comprising: receiving a substrate, the substrate including a first conductive line on a first side of the substrate, a second conductive line on a second side of the substrate, and a conductive path penetrating the substrate to couple the first conductive line to the second conductive line, wherein the first side of the substrate is opposite to the second side of the substrate; placing a semiconductor structure in the substrate, wherein the semiconductor structure includes a conductive pad on the first side of the semiconductor structure; and fabricating a first redistribution layer (RDL) on the first side of the substrate and fabricating a second RDL on the second side of the substrate, wherein the surface roughness of the conductive pad is different from the surface roughness of the first conductive line and different from the surface roughness of the second conductive line. Attached Figure Description

[0014] When read in conjunction with the accompanying drawings, various aspects of the embodiments of this utility model can be best understood from the following detailed description. It should be noted that, in accordance with standard industrial practice, the various structures are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various structures may be arbitrarily increased or decreased.

[0015] Figures 1 to 11 This is a cross-sectional view illustrating various aspects of a packaged assembly at different manufacturing stages constructed according to one or more embodiments of the present invention.

[0016] Figure 12 This is a flowchart illustrating various aspects of a method for manufacturing a packaged component according to one or more embodiments of the present invention. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples of various components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of the present invention. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, in the following description, embodiments in which a first component is formed on or on a second component may include those in which the first and second components are formed in direct contact, and embodiments in which additional components may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of embodiments of the present invention. This repetition is for simplicity and clarity and is not substantially indicative of a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms (such as "below," "under," "lower part," "above," "above," "upper," etc.) are used herein to describe the relationship of one element or component to another element or component illustrated in the figures. These spatial relative terms are intended to encompass different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptions used herein can therefore be understood in the same manner.

[0019] As used herein, although terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as “first,” “second,” and “third” as used herein do not imply a sequence or order.

[0020] While the numerical ranges and parameters stated in the embodiments of this invention are approximate, the values ​​stated in particular instances should be reported as precisely as possible. However, any numerical value inherently contains a specific error that is necessarily caused by the standard deviation present in the corresponding test measurement. Moreover, as used herein, the terms “substantially,” “about,” or “approximately” generally mean a value or range that would be conceived by one of skill in the art. Alternatively, the terms “substantially,” “about,” or “approximately” mean within an acceptable standard error of the mean as considered by one of skill in the art. Those skilled in the art will understand that acceptable standard errors can vary depending on the technology. Except in operational / working instances, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages (e.g., quantity of material, duration, temperature, operating conditions, ratio of quantities, etc.) disclosed herein should be understood to be modified by the terms “substantially,” “about,” or “approximately” in all instances. Therefore, unless indicated otherwise, the numerical parameters stated in the embodiments of this invention and the appended claims are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted in light of the number of significant digits reported and by applying common rounding techniques. Ranges may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include the endpoints.

[0021] For example, a printed circuit board (PCB) package assembly is used to electrically connect electronic components to the PCB and mechanically secure the electronic components to the PCB. The PCB includes an insulator and conductive lines adhered to the insulator. In some embodiments, the insulator and conductive lines form a complete material layer on a substrate. The substrate may contain active and passive devices (not shown), or it may not contain either active or passive devices, or neither. A wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, etc., can be fabricated using any suitable method. For example, the substrate may contain at least one capacitor embedded therein and coupled to the conductive lines through conductive pads. In some comparative methods, metal diffusion and coefficient of thermal expansion (CTE) mismatch may occur after thermal stress, thereby creating a path between two adjacent conductive pads. Therefore, a method is needed to mitigate this problem.

[0022] Some embodiments of this invention provide a packaging assembly and a method of manufacturing the same that offer one or more improvements over existing methods. Embodiments of this invention relate to a packaging assembly comprising conductive pads of different morphologies for embedded capacitors. In some embodiments, the surface roughness of the conductive pads for embedded capacitors is increased, resulting in increased roughness at the interface between the conductive pads and the insulating layer covering the conductive pads. Therefore, the negative effects caused by CTE mismatch are mitigated, metal diffusion is blocked by the insulating layer, and thus the reliability of the packaging assembly is improved.

[0023] Figures 1 to 11 This is a cross-sectional view illustrating the packaging assembly 120 at different manufacturing stages constructed according to one or more embodiments of the present invention.

[0024] refer to Figure 1 The system provides or receives an insulating substrate 200 (sometimes referred to as a substrate core). The insulating substrate 200 may be an insulating core and may comprise one or more layers of insulating material. In some embodiments, the insulating substrate 200 may comprise, for example, a printed circuit board (PCB) material, a glass fiber reinforced resin material, a deposited film such as Ajinomoto ABF, a pre-impregnated composite fiber (pre-impregnated) material, epoxy resin, molding compound, epoxy molding compound, a polymer material such as polytetrafluoroethylene (PTFE) or polyimide, paper, silica filler, glass fiber, non-woven glass fiber, glass, ceramic, other layers, etc., or combinations thereof. In some embodiments, the insulating substrate 200 may be made of a material that facilitates CTE matching with silicon, but the embodiments of the present invention are not limited thereto.

[0025] The insulating substrate 200 has a first side 202a and a second side 202b opposite to the first side 202a. In some embodiments, seed layers 204a and 204b may be formed on the insulating substrate 200 on the first side 202a and / or the second side 202b. The seed layers 204a and 204b may be one or more copper layers, titanium layers, nickel layers, aluminum layers, or combinations thereof, and are deposited or laminated onto the first side 202a and the second side 202b of the insulating substrate 200. In some embodiments, the insulating substrate 200 and the seed layers 204a and 204b are copper-clad epoxy impregnated glass cloth laminates, copper-clad polyimide impregnated glass cloth laminates, etc. In some embodiments, the insulating substrate 200 and the seed layers 204a and 204b may be a double-sided copper-clad laminate (CCL), such as... Figure 1 As shown in the figure. In some alternative embodiments, the insulating substrate 200 and the seed layers 204a and 204b are single-sided copper-faced plates.

[0026] refer to Figure 2In some embodiments, an opening 205 is formed in the insulating substrate 200 and the seed layers 204a and 204b. In some embodiments, the opening 205 is formed by laser drilling. In other embodiments, mechanical drilling with a drill bit can be used to form the opening 205. The opening 205 can have any top-view shape, such as polygonal, circular, etc. In some embodiments, a cleaning operation can be performed to clean areas near the opening 205 that may have been contaminated by removed material from the insulating substrate 200 and the seed layers 204a and 204b. In some embodiments, the cleaning operation can be a decontamination operation. Decontamination can be performed mechanically (e.g., sandblasting with fine abrasives in a wet slurry), chemically (e.g., rinsing with a combination of organic solvents, permanganates, etc.), or by a combination of mechanical and chemical operations.

[0027] refer to Figure 3 In some embodiments, conductive lines 206a and 206b are formed on a first side 202a and a second side 202b on an insulating substrate 200. Additionally, conductive passages 208 are formed to fill openings 205. The conductive lines 206a and 206b and the conductive passages 208 may comprise copper, titanium, tungsten, aluminum, etc. In some embodiments, the conductive lines 206a and 206b and the conductive passages 208 may be made of the same material or different materials. In some embodiments, the conductive lines 206a and 206b and the conductive passages 208 may be formed by the same operation or different operations. In some embodiments, the conductive passages 208 may be formed prior to the formation of the conductive lines 206a and 206b. In such embodiments, a first plating operation (e.g., electroless plating) may be used to fill openings 205 with a conductive material, thereby forming the conductive passages 208. Additionally, in such embodiments, although not shown, a seed layer may be formed in openings 205 prior to electroless plating. Another plating operation can be performed to create conductive lines 206a and 206b. In such embodiments, a patterned photoresist (not shown) can be formed on seed layers 204a and 204b. The patterned photoresist may have openings exposing seed layers 204a and 204b. Then, conductive material is formed in the openings of the patterned photoresist and on the exposed seed layers 204a and 204b by means of electroplating, electroless plating, etc. In such embodiments, the patterned photoresist and portions of the seed layers 204a and 204b without conductive material are then removed. Figure 3 As shown, the remaining portions of the seed layers 204a and 204b, along with the conductive material, form conductive lines 206a and 206b.

[0028] refer to Figure 4 and Figure 5 ,in Figure 5 yes Figure 4A partially enlarged view of circle A shows, in some embodiments, a semiconductor structure 210 is provided or received. The semiconductor structure 210 may include a semiconductor substrate 212. The semiconductor substrate 212 has a first side 214a and a second side 214b opposite to the first side 214a. In some embodiments, a device may be fabricated in the semiconductor substrate 212. For example, at least one capacitor may be fabricated in the semiconductor substrate 212. Additionally, a capacitor may be fabricated on the first side 214a of the semiconductor substrate 212. A plurality of conductive pads 216 may be fabricated on the first side 214a of the semiconductor substrate 212. Furthermore, the conductive pads 216 are electrically connected to the device (i.e., the capacitor) fabricated in the semiconductor substrate 212. The conductive pads 216 provide electrical connections between the device fabricated in the semiconductor substrate 212 and external components. In some embodiments, the conductive pads 216 may comprise copper, titanium, tungsten, aluminum, etc. Furthermore, the conductive pads 216 may comprise the same material as the conductive lines 206a and 206b and the conductive path 208.

[0029] refer to Figure 6A The top and side surfaces of the conductive pad 216 are exposed. In some embodiments, both the top and side surfaces of the conductive pad 216 are fully exposed. In other embodiments, the conductive pad 216 may be partially embedded in the semiconductor substrate 212; therefore, the top surface of the conductive pad 216 is fully exposed, while the side surfaces of the conductive pad 216 are partially exposed. In some embodiments, the width W of the conductive pad 216 may be between approximately 100 micrometers and approximately 250 micrometers, but the present invention is not limited thereto. In some embodiments, the thickness T of the conductive pad 216 (also referred to as the length of the exposed portion of the side surface) may be between approximately 7 micrometers and approximately 12 micrometers, but the present invention is not limited thereto. In some embodiments, the spacing S between two adjacent conductive pads 216 (e.g., ...) Figure 7 The micrometers (as shown in the illustration) can be between approximately 12 micrometers and approximately 30 micrometers, but the embodiments of this invention are not limited thereto.

[0030] refer to Figure 6A The exposed top and side surfaces of the conductive pad 216 are processed. In some embodiments, processing the surface of the conductive pad 216 includes etching. In some embodiments, etching includes wet etching, but the present invention is not limited thereto. In such embodiments, the exposed top and side surfaces of the conductive pad 216 are processed to increase surface roughness. For example, after surface processing, the arithmetic mean roughness (Ra) of the conductive pad 216 is between approximately 0.3 micrometers and approximately 0.8 micrometers. In some embodiments, multiple teeth or peaks P are obtained by surface processing. The conductive pad 216 is 1 × 1 mm. 2The number of peaks P can be between approximately 300 and approximately 1000. In some embodiments, the height Z measured from the top of peak P to the bottom of the valley between peaks P can be between approximately 0.3 micrometers and approximately 1 micrometer. In embodiments where the surface treatment includes etching, the thickness T of the conductive pad 216 can be greater than 7 micrometers, which can reduce the structural strength of the conductive pad 216 and increase the capacitance of the conductive pad 216.

[0031] refer to Figure 6B In some embodiments, the surface treatment of the conductive pad 216 further includes forming a bonding film 218 on the surface of the conductive pad 216. In such embodiments, the bonding film 218 may comprise copper oxide formed by surface treatment. In some embodiments, the formation of the bonding film 218 is optional.

[0032] Please refer to Figure 7 , Figure 8A and Figure 8B ,in Figure 7 yes Figure 8A and Figure 8B A top view. After the surface of the conductive pad 216 is treated, an insulating layer 220 is formed on the semiconductor substrate 212 on the first side 214a. In some embodiments, the insulating layer 220 may comprise polyimide (PI), but the present invention is not limited thereto. The thickness of the insulating layer 220 may be between approximately 3 micrometers and approximately 11 micrometers. In some embodiments, the insulating layer 220 includes a plurality of openings 221 exposing a portion of each conductive pad 216. In other words, the insulating layer 220 covers another portion of each conductive pad 216, such as... Figure 8A and Figure 8B As shown in the diagram, the length L of the portion of the conductive pad 216 covered by the insulating layer 220 can be between approximately 2.5 micrometers and approximately 10 micrometers. In some comparative methods, when the length L is less than 2.5 micrometers, peeling of the insulating layer 220 may occur, and therefore undesirable connections may occur between two adjacent conductive pads 216. In other comparative methods, when the length L is greater than 10 micrometers, the opening 221 of the insulating layer 220 is not large enough to provide a connection, or further effort may be required during the formation of electrical connections to the conductive pads 216.

[0033] refer to Figure 9 In some embodiments, the semiconductor structure 210 is placed within an insulating substrate 200. In such embodiments, a carrier wafer (not shown) may be provided to support the insulating substrate 200. A portion of the insulating substrate 200 is removed. In some embodiments, a recess may be formed in the insulating substrate 200. In other embodiments, a hollow portion may be formed in the insulating substrate 200. Subsequently, the semiconductor structure 210 is placed within the recess or hollow portion of the insulating substrate 200. Figure 9As shown, the first side 214a of the semiconductor structure 210 and the first side 202a of the substrate 200 face the same direction, while the second side 214b of the semiconductor structure 210 and the second side 202b of the substrate 200 face the same direction. Therefore, the conductive pad 216 and the conductive line 206a are placed on the same side. In some embodiments, the semiconductor structure 210 is separated from the substrate 200. Furthermore, the insulating layer 220 and the conductive pad 216 are separated from the substrate 200 and the conductive lines 206a and 206b.

[0034] In some embodiments, the insulating substrate 200 (as well as the conductive lines 206a and 206b and the conductive path 208) and the semiconductor structure 210 can be fabricated or prepared by different operations; therefore, the thickness of the semiconductor substrate 212 may be different from the thickness of the insulating substrate 200. Furthermore, the thickness T of the conductive pad 216 and the thickness of the insulating layer 220 may be different from the thickness of the conductive line 206a.

[0035] refer to Figure 10 In some embodiments, an insulating material is formed to fill the space between the semiconductor structure 210 and the insulating substrate 200, thereby fixing and embedding the semiconductor structure 210 in the insulating substrate 200. In some embodiments, the insulating material serves as an insulating wall 230, which not only fixes the semiconductor structure 210 in the insulating substrate 200, but also separates the semiconductor structure 210 from the insulating substrate 200.

[0036] refer to Figure 11 An insulating layer 240a, conductive lines 242a, and conductive pathways 244a are formed on a first side 202a of the insulating substrate 200. An insulating layer 240b, conductive lines 242b, and conductive pathways 244b are formed on a second side 202b of the insulating substrate 200. In some embodiments, insulating layers 240a and 240b may be made of ABF, prepreg, molding film, etc. In some embodiments, insulating layers 240a and 240b may be made of polymers such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, insulating layers 240a and 240b may be made of: nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or other suitable materials. Insulating layers 240a and 240b can be fabricated by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, etc., or combinations thereof.

[0037] In some embodiments, conductive lines 242a and 242b and conductive paths 244a and 244b comprise the same material as conductive lines 206a and 206b and conductive pad 216, such as copper, titanium, tungsten, aluminum, alloys thereof, combinations thereof, etc. Conductive lines 242a and 242b and conductive paths 244a and 244b can be fabricated by plating (e.g., electroplating or electroless plating, etc.). As an example, a seed layer (not shown) is fabricated to fabricate conductive lines 242a and 242b and conductive paths 244a and 244b. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer situated on top of the titanium layer. The seed layer can be fabricated using, for example, PVD, etc. A photoresist is then applied to the seed layer and patterned. The photoresist can be applied by spin coating, etc., and can be exposed to allow for patterning. Patterning creates openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. Next, the photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma). Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, by using an acceptable etching process (e.g., wet etching or dry etching). The remaining portions of the seed layer and the conductive material form conductive lines 242a and 242b and conductive pathways 244a and 244b.

[0038] In some embodiments, the insulating layer 240a, conductive wire 242a, and conductive passage 244a are referred to as a redistribution layer (RDL) 246a over the first side 202a, and the insulating layer 240b, conductive wire 242b, and conductive passage 244b are referred to as another RDL 246b over the second side 202b. Any number of insulating layers 240a and 240b, conductive wires 242a and 242b, and conductive passages 244a and 244b may be formed on either or both of the sides 202a and 202b in the RDLs 246a and 246b. Figure 11 The number of components shown is for illustrative purposes only and is not intended to be limiting. Furthermore, RDL 246a and RDL 246b are electrically connected via conductive paths 208 in the insulating substrate 200.

[0039] In some embodiments, solder resist 250a may be formed on a first side 202a of the insulating substrate 200 above the topmost conductive line 242a. A plurality of conductive connectors 252 are formed on RDL 246a and coupled to the insulating substrate 200 via RDL 246a. In some embodiments, under-bump metallization (UBM) may be formed prior to forming the conductive connectors 252. The conductive connectors 252 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, etc. The conductive connectors 252 may comprise conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connectors 252 are formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. After the solder layer is structurally formed, reflow soldering may be performed to shape the conductive material into the desired bump shape. In another embodiment, the conductive connector 252 includes metal pillars (e.g., copper pillars) fabricated by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be fabricated by a plating process.

[0040] In some embodiments, solder resist 250b may be formed on a second side 202b of the insulating substrate 200 above the RDL 246b. In some embodiments, although not shown, a conductive connector may be formed on the RDL 246b and coupled to the insulating substrate 200.

[0041] In some embodiments, two or more core substrates are connected to RDL 246a and 246b via solder joints, etc.

[0042] Therefore, a packaging assembly 120 is provided. The packaging assembly 120 includes an insulating substrate 200, and the insulating substrate 200 has a first side 202a and a second side 202b opposite to the first side 202a. The insulating substrate 200 further includes a plurality of conductive channels 208 disposed and embedded therein. The packaging assembly 120 includes an RDL 246a disposed on the first side 202a and an RDL 246b disposed on the second side 202b.

[0043] like Figure 11As shown, RDL 246a may include a plurality of conductive lines 206a and 242a disposed in insulating layer 240a and connected by conductive path 244a. In some embodiments, conductive line 206a is referred to as the bottom layer of RDL 246a and is coupled to conductive path 208. RDL 246b may include a plurality of conductive lines 206b and 242b disposed in insulating layer 240b and connected by conductive path 244b. Conductive line 206b is referred to as the bottom layer of RDL 246b and is coupled to conductive path 208. Furthermore, RDL 246a and RDL 246b are electrically connected through conductive path 208.

[0044] The package assembly 120 further includes a semiconductor structure 210. The semiconductor structure 210 includes a semiconductor substrate 212 in which means for fabricating, for example, a capacitor are disposed. Figure 11 As shown, although the semiconductor structure 210 is placed within the insulating substrate 200, it is separated from the insulating substrate 200. In some embodiments, the semiconductor structure 210 is separated from the insulating substrate 200 by an insulating wall 230. In some embodiments, the package assembly 120 may be described as including a core substrate, and the core substrate includes an insulating portion 200 and a semiconductor portion 212.

[0045] Semiconductor structure 210 has a first side 214a and a second side 214b. Semiconductor structure 210 may be a die containing a passive device (e.g., but not limited to, a capacitor). In some embodiments, semiconductor structure 210 is placed in an insulating substrate 200, wherein the first side 214a faces the same direction or the same side as the first side 202a of the insulating substrate 200. A plurality of conductive pads 216 are placed on the first side 214a of semiconductor structure 210. An insulating layer 220 is placed on the first side 214a over the conductive pads 216. Furthermore, insulating layer 220 covers a first portion of each conductive pad 216 and exposes another portion of each conductive pad 216. In some embodiments, insulating layer 240a covers a portion of conductive line 206a. Figure 11 As shown, a portion of the pad 216 exposed through insulating layers 220 and 240a is coupled and electrically connected to RDL 246a, while a portion of the conductive line 206a exposed through insulating layer 240a is coupled and electrically connected to RDL 246a.

[0046] In addition, the surface of the semiconductor substrate 212 on the second side 214b can be in complete contact with the insulating layer 240b, but the embodiments of the present invention are not limited thereto.

[0047] In some embodiments, the conductive pad 216 and the conductive wire 206a may comprise the same conductive material. However, the thickness of the conductive pad 216 may differ from the thickness of the conductive wire 206a. Furthermore, the surface roughness of the conductive pad 216 is greater than that of the conductive wire 206a. In some embodiments, the arithmetic mean roughness (Ra) of the conductive pad 216 is between approximately 0.3 micrometers and approximately 0.8 micrometers.

[0048] It should be noted that the conductive pad 216 is in contact with the semiconductor substrate 212, the insulating layer 220, and the insulating layer 240a. Therefore, four different materials with four different CTEs (e.g., the conductive material of the conductive pad, the semiconductor material of the semiconductor substrate 212, the insulating material of the insulating layer 220, and another insulating material of the insulating layer 240a) will exert complex thermal stresses on the conductive pad 216. In some embodiments, the rough surface of the conductive pad 216 provides adhesion between the conductive pad 216 and the insulating layer 220. Therefore, even under such thermal stresses, the insulating layer 220, which provides electrical insulation between the conductive pads 216, is adhered and secured to the conductive pad 216.

[0049] Additionally, during operation, metal diffusion may occur between two adjacent conductive pads 216. However, due to the rough surface of the conductive pads 216, the insulating layer 220, which is adhered to and secured to the conductive pads 216, provides sufficient isolation and thus blocks metal diffusion. As a result, the reliability of the insulating layer 220 and the reliability of the package assembly 120 are improved.

[0050] In some embodiments, the package component 120 can be used in various packages. For example, an integrated circuit package may include multiple integrated circuit dies, such as logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), input / output (I / O) dies, etc., or combinations thereof. Integrated circuit dies may be fabricated in one or more wafers that may be contained in different device regions that can be divided in subsequent steps. Integrated circuit dies may be packaged together with other similar or different integrated circuit dies using manufacturing techniques. This type of integrated circuit package may include a package assembly 120 that provides, for example, electrical paths and connections between logic dies and I / O dies, as well as connections from the integrated circuit package to other components.

[0051] The structure of the embodiments of this utility model is not limited to the embodiments mentioned above, and may have other different embodiments. To simplify the description and facilitate comparison between each embodiment of this utility model, equivalent (or similar) components in each of the following embodiments are labeled with equivalent (or similar) numbers. To make it easier to compare the differences between embodiments, the following description will detail the differences in different embodiments, while equivalent features, values, and definitions will not be repeated.

[0052] Figure 12 This is a flowchart illustrating a method 30 for manufacturing a packaged component according to one or more embodiments of the present invention. Although the disclosed method 30 is illustrated and described herein as a series of actions or operations, it should be understood that the order of the illustrated actions or operations should not be interpreted in a limiting sense. For example, some operations may be performed in a different order and / or simultaneously with other actions or operations besides those illustrated and / or described herein. Furthermore, not all illustrated operations may be required to implement one or more aspects or embodiments of the invention described herein. Additionally, one or more of the operations described herein may be performed in one or more separate operations and / or stages.

[0053] In operation 302, the insulating substrate 200 is received. Figures 1 to 3 The illustration shows a cross-sectional view of an intermediate packaging component 100 according to some embodiments corresponding to operation 302. In some embodiments, operation 302 may include as described above and Figures 1 to 3 Further steps or processes described herein; therefore, for the sake of brevity, those repeated descriptions have been omitted.

[0054] In operation 304, semiconductor structure 210 is placed in a substrate. Figures 4 to 9 The illustration shows a cross-sectional view of the intermediate packaging component 110 according to some embodiments corresponding to operation 304.

[0055] In operation 306, RDL 246a is fabricated on a first side 202a of insulating substrate 200, and RDL 246b is fabricated on a second side 202b of insulating substrate 200. Figure 10 and Figure 11 The illustration shows a cross-sectional view of the intermediate packaging component 120 according to some embodiments corresponding to operation 306.

[0056] The purpose of describing method 30 is to illustrate the concept of the embodiments of the present invention, and the description is not intended to limit the embodiments of the present invention beyond the content expressly stated in the claims. The methods described above and... Figure 12Additional operations are provided before, during, and after the method illustrated in the diagrams, and for additional embodiments of the method, some of the described operations may be replaced, eliminated, or moved.

[0057] According to some embodiments of the present invention, a packaging assembly and a method for manufacturing the same are provided to improve upon existing methods. Embodiments of the present invention relate to a packaging assembly comprising conductive pads of different morphologies for embedded capacitors. In some embodiments, the surface roughness of the conductive pads for embedded capacitors is increased, thereby increasing the adhesion between the conductive pads and the insulating layer covering the conductive pads. Therefore, the negative effects of CTE mismatch are mitigated, metal diffusion can be blocked by the insulating layer, and thus the reliability of the packaging assembly is improved.

[0058] According to some embodiments of the present invention, a packaging assembly is provided. The packaging assembly includes an insulating substrate, a semiconductor structure, a first conductive line, and a conductive pad. The semiconductor structure is placed in and separated from the insulating substrate. The first conductive line is placed on a first side of the insulating substrate. The conductive pad is placed on a first side of the semiconductor structure. The first conductive line and the conductive pad are made of the same material. The surface roughness of the conductive pad is greater than the surface roughness of the first conductive line.

[0059] According to some embodiments of the present invention, a packaging assembly is provided. The packaging assembly includes a substrate, a first conductive line, a second conductive line, a conductive pad, a conductive path, and an insulating wall. The substrate includes an insulating portion and a semiconductor portion. The first conductive line is placed on the insulating portion on a first side of the substrate. The second conductive line is placed on the insulating portion on a second side of the substrate. The conductive pad is placed on the semiconductor portion on the first side of the substrate. The conductive path is placed in the insulating portion of the substrate and electrically connects the first conductive line to the second conductive line. The insulating wall is placed between the insulating portion and the semiconductor portion. The surface roughness of the conductive pad is greater than the surface roughness of the first conductive line and the second conductive line.

[0060] According to some embodiments of the present invention, a method for fabricating a packaged assembly is provided. The method includes the following operations: providing or receiving a substrate. The substrate includes a first conductive line on a first side of the substrate, a second conductive line on a second side of the substrate, and a conductive path penetrating the substrate to couple the first conductive line to the second conductive line. The first side of the substrate is opposite to the second side of the substrate. A semiconductor structure is placed in the substrate. The semiconductor structure includes a conductive pad on the first side of the semiconductor structure. A first RDL is formed on the first side of the substrate, and a second RDL is formed on the second side of the substrate. The surface roughness of the conductive pad is different from the surface roughness of the first conductive line and the second conductive line.

[0061] The foregoing outlines the structure of several embodiments, enabling those skilled in the art to better understand various aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention embodiments as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention embodiments, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention embodiments.

[0062] [Symbol Explanation]

[0063] 30: Method / Disclosed Method

[0064] 100: Intermediate encapsulation component

[0065] 110: Intermediate encapsulation component

[0066] 120: Encapsulated Components

[0067] 200: Substrate / Insulating Substrate / Insulating Part

[0068] 202a: Side / First Side

[0069] 202b: Side / Second Side

[0070] 204a: Seed layer / Exposed seed layer

[0071] 204b: Seed layer / Exposed seed layer

[0072] 205: Opening

[0073] 206a: Conductive wire

[0074] 206b: Conductive wire

[0075] 208: Conductive Path

[0076] 210: Semiconductor Structure

[0077] 212: Semiconductor substrate / semiconductor section

[0078] 214a: First side

[0079] 214b: Second side

[0080] 216: Pad / Conductive Pad

[0081] 218: Bonding membrane

[0082] 220: Insulation layer

[0083] 221: Opening

[0084] 230: Insulating wall

[0085] 240a: Insulation layer

[0086] 240b: Insulation layer

[0087] 242a: Conductive wire / Topmost conductive wire

[0088] 242b: Conductive wire

[0089] 244a: Conductive path

[0090] 244b: Conductive path

[0091] 246a: Re-fabricated layer

[0092] 246b: Re-weave layer

[0093] 250a: Solder resist

[0094] 250b: Solder resist

[0095] 252: Conductive connector

[0096] 302: Operation

[0097] 304: Operation

[0098] 306: Operation

[0099] A: Circle

[0100] L: Length

[0101] P: Peak

[0102] S: Spacing distance

[0103] T: Thickness

[0104] W: Width

[0105] Z: Altitude.

Claims

1. A packaging component, characterized in that... include: Insulating substrate; A semiconductor structure, which is placed in the insulating substrate and separated from the insulating substrate; A first conductive line is placed on a first side of the insulating substrate; and A conductive pad is placed on the first side of the semiconductor structure. The first conductive wire and the conductive pad are made of the same material, and the surface roughness of the conductive pad is greater than that of the first conductive wire.

2. The packaging component according to claim 1, characterized in that... Further includes: A first insulating layer covers a first portion of the conductive pad; and A second insulating layer covers a second portion of the conductive pad, the first insulating layer, and a portion of the first conductive wire.

3. The packaging component according to claim 1, characterized in that... It further includes a second conductive line disposed on a second side of the insulating substrate, wherein the second side of the insulating substrate is opposite to the first side of the insulating substrate.

4. The packaging component according to claim 3, characterized in that... Further includes: At least one third conductive line is located on the first side of the insulating substrate and electrically connected to the first conductive line; and At least one fourth conductive line is located on the second side of the insulating substrate and electrically connected to the second conductive line.

5. The packaging component according to claim 1, characterized in that... The semiconductor structure is separated from the insulating substrate by an insulating wall.

6. A packaging component, characterized in that... include: A substrate, comprising an insulating portion and a semiconductor portion; A first conductive line is placed on the insulating portion on a first side of the substrate; A second conductive line is placed on the insulating portion on a second side of the substrate, wherein the second side is opposite to the first side; A conductive pad is placed on the semiconductor portion on the first side of the substrate; A conductive path is placed in the insulating portion of the substrate, wherein the conductive path electrically connects the first conductive line to the second conductive line; and An insulating wall is placed between the insulating portion and the semiconductor portion. The surface roughness of the conductive pad is greater than that of the first conductive wire and the second conductive wire.

7. The packaging component according to claim 6, characterized in that... The first conductive wire, the second conductive wire, and the conductive pad are made of the same material.

8. The packaging component according to claim 6, characterized in that... The thickness of the conductive pad is different from the thickness of the first conductive wire.

9. The packaging component according to claim 6, characterized in that... It further includes a capacitor placed in the semiconductor portion of the substrate.

10. The packaging component according to claim 6, characterized in that... It further includes at least one conductive path placed on the first side of the substrate and electrically connected to the first conductive line.

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