Single-phase PFC power factor correction circuit

Abstract

The utility model discloses a single-phase PFC (Power Factor Correction) circuit, which comprises a rectification filter circuit, an input voltage sampling circuit, a booster circuit, a PFC chip circuit, a voltage division circuit, a voltage regulation circuit and a voltage output end 80, the voltage input end of the rectification filter circuit is connected to the power grid commercial power, and the voltage output end is a DC output end. One end of the input voltage sampling circuit is electrically connected to the input end of a rectifier bridge in the rectifier filter circuit, the other end of the input voltage sampling circuit is electrically connected to the PFC chip circuit, and the input voltage sampling circuit feeds back a sampling signal of the voltage of the input end of the rectifier bridge of the rectifier filter circuit to the voltage regulation circuit. Under the condition that the circuit mode is not changed, by adding components and reasonably setting the PFC circuit layout, the technical difficulty is solved, and the purposes of small size, light weight and high conversion efficiency are achieved.

Description

Technical Field

[0001] This utility model relates to a switching power supply technology, and more particularly to a single-phase PFC power factor correction circuit. Background Technology

[0002] Currently, various countries have strict regulations regarding the power factor and harmonic requirements of switching power supplies when connected to the power grid. To ensure compatibility with different national power grids, power supply manufacturers typically set the input voltage range to AC 176-264VAC. Based on this, the output voltage of the PFC circuit must reach at least 400VDC at 264VAC. Simultaneously, when compatible with an input voltage of 164VAC, the duty cycle of the switching MOSFET Q1 in the PFC circuit will vary significantly. Therefore, the boost inductor in the circuit will also be large, increasing its weight and causing a significant increase in core temperature, ultimately reducing the overall conversion efficiency.

[0003] Furthermore, the increasing output power of PFC within the same volume also necessitates enhanced heat dissipation capabilities in PFC circuits. Existing PFC circuits struggle to meet these requirements.

[0004] In view of the above, this utility model is hereby proposed. Utility Model Content

[0005] The purpose of this invention is to provide a single-phase PFC power factor correction circuit to solve the aforementioned technical problems existing in the prior art.

[0006] The objective of this utility model is achieved through the following technical solution:

[0007] The single-phase PFC power factor correction circuit of this utility model includes a rectifier filter circuit 20, an input voltage sampling circuit 30, a boost circuit 40, a PFC chip circuit 50, a voltage divider circuit 60, a voltage regulation circuit 70, a diode D1, a capacitor C7, a capacitor C8, a resistor R8, an electrolytic capacitor EC1, and a voltage output terminal 80.

[0008] The voltage input terminal 10 of the rectifier and filter circuit 20 is connected to the mains power grid, and the voltage output terminal 80 is a DC output terminal.

[0009] One end of the input voltage sampling circuit 30 is electrically connected to the input terminal of the rectifier bridge in the rectifier filter circuit 20, and the other end of the input voltage sampling circuit 30 is electrically connected to the PFC chip circuit 50. The sampling signal of the voltage at the input terminal of the rectifier bridge of the rectifier filter circuit 20 is fed back by the input voltage sampling circuit 30 to the voltage regulation circuit 70.

[0010] Compared with the prior art, the single-phase PFC power factor correction circuit provided by this utility model can solve the technical difficulties by adding components and reasonably setting the PFC circuit layout without changing the circuit mode, and achieve the purpose of small size, light weight and high conversion efficiency. Attached Figure Description

[0011] Figure 1 A schematic diagram of a single-phase PFC power factor correction circuit provided for an embodiment of this utility model.

[0012] In the picture:

[0013] 20. Rectifier and filter circuit; 30. Input voltage sampling circuit; 40. Boost circuit; 50. PFC chip circuit; 60. Voltage divider circuit; 70. Voltage regulation circuit; 80. Voltage output terminal; 10. Voltage input terminal of rectifier and filter circuit 20. Detailed Implementation

[0014] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments, which do not constitute a limitation on the present utility model. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0015] First, the following explanations are provided for the terms that may be used in this article:

[0016] The contents not described in detail in the embodiments of this utility model are existing technologies known to those skilled in the art. Where specific conditions are not specified in the embodiments of this utility model, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this utility model whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0017] The single-phase PFC power factor correction circuit of the present invention includes a rectifier filter circuit 20, an input voltage sampling circuit 30, a boost circuit 40, a PFC chip circuit 50, a voltage divider circuit 60, a voltage regulation circuit 70, a diode D1, a capacitor C7, a capacitor C8, a resistor R8, an electrolytic capacitor EC1, and a voltage output terminal 80.

[0018] The voltage input terminal 10 of the rectifier and filter circuit 20 is connected to the mains power grid, and the voltage output terminal 80 is a DC output terminal.

[0019] One end of the input voltage sampling circuit 30 is electrically connected to the input terminal of the rectifier bridge in the rectifier filter circuit 20, and the other end of the input voltage sampling circuit 30 is electrically connected to the PFC chip circuit 50. The sampling signal of the voltage at the input terminal of the rectifier bridge of the rectifier filter circuit 20 is fed back by the input voltage sampling circuit 30 to the voltage regulation circuit 70.

[0020] The input voltage sampling circuit 30 includes resistors R4, R5, R6, and R7, as well as capacitors C2 and C5.

[0021] Resistor R4 and capacitor C2 are connected in parallel and then in series with resistor R5. One end of the series is connected to the input circuit L, and the other end is grounded.

[0022] Resistor R7 and capacitor C5 are connected in parallel and then in series with resistor R6. One end of the series circuit is connected to the input circuit N, and the other end is grounded.

[0023] The voltage regulation circuit 70 includes a resistor R9 and a MOSFET Q1. The gate of the MOSFET Q1 is connected to the GD pin of the PFC chip circuit via the resistor R9. The source of the MOSFET Q1 is connected to the boost circuit 40, and the drain of the MOSFET Q1 is grounded.

[0024] The boost circuit 40 includes an inductor L2 and a diode D2;

[0025] After inductor L2 and diode D2 are connected in series, one end is connected to the voltage output terminal and the other end is connected to the rectifier bridge output terminal;

[0026] The common terminal of the inductor L2 and the diode D2 is connected to the source S of the MOSFET Q1.

[0027] The rectifier and filter circuit 20 includes capacitors C1, C3, C4, and C6, a common-mode inductor L1, a resistor R3, and a rectifier bridge BD1.

[0028] Capacitor C1 and resistor R3 are connected in parallel between input circuit L and N; common-mode inductor L1 is connected in series between L and N.

[0029] One end of capacitor C3 is connected to L, and the other end is grounded; one end of capacitor C4 is connected to N, and the other end is grounded; capacitor C6 is connected in parallel between L and N; in the above structure, the rectifier bridge is a bridge rectifier circuit BD1.

[0030] The voltage divider circuit 60 includes resistors R10 and R11, and is disposed between the voltage regulation circuit 70 and the voltage output terminal 80.

[0031] The PFC chip circuit 50 includes a chip U1, and the GD pin of the chip U1 is connected to the gate of the MOS transistor Q1 via a resistor R9.

[0032] The electrolytic capacitor EC1 is connected in parallel across the voltage divider circuit 60, with DC voltage applied to its positive terminal and grounded to its negative terminal.

[0033] The circuit adopts a vertical multi-layer layout. The bottom layer uses an aluminum substrate, and the MOSFET, sampling resistor, power inductor and diode are placed on the bottom plate. The PFC chip circuit 50 is placed on the top layer.

[0034] In summary, the single-phase PFC power factor correction circuit of this invention can solve technical difficulties and achieve the goals of small size, light weight, and high conversion efficiency by adding or replacing components and reasonably setting the PFC circuit layout without changing the circuit mode.

[0035] To more clearly demonstrate the technical solution and its effects provided by the present invention, the embodiments of the present invention will be described in detail below with reference to specific examples.

[0036] Example 1

[0037] like Figure 1 As shown:

[0038] A PFC circuit includes a rectifier-filter circuit 20, an input voltage sampling circuit 30, a boost circuit 40, a PFC chip circuit 50, a voltage divider circuit 60, a voltage regulation circuit 70, and a voltage output terminal 80. The voltage input terminal 10 of the rectifier-filter circuit 20 is connected to the mains power grid, and after rectification and filtering, DC output is achieved at the voltage output terminal 80. One end of the input voltage sampling circuit 30 is electrically connected to the input terminal of the rectifier bridge BD1 in the rectifier-filter circuit 20, and the voltage after voltage division is fed back to the PFC chip circuit to regulate the voltage at the voltage output terminal 80. The PFC chip circuit 50 includes a chip U1, which is a TAE32F5300 chip.

[0039] In this embodiment, the 220V AC power is processed by the input voltage sampling circuit 30, the PFC chip circuit 50, and the voltage regulation circuit 70 in conjunction with a traditional PFC circuit, thereby improving the conversion efficiency. The specific structures of the input voltage sampling circuit 30 and the voltage regulation circuit 70 will be further described below.

[0040] More specifically, the input voltage sampling circuit 30 includes resistors R4, R5, R6, and R7, and capacitor C2. Capacitor C5, resistor R4, and capacitor C2 are connected in parallel and then in series with resistor R5; one end of the series connection is to the input circuit L, and the other end is grounded. Resistor R7 is connected in parallel with capacitor C5 and then in series with resistor R6; one end of the series connection is to the input circuit N, and the other end is grounded. The common terminal of R4 and R5 is connected to the L sampling terminal of the PFC chip circuit, and the common terminal of R6 and R7 is connected to the N sampling terminal of the PFC chip circuit. The sampled voltage enters the PFC chip circuit for voltage loop calculation, controlling the GN terminal to output a control signal with a certain duty cycle to the voltage regulation circuit 70, thereby increasing the voltage on output EC1 to 400VDC.

[0041] Continue to refer to Figure 1 As shown, the PFC circuit also includes a boost circuit 40, a resistor R8, and a diode D1.

[0042] The boost circuit 40 includes an inductor L2 and a diode D2. The inductor L2 and diode D2 are connected in series, with one end connected to the voltage output terminal and the other end connected to the rectifier bridge output terminal. The common terminal of the inductor L2 and diode D2 is connected to the source S of the MOSFET Q1. A planar inductor L2 is used to reduce its size. The switching on and off of the MOSFET Q1 controls the voltage across the inductor L2, causing the voltage across the diode D2 to rise to 400VDC. A resistor R8 is connected at one end to the I- terminal of the PFC chip circuit and at the other end to the GND terminal of the PFC chip circuit. By sampling the current in the loop, it sends the current to the chip to achieve overcurrent protection. One end of the diode D1 is connected to the output terminal of the rectifier filter circuit, and the other end is connected to the voltage output terminal 80, providing a high-frequency bypass (detour) for the inductor L2, thereby reducing the loss of the inductor L2 at high frequencies and improving the overall efficiency and performance of the system.

[0043] Furthermore, the rectifier and filter circuit includes capacitors C1, C3, C4, and C6, inductor L1, resistor R3, and rectifier bridge BD1. Capacitor C1 and resistor R3 are connected in parallel between input circuits L and N; common-mode inductor L1 is connected in series between L and N; one end of capacitor C3 is connected to L, and the other end is grounded; one end of capacitor C4 is connected to N, and the other end is grounded; capacitor C6 is connected in parallel between L and N. In the above structure, the rectifier bridge is a bridge rectifier circuit BD1. Safety capacitors C1, C3, C4, and C6, and common-mode inductor L1 serve as power supply filters, respectively filtering common-mode and differential-mode interference.

[0044] The voltage divider circuit 60, consisting of resistors R10 and R11, is positioned between the voltage regulation circuit and the voltage output terminal. The common terminal of resistors R10 and R11 is connected to the OUT terminal of the PFC chip circuit 50 to monitor the output DC voltage. The feedback value is used to calculate the output duty cycle of the PFC chip, and simultaneously provides overvoltage and undervoltage protection.

[0045] Furthermore, the PFC circuit also includes an electrolytic capacitor EC1; the electrolytic capacitor EC1 is connected in parallel across the voltage divider circuit 60, with a DC voltage applied to its positive terminal and grounded to its negative terminal.

[0046] The PFC circuit adopts a vertical multi-layer layout. The bottom layer uses an aluminum substrate, and devices that generate a lot of heat, such as MOSFETs, sampling resistors, power inductors and diodes, are placed on the bottom plate. The PFC chip circuit and other components are placed on the top layer, which reduces the overall size of the PFC while ensuring the heat dissipation capacity of the PFC module.

[0047] In the circuit structure described above, combined with Figure 1 As shown, the mains power enters through the L and N ports of the power supply terminal, passes through fuse F1, pre-charges the circuit via switch K1 and resistor R2, and is rectified by rectifier and filter circuit 20. After high-frequency filtering by capacitor C7, it becomes pulsating DC power, which is then sent to the input terminal of freewheeling inductor L2. Chip U1 starts working after acquiring the input voltage. Its GD pin outputs a continuous pulse wave through resistor R9 to control the conduction and cutoff of MOSFET Q1. A pulse current flows through freewheeling inductor L2, through MOSFET Q1 to ground, increasing the voltage at the output terminal of freewheeling inductor L2. This voltage is then rectified by diode D2 and filtered by EC1 to become 400V DC power. Furthermore, resistors R4, R5, R6, and R7, along with capacitors C2 and C5, form input voltage sampling circuit 30, and resistor R8 samples the current change in freewheeling inductor L1. By sampling the voltage output terminal 80 through resistors R10 and R11, the signal is fed back to the OUT pin of U1. The pulse width of GD is adjusted to stabilize the output voltage at 400VDC. This reduces the duty cycle of the freewheeling inductor L1. Furthermore, by replacing the inductor with a planar inductor, the size and weight of the inductor itself will be reduced.

[0048] The beneficial effects of this utility model are that, without changing the circuit pattern, it solves the technical difficulties by adding or replacing components and rationally setting the PFC circuit layout, achieving the goal of small size, light weight, and high conversion efficiency.

[0049] The above description is merely a preferred embodiment of this utility model, but the scope of protection of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this utility model should be included within the scope of protection of this utility model. Therefore, the scope of protection of this utility model should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of this utility model and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A single-phase PFC power factor correction circuit, characterized in that, It includes a rectifier filter circuit (20), an input voltage sampling circuit (30), a boost circuit (40), a PFC chip circuit (50), a voltage divider circuit (60), a voltage regulation circuit (70), a diode D1, a capacitor C7, a capacitor C8, a resistor R8, an electrolytic capacitor EC1, and a voltage output terminal (80). The voltage input terminal (10) of the rectifier filter circuit (20) is connected to the mains power grid, and the voltage output terminal (80) is a DC output terminal; One end of the input voltage sampling circuit (30) is electrically connected to the input terminal of the rectifier bridge in the rectifier filter circuit (20), and the other end of the input voltage sampling circuit (30) is electrically connected to the PFC chip circuit (50). The sampling signal of the voltage at the input terminal of the rectifier bridge of the rectifier filter circuit (20) is fed back to the voltage regulation circuit (70).

2. The single-phase PFC power factor correction circuit according to claim 1, characterized in that, The input voltage sampling circuit (30) includes resistors R4, R5, R6, and R7, as well as capacitors C2 and C5. Resistor R4 and capacitor C2 are connected in parallel and then in series with resistor R5. One end of the series is connected to the input circuit L, and the other end is grounded. Resistor R7 and capacitor C5 are connected in parallel and then in series with resistor R6. One end of the series circuit is connected to the input circuit N, and the other end is grounded.

3. The single-phase PFC power factor correction circuit according to claim 2, characterized in that, The voltage regulation circuit (70) includes a resistor R9 and a MOS transistor Q1. The gate of the MOS transistor Q1 is connected to the GD pin of the PFC chip circuit via the resistor R9. The source of the MOS transistor Q1 is connected to the boost circuit (40). The drain of the MOS transistor Q1 is grounded.

4. The single-phase PFC power factor correction circuit according to claim 3, characterized in that, The boost circuit (40) includes an inductor L2 and a diode D2; After inductor L2 and diode D2 are connected in series, one end is connected to the voltage output terminal and the other end is connected to the rectifier bridge output terminal; The common terminal of the inductor L2 and the diode D2 is connected to the source S of the MOSFET Q1.

5. The single-phase PFC power factor correction circuit according to claim 4, characterized in that, The rectifier and filter circuit (20) includes capacitors C1, C3, C4, and C6, a common-mode inductor L1, a resistor R3, and a rectifier bridge BD1. Capacitor C1 and resistor R3 are connected in parallel between input circuit L and N; common-mode inductor L1 is connected in series between L and N. One end of capacitor C3 is connected to L, and the other end is grounded; one end of capacitor C4 is connected to N, and the other end is grounded. Capacitor C6 is connected in parallel between L and N; in the above structure, the rectifier bridge is a bridge rectifier circuit BD1.

6. The single-phase PFC power factor correction circuit according to claim 5, characterized in that, The voltage divider circuit (60) includes resistors R10 and R11, which are disposed between the voltage regulation circuit (70) and the voltage output terminal (80).

7. The single-phase PFC power factor correction circuit according to claim 6, characterized in that, The PFC chip circuit (50) includes a chip U1, and the GD pin of the chip U1 is connected to the gate of the MOS transistor Q1 via a resistor R9.

8. The single-phase PFC power factor correction circuit according to claim 7, characterized in that, The electrolytic capacitor EC1 is connected in parallel across the voltage divider circuit (60), with DC voltage applied to its positive terminal and grounded to its negative terminal.

9. The single-phase PFC power factor correction circuit according to any one of claims 1 to 8, characterized in that, The circuit adopts a vertical multi-layer layout. The bottom layer uses an aluminum substrate, and the MOS transistor, sampling resistor, power inductor and diode are placed on the bottom plate. The PFC chip circuit (50) is placed on the top layer.

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