Semiconductor device structure

Abstract

A semiconductor device structure is provided. A structure includes a device layer, an interconnect structure including a plurality of metal layers disposed on the device layer, and an ultra-thick metal structure disposed on the interconnect structure. The ultra-thick metal structure includes a first ultra-thick metal feature having a first width, and a second ultra-thick metal feature disposed around the first ultra-thick metal feature, where the second ultra-thick metal feature has a second width less than the first width, the second ultra-thick metal feature being separated from the first ultra-thick metal feature by a dielectric layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of devices to solve problems in many different fields, including radio frequency (RF) communications. The increasing popularity of these devices has also created a demand for improvements in the semiconductor manufacturing processes of RF ICs. Some RF circuits use thick metal layers to achieve inductive and other properties. However, the device geometry of next-generation ICs with smaller dimensions presents new constraints. Therefore, improvements in semiconductor device structure and process technology are needed. Utility Model Content

[0003] This disclosure provides a semiconductor device structure. The semiconductor device structure includes a device layer, an interconnect structure, and an ultra-thick metal structure. The interconnect structure includes multiple metal layers disposed on the device layer. The ultra-thick metal structure is disposed on the interconnect structure and includes a first ultra-thick metal feature and a second ultra-thick metal feature. The first ultra-thick metal feature has a first width. The second ultra-thick metal feature is disposed around the first ultra-thick metal feature, wherein the second ultra-thick metal feature has a second width smaller than the first width, and the second ultra-thick metal feature is separated from the first ultra-thick metal feature by a dielectric layer.

[0004] This disclosure also provides a semiconductor device structure. The semiconductor device structure includes an interconnect structure, a first ultra-thick metal structure, and a second ultra-thick metal structure. The interconnect structure includes multiple metal layers disposed on a device layer. The first ultra-thick metal structure is disposed on the interconnect structure and includes a first ultra-thick metal feature and a second ultra-thick metal feature. The second ultra-thick metal feature is adjacent to the first ultra-thick metal feature, wherein a first dielectric layer is between the first ultra-thick metal feature and the second ultra-thick metal feature, and the second ultra-thick metal feature has a second width smaller than a first width of the first ultra-thick metal feature. The second ultra-thick metal structure is disposed on the first ultra-thick metal structure and includes a third ultra-thick metal feature and a fourth ultra-thick metal feature. The fourth ultra-thick metal feature is disposed around the third ultra-thick metal feature, wherein the fourth ultra-thick metal feature is separated from the third ultra-thick metal feature by a second dielectric layer.

[0005] This disclosure provides another semiconductor device structure. The semiconductor device structure includes a device layer, an interconnect structure, a first ultra-thick metal structure, a second ultra-thick metal structure, and a third ultra-thick metal structure. The interconnect structure is on the device layer. The first ultra-thick metal structure is on the interconnect structure, wherein the first ultra-thick metal structure includes a first ultra-thick metal feature, a second ultra-thick metal feature disposed around the first ultra-thick metal feature, and a first dielectric layer separating the first ultra-thick metal feature and the second ultra-thick metal feature, wherein the second ultra-thick metal feature has a second width smaller than the first width of the first ultra-thick metal feature. The second ultra-thick metal structure is on the first ultra-thick metal structure, wherein the second ultra-thick metal structure includes a third ultra-thick metal feature, a fourth ultra-thick metal feature disposed around the third ultra-thick metal feature, and a second dielectric layer separating the third ultra-thick metal feature and the fourth ultra-thick metal feature. The third ultra-thick metal structure is on the second ultra-thick metal structure, wherein the third ultra-thick metal structure includes a fifth ultra-thick metal feature, a sixth ultra-thick metal feature disposed around the fifth ultra-thick metal feature, and a third dielectric layer separating the fifth ultra-thick metal feature and the sixth ultra-thick metal feature. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features may not be drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A This is a perspective view of one of the various stages of manufacturing a semiconductor device structure according to some implementation methods.

[0008] Figure 1B It is based on some implementation methods along Figure 1A A cross-sectional side view of the stage of manufacturing a semiconductor device structure cut out from the cross-section BB;

[0009] Figures 2 to 6 , Figures 9 to 12 and Figure 15 This is a cross-sectional side view of various stages of manufacturing a semiconductor device structure according to some embodiments;

[0010] Figure 7A and Figure 7B It is based on some implementation methods along Figure 6 A top view of a portion of the semiconductor device structure cut out by cross-section AA;

[0011] Figure 8 It is based on some implementation methods along Figure 6 A top view of a portion of the semiconductor device structure cut out from the cross section BB;

[0012] Figure 13A and Figure 13B It is based on some implementation methods along Figure 12 A top view of a portion of a semiconductor device structure cut out by a cross-section CC;

[0013] Figure 14 It is based on some implementation methods along Figure 12 A top view of a portion of the semiconductor device structure cut out by the cross-section DD;

[0014] Figure 16 It is based on Figure 15 A perspective view of a portion of the first ultra-thick metal structure and a portion of the second ultra-thick metal structure in the illustrated embodiment;

[0015] Figures 17 to 23 This is an exemplary configuration of an ultra-thick metal structure according to some implementation methods.

[0016] [Symbol Explanation]

[0017] 100: Semiconductor device structure

[0018] 102: Substrate

[0019] 108: Passage Area

[0020] 114: Quarantine Area

[0021] 122: Gate interstitial material

[0022] 123: Spacer in the fin sidewall

[0023] 124: Source / Drain Region

[0024] 126: Contact Etching Stop Layer

[0025] 128: Interlayer dielectric layer

[0026] 136: Gate dielectric layer

[0027] 138: Gate electrode layer

[0028] 140: Gate Stack

[0029] 142: Source / Drain Contact

[0030] 144: Silicide layer

[0031] 200: Device Layer

[0032] 202: Intermetallic dielectric layer

[0033] 204: Metal Wire

[0034] 206: Through hole

[0035] 222: End

[0036] 224: End

[0037] 232: End

[0038] 234: End

[0039] 250: Interconnection Structure

[0040] 250-1: Metal M1 layer

[0041] 250-2: Metal M2 layer

[0042] 250-3: Metal M3 layer

[0043] 250t: Metal Mtop layer

[0044] 255: First etch stop layer

[0045] 260: The first ultra-thick metal structure

[0046] 260': The first ultra-thick metal structure

[0047] 260-A: The first ultra-thick metal structure

[0048] 261: First dielectric layer

[0049] 262: Barrier Layer

[0050] 263: Extra-thick metal trench

[0051] 263-1: Ultra-thick metal trench

[0052] 263-2: Ultra-thick metal trench

[0053] 263-3: Ultra-thick metal trench

[0054] 263-4: Ultra-thick metal trench

[0055] 263a: Opening

[0056] 263b: Opening

[0057] 264: Seed layer

[0058] 266: Ultra-thick metal layer

[0059] 266'-1: Features of ultra-thick metal

[0060] 266-1: Features of ultra-thick metals

[0061] 266'-2: Features of ultra-thick metal

[0062] 266-2: Features of ultra-thick metals

[0063] 266'-3: Features of ultra-thick metal

[0064] 266-3: Features of ultra-thick metals

[0065] 266'-4: Features of ultra-thick metal

[0066] 266-4: Features of ultra-thick metals

[0067] 266-5: Features of ultra-thick metals

[0068] 270: Second ultra-thick metal structure

[0069] 270': Second ultra-thick metal structure

[0070] 270-A: The first ultra-thick metal structure

[0071] 271: Second dielectric layer

[0072] 272: Barrier Layer

[0073] 273: Extra-thick metal trench

[0074] 273-1: Ultra-thick metal trench

[0075] 273-2: Ultra-thick metal trench

[0076] 273-3: Ultra-thick metal trench

[0077] 273-4: Ultra-thick metal trench

[0078] 273a: Opening

[0079] 273b: Opening

[0080] 274: Seed layer

[0081] 275: Second etch stop layer

[0082] 276: Ultra-thick metal layer

[0083] 276'-1: Features of ultra-thick metal

[0084] 276-1: Features of ultra-thick metals

[0085] 276'-2: Features of ultra-thick metal

[0086] 276-2: Characteristics of ultra-thick metals

[0087] 276'-3: Features of ultra-thick metal

[0088] 276-3: Characteristics of ultra-thick metal

[0089] 276'-4: Features of ultra-thick metal

[0090] 276-4: Characteristics of ultra-thick metal

[0091] 276-5: Features of ultra-thick metals

[0092] 282: Dielectric layer

[0093] 290: Conductive structure

[0094] 2002: Ultra-thick metal structure

[0095] 2004: Ultra-thick metal structure

[0096] 2056a: First columnar structure

[0097] 2056b: Second columnar structure

[0098] 2056c: Third columnar structure

[0099] 2056d: Fourth columnar structure

[0100] 2066a: First columnar structure

[0101] 2066b: Second columnar structure

[0102] 2200: Ultra-thick metal structure

[0103] 2202: The First Ultra-Thick Metal Structure

[0104] 2204: The Second Ultra-Thick Metal Structure

[0105] 2300: Ultra-thick metal structure

[0106] 2302: The First Ultra-Thick Metal Structure

[0107] 2304: The Second Ultra-Thick Metal Structure

[0108] 2400: Ultra-thick metal structure

[0109] 2402: The First Ultra-Thick Metal Structure

[0110] 2404: The second ultra-thick metal structure

[0111] A1: Surface area

[0112] A2: Surface area

[0113] A3: Surface area

[0114] AA: Cross-section

[0115] BB: Cross-section

[0116] CC: Cross section

[0117] D1: Distance

[0118] D2: Distance

[0119] D3: Distance

[0120] D4: Distance

[0121] D5: Distance

[0122] DD: Cross section

[0123] P1: Line spacing

[0124] P2: Line spacing

[0125] W1: Width

[0126] W1a: First width

[0127] W1b: Second width

[0128] W2: Width

[0129] W2a: First width

[0130] W2b: Second Width

[0131] W3: Width

[0132] W4: Width

[0133] X: Axis

[0134] Y: axis

[0135] Z: Axis Detailed Implementation

[0136] The following disclosure provides numerous different implementations or examples for achieving different features of the provided object. Specific examples of elements and configurations are described below to simplify the content of this disclosure. Of course, these are merely examples and not limitations. For example, in the following description, forming a first feature on or above a second feature can include implementations where the first and second features are formed in direct contact, or implementations where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various implementations. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various implementations and / or configurations discussed.

[0137] In addition, spatial relative terms, such as “below,” “down,” “below,” “above,” “up,” “above,” “above,” “top,” etc., may be used herein to describe the relationship between one element or feature and another shown in the figures. Besides the orientations described in the figures, spatial relative terms are also intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein shall be interpreted accordingly.

[0138] Figure 1A The stages of manufacturing a semiconductor device structure 100 are shown. The semiconductor device structure 100 includes a device layer 200 and an interconnect structure 250. Figure 1B A cross-sectional view of a device layer 200 according to some embodiments is shown. The device layer 200 includes a substrate 102 and one or more devices formed within or on the substrate 102. The substrate 102 may be a semiconductor substrate. In some embodiments, the substrate 102 includes a single-crystal semiconductor layer at least on its surface. The substrate 102 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium antimonide arsenide (GaAsSb), and indium phosphide (InP). For example, the substrate 102 is made of silicon.

[0139] The substrate 102 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type impurities). For example, the dopant is phosphorus for an n-type fin field-effect transistor (FinFET) and boron for a p-type fin field-effect transistor.

[0140] Device layer 200 may include any suitable device, such as a transistor, diode, image sensor, resistor, capacitor, inductor, memory cell, or combination thereof. In some embodiments, device layer 200 includes transistors, such as planar field-effect transistors (FETs), fin field-effect transistors, complementary FETs (CFETs), forksheet FETs, nanostructure transistors, or other suitable transistors. Nanostructure transistors may include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a channel surrounded by a gate electrode. An example of a device formed on substrate 102 is a fin field-effect transistor, such as... Figure 1A and Figure 1B As shown. Device layer 200 includes source / drain (S / D) region 124 and gate stack 140. Figure 1A (Only one is illustrated in the figure). Each gate stack 140 can be disposed between a source / drain region 124 that serves as a source region and a source / drain region 124 that serves as a drain region. For example, each gate stack 140 can extend along the Y-axis between one or more source / drain regions 124 that serve as source regions and one or more source / drain regions 124 that serve as drain regions. Figure 1B As shown, two gate stacks 140 are formed on substrate 102. In some embodiments, more than two gate stacks 140 are formed on substrate 102. Although not shown, a channel region is formed between source / drain regions 124, and at least three surfaces of the channel region are covered by the gate stacks 140.

[0141] The source / drain region 124 may include a semiconductor material, such as Si or Ge, a III-V compound semiconductor, a II-VI compound semiconductor, or other suitable semiconductor materials. Exemplary source / drain regions 124 may include, but are not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, etc. The source / drain region 124 may include p-type dopants, such as boron; N-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, or combinations thereof. The source / drain region 124 may be formed by epitaxial growth methods using chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The channel region may include one or more semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. The channel region may include the same semiconductor material as the substrate 102. In some embodiments, the device layer 200 may include fin field-effect transistors, and the channel region is a plurality of fins disposed below the gate stack 140. In some embodiments, the device layer 200 may include nanostructured transistors, and the channel region is surrounded by the gate stack 140.

[0142] like Figure 1A and Figure 1BAs shown, each gate stack 140 includes a gate electrode layer 138 disposed on the channel region (or around the channel region of the nanostructure transistor). The gate electrode layer 138 may be a metal-containing material, such as tungsten, cobalt, aluminum, ruthenium, copper, or multiples thereof, and may be deposited by atomic layer deposition, plasma-enhanced chemical vapor deposition (PECVD), molecular beam deposition (MBD), physical vapor deposition (PVD), or any suitable deposition technique. The gate stack 140 may also include a gate dielectric layer 136 disposed on the channel region. The gate electrode layer 138 may be disposed on the gate dielectric layer 136. In some embodiments, an interface layer (not shown) may be disposed between the channel region 108 and the gate dielectric layer 136, and one or more work function layers (not shown) may be formed between the gate dielectric layer 136 and the gate electrode layer 138. The dielectric layer at the interface may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, or multiple layers thereof, and may be formed by any suitable deposition method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. The gate dielectric layer 136 may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, a high-k dielectric material having a k-value greater than that of silicon dioxide, or multiple layers thereof. The gate dielectric layer 136 may be formed by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. In some embodiments, the gate dielectric layer 136 may be a conformal layer. The term "conformal" may be used herein to describe layers having substantially the same thickness in different regions. The one or more work function layers may include titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, etc.

[0143] Gate spacer 122 is formed along the sidewalls of gate stack 140 (e.g., the sidewalls of gate dielectric layer 136). Gate spacer 122 may comprise silicon oxycarbide, silicon nitride, silicon oxynitride, etc., multilayers thereof, or combinations thereof, and may be deposited by chemical vapor deposition, atomic layer deposition, or other suitable deposition techniques. In some embodiments, fin sidewall spacers 123 may be disposed on opposite sides of each source / drain region 124, and fin sidewall spacers 123 may comprise the same material as gate spacer 122. Multiple portions of gate stack 140, gate spacer 122, and fin sidewall spacers 123 may be disposed on isolation region 114. Isolation region 114 is disposed on substrate 102. Isolation region 114 may comprise an insulating material, such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. In some embodiments, isolation region 114 is shallow trench isolation (STI). The insulating material can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. In one sample, the isolation region 114 comprises silicon oxide formed by a flowable chemical vapor deposition process.

[0144] A contact etch stop layer (CESL) 126 is formed on the source / drain region 124 and the isolation region 114, and an interlayer dielectric (ILD) layer 128 is formed on the CESL 126. The CESL 126 provides a mechanism to stop the etch process when an opening is formed in the interlayer dielectric layer 128. The CESL 126 may be conformally deposited on the surfaces of the source / drain region 124 and the isolation region 114. The CESL 126 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or combinations thereof, and may be deposited by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. The interlayer dielectric layer 128 may comprise an oxide and be formed of tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG), organosilicate glass (OSG), SiOC, and / or any suitable low dielectric constant dielectric material (e.g., a material with a dielectric constant lower than that of silicon dioxide), and may be deposited by spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, or any suitable deposition technique.

[0145] Source / drain contacts 142 may be disposed on the interlayer dielectric layer 128 and the source / drain region 124. The source / drain contacts 142 may be conductive and comprise one or more materials selected from Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN, and the conductive contacts may be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition. A silicide layer 144 may be disposed between the source / drain contacts 142 and the source / drain region 124. The silicide layer 144 may be made of a metal or metal alloy silicide, and the metal includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof.

[0146] In integrated circuits, interconnect structures are used to provide signal routing and power for semiconductor devices. Integrated circuit wafers typically include device layers fabricated in front-end-of-line (FEOL) and middle-end-of-line (MEOL) processes, as well as back-end-of-line (BEOL) layers. Device layers can be formed inside and / or on a substrate, and back-end-of-line layers are formed on the front and / or back sides of the device layers. Device layers can include various semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., and can be formed inside and / or on a substrate. In some embodiments, the device layer may also include middle-end structure structures, such as one or more dielectric layers having conductive characteristics connected to gate and source / drain characteristics in the device layer. Interconnect structures typically include conductive lines and vias formed in the device layers and back-end-of-line layers.

[0147] Figures 2 to 6 , Figures 9 to 12 and Figures 15 to 16 These are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 2In this embodiment, interconnect structure 250 includes metallic features, such as metal lines 204 and vias 206, disposed on device layer 200 and substrate 102. Interconnect structure 250 has multiple downstream metal layers, namely metal M1 layer 250-1, metal M2 layer 250-2, metal M3 layer 250-3, ..., metal Mtop layer 250-t. Metal M1 layer 250-1 may be a layer immediately above the interlayer dielectric layer 128, while metal Mtop layer 250-t may be a top-layer metal layer immediately below the first ultra-thick metal (UTM) structure 260 formed in subsequent steps. In most cases, the metallic features in the top-layer metal Mtop layer 250-t are thicker than the metallic features in the bottom layers, for example, thicker than the metallic features in metal M1 layer 250-1. In this disclosure, the term "metal layer" refers to a collection of metallic features in the same layer. Metal layers M1 250-1 to Mtop 250-t are formed within the inter-metal dielectric (IMD) layer 202. The IMD layer 202 can be formed from oxides, such as undoped silicate glass (USG), fluorinated silicate glass (FSG), or low-dielectric materials. The IMD layer 202 can be formed using chemical vapor deposition, flowable chemical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. The k-value of the low-dielectric-constant material may range from about 1 to about 4. The IMD layer 202 provides insulation for the various metal lines 204 and vias 206.

[0148] Although not shown, it can be imagined that the bottommost metal feature of the interconnect structure 250 (e.g., metal line 204) can be electrically connected to the source / drain region 124. Figure 1A and Figure 1B ) and gate electrode layer 138 ( Figure 1A and Figure 1B Conductive contacts on the device layer 200. For example, one or more metal wires 204 may be electrically connected to source / drain contacts 142 disposed in the interlayer dielectric layer 128 of the device layer 200. In some embodiments, a back-side interconnect structure (not shown), similar to interconnect structure 250, may be formed on the back side of the device layer 200 to provide power and / or additional signal connections to the device layer 200.

[0149] In some embodiments, the thickness of the metal M1 layer 250-1 can be approximately to approximately The thickness of metal M2 layer 250-2, metal M3 layer 250-3, ..., metal Mtop layer 250-t can be between [a certain range], while the thickness of [other layers] can be approximately [a certain range]. to approximately Between. However, the dimensions described in this disclosure are merely examples and may be changed in alternative implementations.

[0150] After the interconnect structure 250 is formed, a first etch stop layer 255 and a first dielectric layer 261 are sequentially formed on the top metal Mtop layer 250-t. The first etch stop layer 255 contacts the metal lines 204 in the metal Mtop layer 250-t. In some embodiments, the first etch stop layer 255 is disposed at the interface between the subsequently formed first ultra-thick metal structure 260 and the metal Mtop layer 250-t. The first etch stop layer 255 may include a different material from the first dielectric layer 261 to have different etch selectivity. In some embodiments, the first etch stop layer 255 is made of a dielectric material, such as oxides, nitrides, metal oxides, metal nitrides, or combinations thereof. Suitable materials for the first etch stop layer 255 may include, but are not limited to, silicon nitride, silicon carbide, oxygen-doped silicon carbide (ODC), silicon carbonitride, silicon oxynitride, nitrogen carbide, silicon oxide, silicon oxycarbonate, and aluminum oxide. The first etch stop layer 255 may be a single-layer or multi-layer structure. The first etch stop layer 255 can be formed by any suitable process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, plasma-assisted atomic layer deposition (PEALD), or plasma-enhanced chemical vapor deposition. The first etch stop layer 255 may include the same material as the inter-metal dielectric layer 202 and can be formed by the same process as the inter-metal dielectric layer 202. The thickness of the first etch stop layer 255 can be approximately... to approximately Between. The first dielectric layer 261 may comprise the same material as the inter-metal dielectric layer 202 and may be formed by the same process as the inter-metal dielectric layer 202. The first dielectric layer 261 may have approximately to approximately The thickness between, for example, approximately to approximately

[0151] After the first etch stop layer 255 and the first dielectric layer 261 are formed, openings 263a and 263b are formed within the first dielectric layer 261. Openings 263a and 263b collectively form ultra-thick-metal (UTM) trenches 263-1, 263-2, 263-3, and 263-4 (collectively referred to as ultra-thick-metal trench 263). In some embodiments, two or more ultra-thick-metal trenches may be part of a continuous trench. For example, ultra-thick-metal trenches 263-2 and 263-3 may be continuous trenches. In some embodiments, ultra-thick-metal trenches 263-2 and 263-3 are configured as continuous trenches surrounding ultra-thick-metal trench 263-1. Although four ultra-thick metal trenches 263-1, 263-2, 263-3, and 263-4 are shown in the figure, more or fewer ultra-thick metal trenches may be considered depending on the actual application. Ultra-thick metal trenches 263-1, 263-2, 263-3, and 263-4 are intended to be filled with conductive material to form ultra-thick metal features. Openings 263a and 263b can be formed by any suitable process, such as one or more etching processes. In some embodiments, openings 263a and 263b are formed using a dual-damascene process. Opening 263a may be a trench opening formed on the upper part of the first dielectric layer 261. Opening 263b may be a via opening formed through the first dielectric layer 261 and the first etch stop layer 255 to expose a portion of the corresponding metal line 204.

[0152] The formation of ultra-thick metal trenches 263-1, 263-2, 263-3, and 263-4 results in a distance D1 between ultra-thick metal trenches 263-1 and 263-2 and 263-3, respectively, and a distance D2 between ultra-thick metal trenches 263-3 and 263-4. In some embodiments, distances D1 and D2 are substantially the same. In some embodiments, distance D1 is greater than or less than distance D2. The widths of ultra-thick metal trenches 263-1, 263-2, 263-3, and 263-4 are from 0.1 μm to approximately 50 μm. The ultra-thick metal trench 263-1 may have a width W1, and the widths W2 of ultra-thick metal trenches 263-2, 263-3, and 263-4 may be smaller than the width W1. In some embodiments, the ratio of width W1 to width W2 (width W1:width W2) may be approximately 2:1 or greater, for example, approximately 3:1 to approximately 6:1, for example, approximately 4:1. In some embodiments, the width W2 may be in the range of approximately 0.2 μm to approximately 10 μm, and the distance D1 may be approximately 0.2 μm or greater. The larger width of the ultra-thick metal trench 263-1 allows the subsequently formed ultra-thick metal feature 266-1 to have larger dimensions therein. Therefore, the formed inductor can provide lower DC resistance.

[0153] exist Figure 3In this process, a barrier layer 262 is conformally formed on the exposed surface of the first dielectric layer 261. The barrier layer 262 may be formed on the top surface of the first dielectric layer 261 and the sidewall surfaces within openings 263a and 263b, including the exposed surface of the metal line 204 formed at the bottom of opening 263b. The barrier layer 262 serves as a diffusion barrier layer, preventing metal from diffusing into surrounding materials, such as the first dielectric layer 261, the first etch stop layer 255, and the metal line 204. The barrier layer 262 can be deposited using any suitable deposition technique, such as chemical vapor deposition, physical vapor deposition, ion metal plasma (IMP), or self-ionized plasma (SIP). The barrier layer 262 may include metal nitrides, metal oxides, two-dimensional (2D) materials, or combinations thereof. Suitable metals for the barrier layer 262 may include, but are not limited to, Ta, Ti, W, Mn, Zn, Cr, In, or Hf. In some embodiments, the barrier layer 262 is a metal nitride, such as TaN, TiN, WN, CrN, TaSiN, TiSiN, WSiN, or a metal oxide, such as HfOx. The term "2D material" as used in this disclosure refers to a monolayer material or an atomically thin, crystalline solid monolayer material having intralayer covalent bonds and interlayer Van der Waals forces. Examples of two-dimensional materials may include graphene, hexagonal boron nitride (h-BN), or transition metal dichalcogenides (MX2), where M is a transition metal element and X is a chalcogenide element. Some exemplary MX2 materials may include, but are not limited to, Hf, Te2, WS2, MoS2, WSe2, MoSe2, or combinations thereof. The thickness of the barrier layer 262 may range from approximately [missing information - likely a value]. to approximately

[0154] exist Figure 4 In this process, a seed layer 264 is formed on the barrier layer 262. The seed layer 264 assists in the formation of subsequent conductive material, allowing the conductive material to fill the openings 263a and 263b. The seed layer 264 can be a metal, such as Cu, Al, Ti, Au, Mn, Fe, alloys, or other suitable materials compatible with the electroplated layer. The seed layer 264 can be formed using atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition techniques. The thickness of the seed layer 264 can range from approximately [missing information - likely a value]. to approximately

[0155] exist Figure 5 In this process, an ultra-thick metal layer 266 is formed on seed layer 264. The ultra-thick metal layer 266 is deposited until ultra-thick metal trenches 263-1, 263-2, 263-3, and 263-4 are completely filled. The ultra-thick metal layer 266 may include a conductive material, such as Cu, Al, Ag, Fe, Mn, Co, Ru, Zn, Zr, W, Mo, Os, Ir, Ni, alloys thereof, or combinations thereof. In some embodiments, the ultra-thick metal layer 266 includes AlCu, CuAg, CuAl, CuMn, or CoRu. In one exemplary embodiment, the ultra-thick metal layer 266 is a copper-silver alloy, wherein silver has about 5 atomic percent or greater. The ultra-thick metal layer 266 fills the openings 263a and 263b and is deposited to a height above the top surface of the first dielectric layer 261. The ultrathick metal layer 266 in openings 263a and 263b is surrounded by a first dielectric layer 261. The ultrathick metal layer 266 can be deposited using physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition processes or combinations thereof. In some embodiments, the ultrathick metal layer 266 formed in ultrathick metal trench 263-1 comprises a first conductive material, while the ultrathick metal layers 266 formed in ultrathick metal trenches 263-2, 263-3, and 263-4 comprise a second conductive material different from the first conductive material.

[0156] exist Figure 6In this process, a planarization process, such as chemical mechanical polishing (CMP), is performed on the semiconductor device structure 100 to remove excess ultrathick metal layer 266 on the top surface of the first dielectric layer 261. After the planarization process, the top surfaces of the first dielectric layer 261, the barrier layer 262, the seed layer 264, and the ultrathick metal layer 266 are substantially coplanar. The ultrathick metal layer 266 in ultrathick metal trenches 263-1, 263-2, 263-3, and 263-4 form ultrathick metal features 266-1, 266-2, 266-3, and 266-4, which are separated from each other by the first dielectric layer 261. Ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 (and other ultra-thick metal features not shown) form a first ultra-thick metal structure 260 in the first dielectric layer 261. The first ultra-thick metal structure 260 may have a first thickness, and the conductive features (e.g., metal lines 204) in the metal M1 layer 250-1 of the interconnect structure 250 may have a second thickness significantly smaller than the first thickness. The term "ultra-thick metal layer" as used in this disclosure may refer to the collection of all ultra-thick metal features in the first dielectric layer 261. In various embodiments, ultra-thick metal features 266-2, 266-3, and 266-4 are configured in a planar coil-like pattern to help enhance the magnetic field strength of the inductor.

[0157] Ultra-thick metal features 266-1, 266-2, 266-3, and 266-4, or the first ultra-thick metal structure 260, can form part of an inductor when the semiconductor device structure 100 includes or serves as a radio frequency device. Ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 can be considered discrete inductors because they are separated from the device layer 200 and interconnect structure 250 by a barrier layer 262, a first dielectric layer 261, and a first etch stop layer 255. In some embodiments, ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 form part of a capacitor. In some embodiments, ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 form part of a power line. Ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 are electrically connected to various conductive features (e.g., metal wire 204) in interconnect structure 250. In some embodiments, ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 are electrically connected to various devices in device layer 200 via external routing (not shown), for example, via wire bonding.

[0158] Figure 7A This is a top view of a portion of a semiconductor device structure 100, showing the path along certain embodiments. Figure 6The first ultra-thick metal structure 260 is cut from the cross-section AA. It can be seen that ultra-thick metal features 266-2, 266-3, and 266-4 are separated metal lines arranged in a planar coil-like pattern. In some embodiments, ultra-thick metal features 266-2 and 266-3 are arranged as continuous metal lines surrounding ultra-thick metal feature 266-1, while ultra-thick metal feature 266-4 is arranged as continuous metal lines surrounding ultra-thick metal features 266-2 and 266-3. Ultra-thick metal features 266-2, 266-3, and 266-4 may have the same width. The extra-thick metal features 266-2, 266-3, and 266-4 can be arranged asymmetrically, such that the number of metal lines on the first side of extra-thick metal feature 266-1 differs from the number of metal lines on the second side of extra-thick metal feature 266-1 opposite to the first side. The distance between extra-thick metal feature 266-1 and extra-thick metal feature 266-2 or extra-thick metal feature 266-3 is distance D1, and the distance between extra-thick metal feature 266-2 or extra-thick metal feature 266-3 and extra-thick metal feature 266-4 is distance D2. Depending on the application, distance D1 may be less than, equal to, or greater than distance D2. In some embodiments, extra-thick metal feature 266-1 can be a columnar structure. Although illustrated as a square column, when viewed from above, extra-thick metal feature 266-1 can be other shapes, such as circular, rectangular, or elliptical columns. Although not illustrated, in some embodiments, the extra-thick metal feature 266-4 may have a first end electrically connected to a conductive feature (e.g., metal wire 204) and a first end connected to a conductive terminal (e.g., Figure 15 The second end of the conductive structure 290 shown is electrically connected. Alternatively, the second end may be electrically connected to an ultra-thick metal feature (e.g., ultra-thick metal feature 276-4) of the second ultra-thick metal structure 270, such as... Figure 12 As shown.

[0159] Figure 7B This is a top view of a portion of a semiconductor device structure 100, illustrating a first ultra-thick metal structure 260-A, for example, along... Figure 6 Some alternative embodiments of the first ultra-thick metal structure 260 cut from the cross section AA. In this embodiment, ultra-thick metal features 266-2, 266-3, and 266-4 are arranged symmetrically such that the number of metal lines on the first side of ultra-thick metal feature 266-1 is the same as the number of metal lines on the second side of ultra-thick metal feature 266-1 opposite to the first side. Figure 7B Further illustration shows that one of the outermost ultra-thick metal features (e.g., ultra-thick metal feature 266-4) has a conductive terminal (e.g.) Figure 15 The conductive structure 290 shown is electrically connected to terminal 222. Alternatively, terminal 222 may be electrically connected to an ultra-thick metal feature (e.g., ultra-thick metal feature 276-4) of the second ultra-thick metal structure 270, such as... Figure 12 As shown. In addition, one of the outermost ultra-thick metal features (e.g., ultra-thick metal feature 266-5) may have a terminal 224 that is electrically connected to an external voltage source.

[0160] Back Figure 7A The ultra-thick metal feature 266-1 may have a first width W1a, and ultra-thick metal features 266-2, 266-3, and 266-4 may have a second width W1b smaller than the first width W1a. In some embodiments, the first width W1a is at least twice as large as the second width W1b. In some embodiments, the first width W1a and the second width W1b may have a ratio of about 3:1 to about 6:1 (first width W1a: second width W1b). In some embodiments, there is a line spacing P1 of about 1 μm to about 30 μm between ultra-thick metal features 266-2 or 266-3 and ultra-thick metal features 266-4, for example, about 2.7 μm to about 5 μm. The line spacing P1 is a critical dimension (CD), which is determined by, for example... Figure 7A The diagram illustrates the minimum line spacing dimension that can be present in the coil-like pattern. Although not illustrated, it is conceivable that the first ultra-thick metal structure 260 may include multiple sets of different line spacings, with the minimum line spacing being the critical dimension for line spacing. In some embodiments, ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 occupy surface area A2, while the total surface area of ​​the substrate 102 has surface area A1. It should be noted that the total surface area of ​​the substrate 102 may be the total surface area of ​​a single grain containing the first ultra-thick metal structure 260 disclosed herein. The area ratio (surface area A2 / surface area A1) may be referred to as the area density of the ultra-thick metal structure. The area density of the ultra-thick metal is the total surface area of ​​the ultra-thick metal divided by the total surface area of ​​the substrate 102, particularly the area density of the ultra-thick metal at the first ultra-thick metal structure 260. In some embodiments, surface area A2 is approximately 50% or less of surface area A1.

[0161] In some implementations, the ultra-thick metal feature 266-1 is not a columnar structure. Instead, the ultra-thick metal feature 266-1 is part of a continuous metal line. Figure 8 This is a top view of a portion of a semiconductor device structure 100, illustrating the arrangement along a path according to another embodiment. Figure 6The first ultra-thick metal structure 260 is cut from the cross-section BB. In this embodiment, ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 are configured as a single continuous metal line and arranged in a planar coil-like pattern. In some embodiments, ultra-thick metal feature 266-1 may have a first width, while the second width of ultra-thick metal features 266-2, 266-3, and 266-4 may be smaller than the first width.

[0162] exist Figure 9 In the first ultra-thick metal structure 260, a second etch stop layer 275 and a second dielectric layer 271 are sequentially formed on the second etch stop layer 261. The second etch stop layer 275 may comprise the same material as the first etch stop layer 255, and the second dielectric layer 271 may comprise the same material as the first dielectric layer 261. The thickness of the second dielectric layer 271 can be approximately... to approximately Between, for example, about To date In some embodiments, the first dielectric layer 261 and the second dielectric layer 271 have the same thickness. In other embodiments, the first dielectric layer 261 and the second dielectric layer 271 have different thicknesses. The first dielectric layer 261 may have a first thickness, and the second dielectric layer 271 may have a second thickness that is less than or greater than the first thickness, depending on the surface areas of the first dielectric layer 261 and the second dielectric layer 271. For example, when the surface area of ​​the first dielectric layer 261 is greater than the surface area of ​​the second dielectric layer 271, the first thickness of the first dielectric layer 261 may be less than the second thickness of the second dielectric layer 271. When the surface area of ​​the first dielectric layer 261 is less than the surface area of ​​the second dielectric layer 271, the first thickness of the first dielectric layer 261 may be greater than the second thickness of the second dielectric layer 271.

[0163] The second dielectric layer 271 and the second etch stop layer 275 are patterned and etched to form openings 273a and 273b. In some embodiments, openings 273a and 273b are formed to align with the positions of ultra-thick metal features 266-1, 266-2, 266-3, and 266-4. Openings 273a and 273b together form ultra-thick metal trenches 273-1, 273-2, 273-3, and 273-4 (collectively referred to as ultra-thick metal trench 273). In some embodiments, two or more ultra-thick metal trenches may be part of a continuous trench. Similarly, ultra-thick metal trenches 273-2 and 273-3 may be continuous trenches in some embodiments. In some embodiments, ultra-thick metal trenches 273-2 and 273-3 are continuous trenches and configured to surround ultra-thick metal trench 273-1. Although four ultra-thick metal trenches 273-1, 273-2, 273-3, and 273-4 are illustrated, more or fewer ultra-thick metal trenches may be considered depending on the application. Ultra-thick metal trenches 273-1, 273-2, 273-3, and 273-4 are used to fill conductive material to form ultra-thick metal features therein. Openings 273a and 273b can be formed by any suitable process, such as one or more etching processes. In some embodiments, openings 273a and 273b are formed by a dual damascene process. Opening 273a may be a trench opening formed on the upper part of the second dielectric layer 271. The opening 273b can be a via opening formed through the second dielectric layer 271 and the second etch stop layer 275 to expose a portion of the corresponding ultra-thick metal feature. For example, the opening 273b of the ultra-thick metal trench 273-1 is formed to expose the top surface of the ultra-thick metal feature 266-1, the opening 273b of the ultra-thick metal trench 273-2 is formed to expose the top surface of the ultra-thick metal feature 266-2, the opening 273b of the ultra-thick metal trench 273-3 is formed to expose the top surface of the ultra-thick metal feature 266-3, and the opening 273b of the ultra-thick metal trench 273-4 is formed to expose the top surface of the ultra-thick metal feature 266-4.

[0164] Similarly, the formation of ultra-thick metal trenches 273-1, 273-2, 273-3, and 273-4 results in ultra-thick metal trench 273-1 being separated from ultra-thick metal trenches 273-2 and 273-3 by a distance D3, and ultra-thick metal trenches 273-3 and 273-4 being separated by a distance D4. In some embodiments, distances D3 and D4 are substantially the same. In some embodiments, distance D3 is greater than or less than distance D4. The widths of ultra-thick metal trenches 273-1, 273-2, 273-3, and 273-4 are from 0.1 μm to approximately 10 μm. The width of the ultra-thick metal trench 273-1 may be W3, while the widths W4 of the ultra-thick metal trenches 273-2, 273-3, and 273-4 may be smaller than W3. In some embodiments, the ratio of width W3 to width W4 (width W3:width W4) may be approximately 2:1 or greater, for example, approximately 3:1 to approximately 6:1, for example, approximately 4:1. In some embodiments, the width W3 may be in the range of approximately 0.1 μm to approximately 10 μm, and the distance D3 may be greater than approximately 0.2 μm, for example, approximately 1.8 μm or greater.

[0165] exist Figure 10 In this process, barrier layer 272 and seed layer 274 are sequentially formed on the exposed surface of the second dielectric layer 271. Barrier layer 272 and seed layer 274 may each comprise the same material as barrier layer 262 and seed layer 264, and may be deposited in the same manner as barrier layer 262 and seed layer 264.

[0166] exist Figure 11 In this process, an ultra-thick metal layer 276 is formed on seed layer 274. Similarly, the ultra-thick metal layer 276 is deposited until ultra-thick metal trenches 273-1, 273-2, 273-3, and 273-4 are completely filled. The ultra-thick metal layer 276 may include the same material as ultra-thick metal layer 266 and may be deposited using the same method as ultra-thick metal layer 266. In some embodiments, the ultra-thick metal layer 276 formed in ultra-thick metal trench 273-1 includes a first conductive material, while the ultra-thick metal layers 276 formed in ultra-thick metal trenches 273-2, 273-3, and 273-4 include a second conductive material different from the first conductive material.

[0167] In some embodiments, the ultra-thick metal layer 276 formed in ultra-thick metal trenches 273-1, 273-2, 273-3, and 273-4 includes a first conductive material, while the ultra-thick metal layer 266 formed in ultra-thick metal trenches 263-1, 263-2, 263-3, and 263-4 includes a second conductive material different from the first conductive material.

[0168] In some embodiments, the ultra-thick metal layer 276 formed in the ultra-thick metal trench 273-1 includes a first conductive material, and the ultra-thick metal layer 276 formed in the ultra-thick metal trenches 273-2, 273-3, and 273-4, and the ultra-thick metal layer 266 formed in the ultra-thick metal trenches 263-1, 263-2, 263-3, and 263-4 (i.e., ultra-thick metal features 266-1, 266-2, 266-3, and 266-4) include a second conductive material different from the first conductive material. Alternatively, the ultra-thick metal layer 266 (i.e., ultra-thick metal feature 266-1) formed in the ultra-thick metal trench 263-1 includes a first conductive material, and the ultra-thick metal layer 276 formed in the ultra-thick metal trenches 273-1, 273-2, 273-3, and 273-4, and the ultra-thick metal layer 266 (i.e., ultra-thick metal feature 266-2, 266-3, and 266-4) formed in the ultra-thick metal trenches 263-2, 263-3, and 263-4 include a second conductive material different from the first conductive material.

[0169] exist Figure 12In this process, a planarization process, such as a chemical mechanical polishing process, is performed on the semiconductor device structure 100 until the top surfaces of the second dielectric layer 271, the barrier layer 272, the seed layer 274, and the ultrathick metal layer 276 are substantially coplanar. The ultrathick metal layers 276 in ultrathick metal trenches 273-1, 273-2, 273-3, and 273-4 form ultrathick metal features 276-1, 276-2, 276-3, and 276-4, which are separated from each other by the second dielectric layer 271. Ultra-thick metal features 276-1, 276-2, 276-3, and 276-4 (and other ultra-thick metal features not shown) form a second ultra-thick metal structure 270 in the second dielectric layer 271. The second ultra-thick metal structure 270 may have a first thickness, and the conductive features (e.g., metal lines 204) in the metal M1 layer 250-1 of the interconnect structure 250 may have a second thickness significantly smaller than the first thickness. In some embodiments, the first thickness may be at least 10 times greater than the second thickness. In various embodiments, ultra-thick metal features 276-2, 276-3, and 276-4 are arranged in a planar coil-like pattern. Similarly, ultra-thick metal features 276-1, 276-2, 276-3, and 276-4 may constitute part of an inductor. Ultra-thick metal features 276-1, 276-2, 276-3, and 276-4 are electrically connected to ultra-thick metal features 266-1, 266-2, 266-3, and 266-4. Stacking the first ultra-thick metal structure 260 and the second ultra-thick metal structure 270 together reduces the area ratio and achieves a higher Q-value inductance. Therefore, the performance of the RF circuit is enhanced.

[0170] Figure 13A This is a top view of a portion of a semiconductor device structure 100, illustrating the path along certain embodiments. Figure 12The second ultra-thick metal structure 270 is cut from the cross-section CC. It can be seen that ultra-thick metal features 276-2, 276-3, and 276-4 are arranged as separate metal lines in a planar coil-like pattern. In some embodiments, ultra-thick metal features 276-2 and 276-3 are configured as continuous metal lines surrounding ultra-thick metal feature 276-1, while ultra-thick metal feature 276-4 is configured as continuous metal lines surrounding ultra-thick metal features 276-2 and 276-3. Ultra-thick metal features 276-2, 276-3, and 276-4 may have the same width. Ultra-thick metal features 276-2, 276-3, and 276-4 may be arranged asymmetrically, such that the number of metal lines on the first side of ultra-thick metal feature 276-1 differs from the number of metal lines on the second side of ultra-thick metal feature 276-1 opposite to the first side. The distance between ultra-thick metal feature 276-1 and ultra-thick metal feature 276-2 or ultra-thick metal feature 276-3 is distance D3, and the distance between ultra-thick metal feature 276-2 or ultra-thick metal feature 276-3 and ultra-thick metal feature 276-4 is distance D4. Depending on the application, distance D3 may be less than, equal to, or greater than distance D4. In some embodiments, ultra-thick metal feature 276-1 can be a columnar structure of any shape, such as a square, circular, rectangular, or elliptical column when viewed from above. In some embodiments, ultra-thick metal feature 276-1 can have a first shape, while ultra-thick metal feature 266-1 can have a second shape that is the same as or different from the first shape. For example, ultra-thick metal feature 276-1 can be a square column, while ultra-thick metal feature 266-1 can be a rectangular column.

[0171] Although not illustrated, the ultra-thick metal feature 276-4 may have a first end and a conductive terminal (e.g. Figure 15 The conductive structure 290 shown is electrically connected, and the second terminal is electrically connected to an external voltage source.

[0172] Figure 13B This is a top view of a portion of a semiconductor device structure 100, illustrating the first ultra-thick metal structure 270-A, for example along... Figure 12 Some alternative embodiments of the second ultra-thick metal structure 270 cut from the cross-section CC. In this embodiment, ultra-thick metal features 276-2, 276-3, and 276-4 are arranged symmetrically such that the number of metal lines on the first side of ultra-thick metal feature 276-1 is the same as the number of metal lines on the second side of ultra-thick metal feature 276-1 opposite to the first side. Figure 13BFurther illustration shows that one of the outermost ultra-thick metal features (e.g., ultra-thick metal feature 276-4) has a conductive terminal (e.g.) Figure 15 The conductive structure 290 shown has an electrically connected terminal 232, and one of the outermost ultra-thick metal features (e.g., ultra-thick metal feature 276-5) has a terminal 234 electrically connected to an external voltage source.

[0173] Back Figure 13A The ultra-thick metal feature 276-1 may have a first width W2a, and ultra-thick metal features 276-2, 276-3, and 276-4 may have a second width W2b smaller than the first width W2a. In some embodiments, the first width W2a is at least twice as large as the second width W2b. In some embodiments, the first width W2a and the second width W2b may have a ratio of about 3:1 to about 6:1 (first width W2a: second width W2b). In some embodiments, ultra-thick metal feature 276-2 or ultra-thick metal feature 276-3 and ultra-thick metal feature 276-4 have a line spacing P2 of about 1 μm to about 30 μm, for example, about 2.7 μm to about 5 μm. Although not illustrated, it is conceivable that the second ultra-thick metal structure 270 may include multiple sets of different line spacings. In some embodiments, ultrathick metal features 276-1, 276-2, 276-3, and 276-4 occupy surface area A3, while the total surface area of ​​substrate 102 has surface area A1. As described above, the total surface area of ​​substrate 102 can be the total surface area of ​​a single grain containing the second ultrathick metal structure 270 disclosed herein. The layout area ratio (surface area A3 / surface area A1) can be referred to as the area density of the ultrathick metal structure. The area density of the ultrathick metal is the total ultrathick metal surface area divided by the total surface area of ​​substrate 102, particularly the area density of the ultrathick metal at the second ultrathick metal structure 270. In some embodiments, surface area A3 is approximately 50% or less of surface area A1.

[0174] In some implementations, the ultra-thick metal feature 276-1 is not a columnar structure. Instead, the ultra-thick metal feature 276-1 is part of a continuous metal line. Figure 14 This is a top view of a portion of a semiconductor device structure 100, illustrating the arrangement along a path according to another embodiment. Figure 12The second ultra-thick metal structure 270 is cut from the cross-section DD. In this embodiment, ultra-thick metal features 276-1, 276-2, 276-3, and 276-4 are configured as a single continuous metal line and arranged in a planar coil pattern. In some embodiments, ultra-thick metal feature 276-1 may have a first width, while ultra-thick metal features 276-2, 276-3, and 276-4 may have a second width smaller than the first width.

[0175] In some embodiments, the ultra-thick metal feature 276-1 is a columnar structure in the second ultra-thick metal structure 270, while the ultra-thick metal feature 266-1 is a non-columnar structure in the first ultra-thick metal structure 260. Alternatively, the ultra-thick metal feature 276-1 is a non-columnar structure in the second ultra-thick metal structure 270, while the ultra-thick metal feature 266-1 is a columnar structure in the first ultra-thick metal structure 260.

[0176] exist Figure 15 In this process, dielectric layer 282 is then formed on the second ultrathick metal structure 270. Dielectric layer 282 may include the same material as the first dielectric layer 261. A portion of dielectric layer 282 may contact ultrathick metal features 276-1, 276-2, 276-3, and 276-4 of the second ultrathick metal structure 270. After the dielectric layer 282 is formed, an etching process, such as dry etching, wet etching, or a combination thereof, is performed to form openings in the dielectric layer 282. The configuration of the openings allows the various ultrathick metal features in the second ultrathick metal structure 270 to be electrically connected to subsequent conductive terminals (e.g., conductive structure 290). For example, one end of an ultrathick metal feature, such as ultrathick metal feature 276-2, may be connected to a conductive pad (not shown) connecting to conductive structure 290. Additionally or optionally, a portion of an ultrathick metal feature, such as ultrathick metal feature 276-4, may be connected to conductive structure 290. Optionally, a passivation layer (not shown) may be formed between the conductive structure 290 and the dielectric layer 282. The passivation layer may be made of an organic material, such as silicon oxide, undoped silicate glass, silicon oxynitride, solder resist (SR), silicon nitride, hexamethyldisilazane (HMDS), etc. In some embodiments, the passivation layer is made of a polymeric material, such as polyimide (PI), epoxy resin, or a fluoropolymer. After the passivation layer is formed, a patterning process is performed to form openings, thereby exposing portions of the ultra-thick metal feature.

[0177] In any case, a conductive material, such as Cu, Au, Ag, Sn, their alloys, or other suitable materials, is formed in an opening (in the dielectric layer 282 and / or passivation layer) to form a conductive structure 290. The conductive structure 290 may be a spherical protrusion or a columnar shape. In some cases, the conductive structure 290 is electrically connected to various ultrathick metal features in the second ultrathick metal structure 270. In some cases, the conductive structure 290 is electrically connected to various ultrathick metal features in the first ultrathick metal structure 260 via redistribution pads (not shown) and vias (not shown). The conductive structure 290 is electrically connected to a voltage source (not shown). In some embodiments, the first ultra-thick metal structure 260 or the second ultra-thick metal structure 270 is a discrete inductor that is not connected to conductive features in the various devices and / or interconnect structures 250 in the device layer 200 via ultra-thick metal features (e.g., ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 or ultra-thick metal features 276-1, 276-2, 276-3, and 276-4), but rather via an external connection. The external connection may be in the form of a wire connection, connecting one end of the discrete inductor to a voltage source and the other end to conductive features in the various devices and / or interconnect structures 250 in the device layer 200.

[0178] Figure 16 It shows that according to Figure 15 The illustration shows a perspective view of a portion of the first ultra-thick metal structure 260 and a portion of the second ultra-thick metal structure 270. It can be seen that ultra-thick metal features 266-2, 266-3, and 266-4 are arranged in a planar coil pattern and configured to surround ultra-thick metal feature 266-1, and ultra-thick metal features 266-2, 266-3, and 266-4 are configured to have a first number of turns. Ultra-thick metal features 276-2, 276-3, and 276-4 are arranged in a coil pattern and configured to surround ultra-thick metal feature 276-1, and ultra-thick metal features 276-2, 276-3, and 276-4 are configured to have a second number of turns. In some embodiments, the ultra-thick metal feature 266-1 and the ultra-thick metal feature 276-1 have substantially the same surface area, and the first number of turns is substantially the same as the second number of turns.

[0179] In some embodiments, the arrangement of ultra-thick metal features 266-2, 266-3, 266-4, 276-2, 276-3, and 276-4 is such that the first number of turns is different from the second number of turns, and ultra-thick metal features 266-1 and 276-1 have substantially the same surface area. Figure 17 An exemplary configuration of an ultra-thick metal structure is shown, wherein a first ultra-thick metal structure 260', such as a first ultra-thick metal structure 260, is disposed below a second ultra-thick metal structure 270 and has a first number of turns greater than the second number of turns of the second ultra-thick metal structure 270. That is, the surface area occupied by ultra-thick metal features 266'-1, 266'-2, 3, and 4 is greater than the surface area of ​​ultra-thick metal features 276-1, 276-2, 3, and 4 of the second ultra-thick metal structure 270. In some embodiments, the first number of turns is 4 or greater, and the second number of turns is 3 or greater. Figure 17 The configuration shown allows for easy routing of the second ultra-thick metal structure 270 because the first ultra-thick metal structure 260' has a larger surface area than the second ultra-thick metal structure 270.

[0180] In some implementations, the ultra-thick metal feature 266'-1 may have a first surface area, while the ultra-thick metal feature 276-1 may have a second surface area smaller than the first surface area. Alternatively, the ultra-thick metal feature 266'-1 may have a first surface area, while the ultra-thick metal feature 276-1 may have a second surface area larger than the first surface area. A larger size of the ultra-thick metal feature 266'-1 will help reduce the overall DC resistance of the inductor.

[0181] In some embodiments, the arrangement of ultra-thick metal features 266-2, 266-3, 266-4, 276-2, 276-3, and 276-4 is such that the first number of turns is less than the second number of turns, and ultra-thick metal features 266-1 and 276-1 have substantially the same surface area. Figure 18An exemplary configuration of an ultra-thick metal structure is shown, wherein a second ultra-thick metal structure 270', such as a second ultra-thick metal structure 270, is disposed on a first ultra-thick metal structure 260 and has a second number of turns greater than the first number of turns of the first ultra-thick metal structure 260. That is, the surface area occupied by ultra-thick metal features 266-1, 266-2, 266-3, and 266-4 is smaller than the surface area of ​​ultra-thick metal features 276'-1, 276'-2, 276'-3, and 276'-4. In some embodiments, the first number of turns is 3 or greater, and the second number of turns is 4 or greater. Figure 18 The configuration shown helps to minimize parasitic inductance on device layer 200 because the larger second ultra-thick metal structure 270' is located further away from device layer 200. Therefore, the parasitic capacitance between the second ultra-thick metal structure 270' and the various circuit devices in device layer 200 is lower.

[0182] In some implementations, the ultra-thick metal feature 276'-1 may have a first surface area, while the ultra-thick metal feature 266-1 may have a second surface area smaller than the first surface area. A larger ultra-thick metal feature 276'-1 helps reduce the overall DC resistance of the inductor. Alternatively, the ultra-thick metal feature 276'-1 may have a first surface area, while the ultra-thick metal feature 266-1 may have a second surface area larger than the first surface area.

[0183] Figure 19 An exemplary configuration of a top view of an ultra-thick metal structure 2002 according to some embodiments is shown. The configuration of the ultra-thick metal structure 2002 can be applied to a first ultra-thick metal structure 260 and / or a second ultra-thick metal structure 270. The ultra-thick metal structure 2002 and... Figure 7AThe first ultra-thick metal structure 260 is substantially the same as the first ultra-thick metal structure 266-1, except that the ultra-thick metal feature 266-1 is divided into two columnar structures, namely a first columnar structure 2066a and a second columnar structure 2066b. The first columnar structure 2066a and the second columnar structure 2066b may each have a rectangular shape extending along the Y-axis. In some embodiments, the first columnar structure 2066a and the second columnar structure 2066b may each have a rectangular shape extending along the X-axis (the X, Y, and Z axes are perpendicular to each other). In some embodiments, the first columnar structure 2066a may be a rectangular shape extending in a first direction, while the second columnar structure 2066b may be a rectangular shape extending in a second direction different from the first direction. In some embodiments, the first columnar structure 2066a may have a first shape (e.g., rectangular), and the second columnar structure 2066b may have a second shape different from the first shape (e.g., square). Various configuration combinations of the first columnar structure 2066a and the second columnar structure 2066b can increase the permeability of the inductor.

[0184] Figure 20 An exemplary configuration of a top view of an ultra-thick metal structure 2004 according to some embodiments is shown. The configuration of the ultra-thick metal structure 2004 can be applied to a first ultra-thick metal structure 260 and / or a second ultra-thick metal structure 270. The ultra-thick metal structure 2004 and... Figure 7A The first ultra-thick metal structure 260 is essentially the same, except that the ultra-thick metal feature 266-1 is divided into four columnar structures: the first columnar structure 2056a, the second columnar structure 2056b, the third columnar structure 2056c, and the fourth columnar structure 2056d. Each columnar structure is separated from the innermost ring of the metal wire (e.g., ultra-thick metal features 266-2 and 266-3) by a distance D5, which may be greater than or less than a distance D4. Figure 7A Various configurations and combinations of the first columnar structure 2056a, the second columnar structure 2056b, the third columnar structure 2056c, and the fourth columnar structure 2056d can increase the permeability of the inductor.

[0185] The various ultra-thick metal structures discussed in this paper can be combined in different ways to improve the permeability of inductors. Figure 21 A schematic diagram of an ultra-thick metal structure 2200 according to some alternative embodiments is shown. In this embodiment, such as Figure 13A The second ultra-thick metal structure 270 and the first ultra-thick metal structure 2202 are set as follows: Figure 20 On the second ultra-thick metal structure 2204 of the ultra-thick metal structure 2004. Figure 22 A schematic diagram of an ultra-thick metal structure 2300 according to some alternative embodiments is shown. In this embodiment, such as Figure 19The first ultra-thick metal structure 2302 of the ultra-thick metal structure 2002 is set as follows: Figure 20 On the second ultra-thick metal structure 2304 of the ultra-thick metal structure 2004. Figure 23 A schematic diagram of an ultra-thick metal structure 2400 according to some alternative embodiments is shown. In this embodiment, such as Figure 19 The first ultra-thick metal structure 2402 of the ultra-thick metal structure 2002 is set as follows: Figure 13A On the second ultra-thick metal structure 2404 of the second ultra-thick metal structure 270. Although not shown, it can be foreseen that... Figures 21 to 23 The dimensions of the upper and lower ultra-thick metal structures can differ from each other. Furthermore, although two ultra-thick metal structures are illustrated in various embodiments of this disclosure, three or more ultra-thick metal structures with similar designs are contemplated.

[0186] Embodiments of this disclosure provide an improved semiconductor device structure (e.g., a radio frequency device) having an inductor constructed from two ultra-thick-metal (UTM) structures stacked vertically. Each UTM structure has multiple UTM features configured in a coil-like pattern around a columnar UTM feature, which helps to reduce the layout area ratio at a lower cost due to increased routing flexibility. The columnar UTM feature has a larger surface area, which increases the inductor's permeability and magnetic field strength. Therefore, a higher Q-value inductor can be obtained, and the performance of the radio frequency circuit can be enhanced.

[0187] One embodiment relates to a semiconductor device structure. The semiconductor device structure includes a device layer, an interconnect structure, and an ultra-thick metal structure. The interconnect structure includes multiple metal layers disposed on the device layer. The ultra-thick metal structure is disposed on the interconnect structure and includes a first ultra-thick metal feature and a second ultra-thick metal feature. The first ultra-thick metal feature has a first width. The second ultra-thick metal feature is disposed around the first ultra-thick metal feature, wherein the second ultra-thick metal feature has a second width smaller than the first width, and the second ultra-thick metal feature is separated from the first ultra-thick metal feature by a dielectric layer. In some embodiments, the first ultra-thick metal feature is a columnar structure. In some embodiments, the first ultra-thick metal feature includes two or more columnar structures. In some embodiments, the second ultra-thick metal feature includes multiple separated metal lines. In some embodiments, the second ultra-thick metal feature is arranged in a coil-like pattern. In some embodiments, the metal lines have the same width. In some embodiments, the number of metal lines of the second ultra-thick metal feature on a first side of the first ultra-thick metal feature is different from the number of metal lines of the second ultra-thick metal feature on a second side of the first ultra-thick metal feature. In some embodiments, one of the metal layers disposed immediately above the device layer has a first thickness, and the ultra-thick metal structure has a second thickness greater than the first thickness. In some embodiments, the first ultra-thick metal feature is formed of a first conductive material, and the second ultra-thick metal feature is formed of a second conductive material that is chemically different from the first conductive material.

[0188] Another embodiment relates to a semiconductor device structure. The semiconductor device structure includes an interconnect structure, a first ultra-thick metal structure, and a second ultra-thick metal structure. The interconnect structure includes multiple metal layers disposed on a device layer. The first ultra-thick metal structure is disposed on the interconnect structure and includes a first ultra-thick metal feature and a second ultra-thick metal feature. The second ultra-thick metal feature is disposed around the first ultra-thick metal feature, wherein the second ultra-thick metal feature is separated from the first ultra-thick metal feature by a first dielectric layer. The second ultra-thick metal structure is disposed on the first ultra-thick metal structure and includes a third ultra-thick metal feature and a fourth ultra-thick metal feature. The fourth ultra-thick metal feature is disposed around the third ultra-thick metal feature, wherein the fourth ultra-thick metal feature is separated from the third ultra-thick metal feature by a second dielectric layer. In some embodiments, the bottommost metal layer of the interconnect structure has a first thickness, and the first and second ultra-thick metal structures have a second thickness greater than the first thickness. In some embodiments, the first and third ultra-thick metal features are aligned. In some embodiments, the first and third ultra-thick metal features are columnar structures. In some embodiments, the first ultra-thick metal feature has a first number of columnar structures, and the third ultra-thick metal feature has a second number of columnar structures different from the first number. In some embodiments, each of the second and fourth ultra-thick metal features includes a plurality of separate metal wires. In some embodiments, the second ultra-thick metal feature is configured in a coil-like pattern, and the fourth ultra-thick metal feature is configured in a coil-like pattern. In some embodiments, the second ultra-thick metal feature is configured to have a first number of turns, and the fourth ultra-thick metal feature is configured to have a second number of turns different from the first number of turns.

[0189] Another embodiment relates to a method of forming a semiconductor device structure. The method includes the following operations: forming an interconnect structure on a device layer; forming a first ultra-thick metal structure on the interconnect structure, wherein the first ultra-thick metal structure includes a first ultra-thick metal feature, a second ultra-thick metal feature disposed around the first ultra-thick metal feature, and a first dielectric layer separating the first ultra-thick metal feature and the second ultra-thick metal feature; forming a second ultra-thick metal structure on the first ultra-thick metal structure, wherein the second ultra-thick metal structure includes a third ultra-thick metal feature, a fourth ultra-thick metal feature disposed around the third ultra-thick metal feature, and a second dielectric layer separating the third ultra-thick metal feature and the fourth ultra-thick metal feature. In some embodiments, the first ultra-thick metal feature and the third ultra-thick metal feature have a first width, and the second ultra-thick metal feature and the fourth ultra-thick metal feature have a second width less than the first width. In some embodiments, the second ultra-thick metal feature is configured in a coil-like pattern having a first number of turns, the fourth ultra-thick metal feature is configured in a coil-like pattern having a second number of turns, and the first number of turns is different from the second number of turns.

[0190] This disclosure also provides a semiconductor device structure. The semiconductor device structure includes an interconnect structure, a first ultra-thick metal structure, and a second ultra-thick metal structure. The interconnect structure includes multiple metal layers disposed on a device layer. The first ultra-thick metal structure is disposed on the interconnect structure and includes a first ultra-thick metal feature and a second ultra-thick metal feature. The second ultra-thick metal feature is adjacent to the first ultra-thick metal feature, wherein a first dielectric layer is between the first ultra-thick metal feature and the second ultra-thick metal feature, and the second ultra-thick metal feature has a second width smaller than a first width of the first ultra-thick metal feature. The second ultra-thick metal structure is disposed on the first ultra-thick metal structure and includes a third ultra-thick metal feature and a fourth ultra-thick metal feature. The fourth ultra-thick metal feature is disposed around the third ultra-thick metal feature, wherein the fourth ultra-thick metal feature is separated from the third ultra-thick metal feature by a second dielectric layer. In some embodiments, the first ultra-thick metal feature is a columnar structure, and the third ultra-thick metal feature is a columnar structure. In some embodiments, the first ultra-thick metal feature has a first number of columnar structures, and the third ultra-thick metal feature has a second number of columnar structures different from the first number. In some embodiments, the second ultra-thick metal feature is configured in a coil-like pattern, and the fourth ultra-thick metal feature is configured in a coil-like pattern. In some embodiments, the second ultra-thick metal feature is configured to have a first number of turns, and the fourth ultra-thick metal feature is configured to have a second number of turns different from the first number of turns.

[0191] This disclosure provides another semiconductor device structure. The semiconductor device structure includes a device layer, an interconnect structure, a first ultra-thick metal structure, a second ultra-thick metal structure, and a third ultra-thick metal structure. The interconnect structure is on the device layer. The first ultra-thick metal structure is on the interconnect structure, wherein the first ultra-thick metal structure includes a first ultra-thick metal feature, a second ultra-thick metal feature disposed around the first ultra-thick metal feature, and a first dielectric layer separating the first ultra-thick metal feature and the second ultra-thick metal feature, wherein the second ultra-thick metal feature has a second width smaller than the first width of the first ultra-thick metal feature. The second ultra-thick metal structure is on the first ultra-thick metal structure, wherein the second ultra-thick metal structure includes a third ultra-thick metal feature, a fourth ultra-thick metal feature disposed around the third ultra-thick metal feature, and a second dielectric layer separating the third ultra-thick metal feature and the fourth ultra-thick metal feature. The third ultra-thick metal structure is on the second ultra-thick metal structure, wherein the third ultra-thick metal structure includes a fifth ultra-thick metal feature, a sixth ultra-thick metal feature disposed around the fifth ultra-thick metal feature, and a third dielectric layer separating the fifth ultra-thick metal feature and the sixth ultra-thick metal feature.

[0192] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications to this disclosure without departing from its spirit and scope.

Claims

1. A semiconductor device structure, characterized in that, include: One device layer; An interconnect structure comprising multiple metal layers disposed on the device layer; as well as An ultra-thick metal structure is disposed on the interconnect structure, the ultra-thick metal structure comprising: A first ultra-thick metal feature, having a first width; as well as A second ultra-thick metal feature is disposed around the first ultra-thick metal feature, wherein the second ultra-thick metal feature has a second width smaller than the first width, and the second ultra-thick metal feature is separated from the first ultra-thick metal feature by a dielectric layer.

2. The semiconductor device structure as described in claim 1, characterized in that, The first ultra-thick metal feature is a columnar structure.

3. The semiconductor device structure as described in claim 2, characterized in that, The second ultra-thick metal feature includes multiple separate metal lines.

4. The semiconductor device structure as described in any one of claims 1 to 2, characterized in that, One of the plurality of metal layers disposed immediately above the device layer has a first thickness, and the ultra-thick metal structure has a second thickness greater than the first thickness.

5. A semiconductor device structure, characterized in that, include: An interconnect structure comprising multiple metal layers disposed on a device layer; A first ultra-thick metal structure is disposed on the interconnect structure, the first ultra-thick metal structure comprising: The first ultra-thick metal feature; and A second ultra-thick metal feature is adjacent to the first ultra-thick metal feature, wherein a first dielectric layer is between the first ultra-thick metal feature and the second ultra-thick metal feature, and the second ultra-thick metal feature has a second width smaller than a first width of the first ultra-thick metal feature; and a second ultra-thick metal structure is disposed on the first ultra-thick metal structure, the second ultra-thick metal structure comprising: A third ultra-thick metal feature; and A fourth ultra-thick metal feature is disposed around the third ultra-thick metal feature, wherein the fourth ultra-thick metal feature is separated from the third ultra-thick metal feature by a second dielectric layer.

6. The semiconductor device structure as described in claim 5, characterized in that, The first ultra-thick metal feature is a columnar structure, and the third ultra-thick metal feature is a columnar structure.

7. The semiconductor device structure as described in claim 6, characterized in that, The first ultra-thick metal feature has a first number of columnar structures, and the third ultra-thick metal feature has a second number of columnar structures that is different from the first number.

8. The semiconductor device structure as described in claim 7, characterized in that, The second ultra-thick metal feature is configured in a coil-like pattern, and the fourth ultra-thick metal feature is configured in a coil-like pattern.

9. The semiconductor device structure as described in claim 8, characterized in that, The second ultra-thick metal feature is configured to have a first number of turns, and the fourth ultra-thick metal feature is configured to have a second number of turns that is different from the first number of turns.

10. A semiconductor device structure, characterized in that, include: One device layer; An interconnect structure is located on the device layer; A first ultra-thick metal structure is provided on the interconnect structure, wherein the first ultra-thick metal structure includes a first ultra-thick metal feature, a second ultra-thick metal feature disposed around the first ultra-thick metal feature, and a first dielectric layer separating the first ultra-thick metal feature and the second ultra-thick metal feature, wherein the second ultra-thick metal feature has a second width smaller than a first width of the first ultra-thick metal feature. A second ultra-thick metal structure is on the first ultra-thick metal structure, wherein the second ultra-thick metal structure includes a third ultra-thick metal feature, a fourth ultra-thick metal feature disposed around the third ultra-thick metal feature, and a second dielectric layer separating the third ultra-thick metal feature and the fourth ultra-thick metal feature. as well as A third ultrathick metal structure is on the second ultrathick metal structure, wherein the third ultrathick metal structure includes a fifth ultrathick metal feature, a sixth ultrathick metal feature disposed around the fifth ultrathick metal feature, and a third dielectric layer separating the fifth ultrathick metal feature and the sixth ultrathick metal feature.

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