Dynamic performance test circuit, system and module of three-phase full-bridge MOS module

Abstract

The utility model discloses a dynamic performance test circuit, system and module of a three-phase full-bridge MOS module. The dynamic performance test circuit is configured with a switch U1, a switch U2, a switch U3, a switch U4, a switch U5, a switch U6, an inductor L1 and an inductor L2. According to the dynamic performance test circuit, the switches U1-U6 are configured, a circuit loop used for a double-pulse test and a circuit loop used for a short-circuit test are constructed by controlling the on and off of the switches U1-U6, the double-pulse test and the short-circuit test can be carried out on the same circuit, and the test cost is effectively reduced.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the field of electronic circuit, especially is involved in a kind of dynamic performance test circuit, system and module of three-phase full-bridge MOS module. BACKGROUND

[0002] Three-phase full-bridge composed of MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistor) is a common power electronic circuit structure, used for controlling and converting electric energy. This circuit is very useful in many industrial applications, especially in situations that require efficient and accurate power control. A three-phase full-bridge is usually composed of three upper bridge arms MOS tubes and three lower bridge arms MOS tubes, and the three-phase full-bridge circuit composed of MOS tubes is widely used in motor drives, frequency converters, uninterruptible power supplies, renewable energy systems and power converters in many industries. By precisely controlling the turn-on and turn-off of MOS tubes, it realizes efficient and reliable energy conversion and control.

[0003] Through double-pulse testing, the switching characteristics of MOS tubes under actual working conditions can be evaluated, including turn-on time, turn-off time, switching loss, etc. This is crucial to ensure the performance of MOS tubes in high-frequency and high-power applications. Short-circuit testing can verify the protection and tolerance of MOS tubes when a short-circuit fault occurs, which helps to ensure that MOS tubes can safely turn off under extreme conditions and will not be damaged by overheating or overcurrent. At the same time, double-pulse and short-circuit testing can more comprehensively detect various potential faults of MOS tubes, such as poor welding, internal defects, etc. This helps to improve the reliability of the entire system. Through repeated double-pulse and short-circuit testing, the performance degradation of MOS tubes over time can be evaluated, thus predicting their service life. According to the test results, the parameters of the drive circuit (such as gate resistance, drive voltage) can be optimized to obtain the best switching characteristics and minimum loss.

[0004] In existing designs, dynamic performance testing is usually only performed on one tube, such as double-pulse testing, which cannot perform comprehensive dynamic performance testing. UTILITY MODEL CONTENT

[0005] To solve the technical problems existing in the prior art, the utility model provides a dynamic performance test circuit for a three-phase full-bridge MOS module, which can perform both double-pulse testing and short-circuit testing, effectively reducing testing costs.

[0006] The dynamic performance test circuit provided by the utility model is configured with switches U1, U2, U3, U4, U5, U6, inductors L1 and L2;

[0007] One end of the switch U1 is connected to the first connection end of the circuit, and is used for connecting the first end of the three-phase full-bridge upper bridge MOS tube Q1, the MOS tube Q3 and the MOS tube Q5 and the excitation input; the other end is connected to one end of the switch U4, and is used as the second connection end of the circuit, and is used for connecting the third end of the three-phase full-bridge upper bridge MOS tube Q1; the other end of the switch U4 is used as the third connection end of the circuit, and is used for connecting the third end of the three-phase full-bridge lower bridge MOS tube Q2, the MOS tube Q4 and the MOS tube Q6 and the excitation input;

[0008] One end of the switch U2 is connected to the first connection end, and the other end is connected to one end of the switch U3, one end of the switch U5 and one end of the switch U6 through the inductor L1;

[0009] The other end of the switch U3 is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to the third connection end;

[0010] The other end of the switch U5 is used as the fourth connection end of the circuit, and is used for connecting the third end of the three-phase full-bridge upper bridge MOS tube Q3;

[0011] The other end of the switch U6 is used as the fifth connection end of the circuit, and is used for connecting the third end of the three-phase full-bridge upper bridge MOS tube Q5.

[0012] Further, the circuit is further configured with a switch Q7, and the excitation is input to the first connection end through the switch Q7.

[0013] Further, the circuit is further configured with resistors R1-R6 and capacitors C2-C7;

[0014] One end of the resistor R1 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C2; the second plate of the capacitor C2 is connected to the second connection end;

[0015] One end of the resistor R2 is connected to the second connection end, and the other end is connected to the first plate of the capacitor C3; the second plate of the capacitor C3 is connected to the third connection end;

[0016] One end of the resistor R3 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C4; the second plate of the capacitor C4 is connected to the fourth connection end;

[0017] One end of the resistor R4 is connected to the fourth connection end, and the other end is connected to the first plate of the capacitor C5; the second plate of the capacitor C5 is connected to the third connection end;

[0018] One end of the resistor R5 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C6; the second plate of the capacitor C6 is connected to the fifth connection end;

[0019] One end of the resistor R6 is connected to the fifth connection end, and the other end is connected to the first plate of the capacitor C7, and the second plate of the capacitor C7 is connected to the third connection end.

[0020] Further, the circuit is further configured with a capacitor C1 for decoupling and filtering the excitation.

[0021] Further, the circuit is further configured with a resistor R7, one end of the resistor R7 is connected to the third connection end and serves as the sixth connection end of the circuit for connecting to an external circuit, and the other end serves as the seventh connection end of the circuit for excitation access.

[0022] Further, the circuit is further configured with a diode D1, and the excitation is accessed to the first connection end through the diode D1 in a forward direction.

[0023] The utility model further provides a kind of dynamic performance test system of three-phase full-bridge MOS module, and the system is configured with:

[0024] Dynamic performance test circuit, for being connected with measured three-phase full-bridge circuit, and with measured MOS tube to form double-pulse test loop or short-circuit test loop;

[0025] Pulse signal generating circuit, for generating the pulse signal required for double-pulse test, short-circuit test, control measured MOS tube conduction, cutoff;

[0026] Acquisition device, for acquiring the current and voltage of measured MOS tube during double-pulse test, short-circuit test;The dynamic performance test circuit of the utility model provides dynamic performance test circuit.

[0027] The utility model third aspect provides a kind of three-phase full-bridge MOS module, and the module is configured with three-phase full-bridge circuit mainly by MOS tube Q1-MOS tube Q6 and dynamic performance test circuit for carrying out dynamic test to the three-phase full-bridge circuit;

[0028] The dynamic performance test circuit includes switch U1, switch U2, switch U3, switch U4, switch U5, switch U6, inductance L1 and inductance L2;

[0029] One end of the switch U1 is connected to the first end of the MOS tube Q1, the MOS tube Q3 and the MOS tube Q5, and serves as the first connection end of the test circuit for excitation access;The other end is connected to the third end of the MOS tube Q1 and one end of the switch U4;The other end of the switch U4 is connected to the third end of the MOS tube Q2, the MOS tube Q4 and the MOS tube Q6, and serves as the third connection end of the test circuit for excitation access;

[0030] One end of the switch U2 is connected to the first connection end, and the other end is connected to one end of the switch U3, one end of the switch U5, one end of the switch U6, and the third end of the MOS tube Q1 through the inductor L1;

[0031] The other end of the switch U3 is connected to one end of the inductor L2, and the inductor L2 is connected to the third connection end;

[0032] The other end of the switch U5 is connected to the third end of the MOS tube Q3;

[0033] The other end of the switch U6 is connected to the third end of the MOS tube Q5.

[0034] Further, the module is also configured with a switch Q7, and the first connection end is accessed through the switch Q7.

[0035] Further, the module is also configured with resistors R1-R6 and capacitors C2-C7;

[0036] One end of the resistor R1 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C2, and the second plate of the capacitor C2 is connected to the third end of the MOS tube Q1;

[0037] One end of the resistor R2 is connected to the third end of the MOS tube, and the other end is connected to the first plate of the capacitor C3, and the second plate of the capacitor C3 is connected to the third connection end;

[0038] One end of the resistor R3 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C4, and the second plate of the capacitor C4 is connected to the third end of the MOS tube Q3;

[0039] One end of the resistor R4 is connected to the third end of the MOS tube Q3, and the other end is connected to the first plate of the capacitor C5, and the second plate of the capacitor C5 is connected to the third connection end;

[0040] One end of the resistor R5 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C6, and the second plate of the capacitor C6 is connected to the third end of the MOS tube Q5;

[0041] One end of the resistor R6 is connected to the third end of the MOS tube Q5, and the other end is connected to the first plate of the capacitor C7, and the second plate of the capacitor C7 is connected to the third connection end.

[0042] The utility model discloses a beneficial effect: the utility model discloses dynamic performance test circuit configuration switch U1 - switch U6, through the conduction, cut -off of control switch U1 - switch U6, constructs into the circuit loop for double -pulse test, the circuit loop of short -circuit test, realizes same circuit can carry out double -pulse test, can also carry out short -circuit test, effectively reduces test cost. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application, the drawings needed to be used or involved in the embodiments will be simply introduced below, and obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor:

[0044] Figure 1 The utility model provides dynamic performance test circuit's circuit principle drawing. DETAILED DESCRIPTION

[0045] This part refers to the drawings to more fully describe the utility model, and the illustrative embodiments of the utility model are shown in the drawings. However, the utility model also embodies in many different forms and should not be understood as limiting to the embodiments described here. On the contrary, these embodiments are provided in order to make the disclosure sufficient and complete, and to fully convey the scope of the utility model to the person skilled in the art.

[0046] Unless defined contrary, all terms (including technical and scientific terms) used here have the same meaning as that generally understood by the person skilled in the art to which the utility model belongs. It will be further understood that the terms such as defined in the commonly used dictionary should be interpreted as having the meaning consistent with its meaning in the relevant field, and will not be interpreted according to the idealized or very formal meaning, unless specifically defined here.

[0047] Now the example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be understood as limiting to the examples set forth here; on the contrary, these embodiments are provided so that the utility model will be more comprehensive and complete, and the ideas of the example embodiments will be fully conveyed to the person skilled in the art. EMBODIMENTS

[0048] Please refer to Figure 1The dynamic performance test circuit of the three-phase full-bridge MOS module provided in this embodiment is configured with switches U1, U2, U3, U4, U5, U6, inductor L1, and inductor L2. One end of switch U1 serves as the first connection terminal of the circuit, used to connect to the first terminals of the three-phase full-bridge upper-bridge MOS transistors Q1, Q3, and Q5 and to provide excitation input. The other end is connected to one end of switch U4 and serves as the second connection terminal of the circuit, used to connect to the third terminal of the three-phase full-bridge upper-bridge MOS transistor Q1. The other end of switch U4 serves as the third connection terminal of the circuit, used to connect to the third terminals of the three-phase full-bridge lower-bridge MOS transistors Q2, Q4, and Q6 and to provide excitation input. One end of switch U2 is connected to the first connection terminal, and the other end is connected to one end of switch U3, one end of switch U5, and one end of switch U6 via inductor L1. The end of switch U3 connected to inductor L1 is also connected to the second connection terminal, the other end of switch U3 is connected to one end of inductor L2, and the other end of inductor L2 is connected to the third connection terminal.

[0049] The other end of switch U5 serves as the fourth connection terminal of the circuit, used to connect to the third terminal of the three-phase full-bridge MOSFET Q3; the other end of switch U6 serves as the fifth connection terminal of the circuit, used to connect to the third terminal of the three-phase full-bridge MOSFET Q5.

[0050] The “excitation” described refers to the power supply + (e.g., +5V, +10V, +12V), ground, or power supply - (e.g., -5V, -10V, -12V) required by the circuit. As shown in the figure, VCC is the power supply +, and GND is the ground or power supply -, which is configured according to the circuit structure.

[0051] When this test circuit is applied, it should be in accordance with... Figure 1 The connections shown are used to connect the upper and lower bridge MOSFETs of the three-phase full-bridge circuit. The dual-pulse test circuit is built as follows:

[0052] When performing a double-pulse test on MOSFET Q1, the control drive signal turns off MOSFETs Q2, Q3, Q4, Q5, and Q6, and the excitation is connected to the first and third connection terminals. The control switch U3 is closed, and switches U1, U2, U4, U5, and U6 are opened. At this time, MOSFET Q2 is the companion test tube for MOSFET Q1.

[0053] During the double-pulse test of MOSFET Q2, the control drive signal turns off MOSFETs Q1, Q3, Q4, Q5, and Q6, and the excitation is connected to the first and third connection terminals. Control switch U2 is closed, and switches U1, U3, U4, U5, and U6 are open. At this time, MOSFET Q1 acts as a test tube for MOSFET Q2.

[0054] When the double pulse test of MOS tube Q3 is performed, the control drive signal is controlled to turn off MOS tube Q1, MOS tube Q2, MOS tube Q4, MOS tube Q5 and MOS tube Q6, and the first connecting end and the third connecting end are excited. The switch U3 and the switch U5 are controlled to be closed, and the switch U1, the switch U2, the switch U4 and the switch U6 are controlled to be opened. At this time, MOS tube Q4 is the test tube of MOS tube Q3.

[0055] When the double pulse test of MOS tube Q4 is performed, the control drive signal is controlled to turn off MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q5 and MOS tube Q6, and the first connecting end and the third connecting end are excited. The switch U2 and the switch U5 are controlled to be closed, and the switch U1, the switch U3, the switch U4 and the switch U6 are controlled to be opened. At this time, MOS tube Q3 is the test tube of MOS tube Q4.

[0056] When the double pulse test of MOS tube Q5 is performed, the control drive signal is controlled to turn off MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4 and MOS tube Q6, and the first connecting end and the third connecting end are excited. The switch U3 and the switch U6 are controlled to be closed, and the switch U1, the switch U2, the switch U4 and the switch U5 are controlled to be opened. At this time, MOS tube Q6 is the test tube of MOS tube Q5.

[0057] When the double pulse test of MOS tube Q6 is performed, the control drive signal is controlled to turn off MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4 and MOS tube Q5, and the first connecting end and the third connecting end are excited. The switch U2 and the switch U6 are controlled to be closed, and the switch U1, the switch U3, the switch U4 and the switch U5 are controlled to be opened. At this time, MOS tube Q5 is the test tube of MOS tube Q6.

[0058] After the above circuit is built, the double pulse test circuit of MOS tube Q1-MOS tube Q6 is formed. The double pulse test is usually performed in the form of a half bridge. During the test process, the upper tube is continuously turned off, and the lower tube is driven by a given two pulses, so as to test the switching characteristics of the lower tube. An inductor is connected in parallel with the upper tube, and the characteristics of the lower tube and the reverse diode characteristics of the upper tube are mainly tested. During the test process, a first pulse is first applied, the switch tube is saturated and turned on, and the inductor current linearly rises. Then, after the first pulse ends, the inductor current is continued by the upper tube diode. Then, a second pulse is applied, the switch tube is turned on again, the continuation diode enters reverse recovery, and the reverse recovery current will pass through the switch tube. Similarly, when the upper tube is tested, the inductor is connected in parallel with the DS of the lower tube, the lower tube is continuously turned off, and the upper tube is driven by two pulses.

[0059] In the double-pulse test of MOSFET, the accompanying tube is mainly used to simulate the switching behavior of the measured MOS tube in the actual application environment, so as to more accurately evaluate the performance of the main test MOSFET. The diode (usually an anti-parallel diode) in the accompanying tube mainly plays a protective role. Specifically, it can prevent the MOSFET from being damaged due to voltage reversal during turn-off. In addition, the diode can also help to quickly release the energy stored in the internal capacitor of the MOSFET, thereby reducing oscillation and overshoot phenomena during turn-off. This helps to more accurately evaluate the switching characteristics and losses of the MOSFET.

[0060] The short circuit test is usually to test the maximum current, voltage, recovery capability and thermal characteristics of the MOS tube when the upper tube or lower tube is short-circuited in the circuit, causing the power supply voltage to be directly applied across the other MOS tube in the half-bridge. In actual testing, the short circuit of the MOS tube to be tested is simulated by short-circuiting the DS of the accompanying tube. The circuit for short circuit test is built as follows:

[0061] When performing short circuit test on MOS tube Q1, control the drive signal to turn off MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q5, MOS tube Q6, and excite the first connection end and the third connection end. Control switch U4 to close and switches U1, U2, U3, U5, U6 to open, at this time MOS tube Q2 is the accompanying tube of MOS tube Q1.

[0062] When performing short circuit test on MOS tube Q2, control the drive signal to turn off MOS tube Q1, MOS tube Q3, MOS tube Q4, MOS tube Q5, MOS tube Q6, and excite the first connection end and the third connection end. Control switch U1 to close and switches U2, U3, U4, U5, U6 to open, at this time MOS tube Q1 is the accompanying tube of MOS tube Q2.

[0063] When performing short circuit test on MOS tube Q3, control the drive signal to turn off MOS tube Q1, MOS tube Q2, MOS tube Q4, MOS tube Q5, MOS tube Q6, and excite the first connection end and the third connection end. Control switches U4, U5 to close and switches U1, U2, U3, U6 to open, at this time MOS tube Q4 is the accompanying tube of MOS tube Q3.

[0064] When performing short circuit test on MOS tube Q4, control the drive signal to turn off MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q5, MOS tube Q6, and excite the first connection end and the third connection end. Control switches U1, U5 to close and switches U2, U3, U4, U6 to open, at this time MOS tube Q3 is the accompanying tube of MOS tube Q4.

[0065] When performing the short circuit test of MOS tube Q5, the drive signal is controlled to turn off MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q6, and the first connection end and the third connection end are excited. The switches U4 and U6 are controlled to be closed, and the switches U1, U2, U3 and U5 are controlled to be open. At this time, MOS tube Q6 is the auxiliary tube of MOS tube Q5.

[0066] When performing the short circuit test of MOS tube Q6, the drive signal is controlled to turn off MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q5, and the first connection end and the third connection end are excited. The switches U1 and U6 are controlled to be closed, and the switches U2, U3, U4 and U5 are controlled to be open. At this time, MOS tube Q5 is the auxiliary tube of MOS tube Q6.

[0067] In the short circuit test of MOSFET, the diode in the auxiliary tube also plays an important protective and auxiliary role. The auxiliary tube can help simulate the load conditions in actual applications, making the test results closer to the actual situation. The auxiliary tube can share part of the current, reducing the current stress of the main test MOSFET in the short circuit test, thereby reducing the risk of damage to the main test MOSFET. The presence of the auxiliary tube can reduce interference and fluctuations in the test, making the test results more stable and reliable. This helps to more accurately evaluate the performance and tolerance of MOSFET under short circuit conditions. The auxiliary tube can be used to assist in measuring parameters such as voltage drop and temperature change of the main test MOSFET, thereby providing more comprehensive data support.

[0068] According to the above description, a double pulse test circuit and a short circuit test circuit are formed, and a pulse signal generation circuit for generating the pulse signals required for double pulse testing and short circuit testing is configured. The pulse signal generation circuit controls the conduction and cutoff of the measured MOS tube, the upper and lower bridge MOS tubes of the three-phase full-bridge, and the switches U1-U6. A collection device for collecting the current and voltage of the measured MOS tube during double pulse testing and short circuit testing is also configured. The collection device can be any device capable of collecting the current and voltage of the measured MOS tube, such as an oscilloscope. The probe of the oscilloscope is connected to the measured MOS tube to collect the current and voltage. Based on the current and voltage, the dynamic performance parameters of the measured MOS tube, such as turn-on loss and turn-off loss, are calculated.

[0069] The test circuit for double pulse testing and short circuit testing has an auxiliary tube, which has the following advantages:

[0070] 1. Protect the DUT MOSFET: During short circuit testing, the DUT MOSFET can be subjected to high current and voltage stress. The diode in the companion tube can prevent the DUT MOSFET from being damaged by reverse voltage, especially when the DUT MOSFET is turned off.

[0071] 2. Fast discharge: The diode in the companion tube can help quickly discharge the energy in the internal capacitance of the DUT MOSFET, reducing oscillation and overshoot during the turn-off process, thereby reducing the stress on the DUT MOSFET under short circuit conditions.

[0072] 3. Improve test results: By reducing oscillation and overshoot, the diode in the companion tube helps provide more accurate test results, allowing engineers to more realistically evaluate the performance and reliability of the DUT MOSFET under short circuit conditions. Embodiment

[0073] Please refer to Figure 1 , the dynamic performance test circuit provided by the embodiment is further configured with switch Q7, and the control of the test circuit excitation access is realized by controlling the conduction and cutoff of switch Q7. When performing double-pulse testing and short circuit testing, switch Q7 is in a normally closed state. Embodiment

[0074] Please refer to Figure 1 , the dynamic performance test circuit provided by the embodiment is further configured with resistors R1-R6 and capacitors C2-C7; one end of resistor R1 is connected to the first connection end, and the other end is connected to the first plate of capacitor C2, and the second plate of capacitor C2 is connected to the second connection end; one end of resistor R2 is connected to the second connection end, and the other end is connected to the first plate of capacitor C3, and the second plate of capacitor C3 is connected to the third connection end; one end of resistor R3 is connected to the first connection end, and the other end is connected to the first plate of capacitor C4, and the second plate of capacitor C4 is connected to the fourth connection end; one end of resistor R4 is connected to the fourth connection end, and the other end is connected to the first plate of capacitor C5, and the second plate of capacitor C5 is connected to the third connection end; one end of resistor R5 is connected to the first connection end, and the other end is connected to the first plate of capacitor C6, and the second plate of capacitor C6 is connected to the fifth connection end; one end of resistor R6 is connected to the fifth connection end, and the other end is connected to the first plate of capacitor C7, and the second plate of capacitor C7 is connected to the third connection end.

[0075] When the circuit of the embodiment is connected with a three-phase full-bridge MOS module, the connection relationship of resistors R1-R6 and capacitors C2-C7 is as follows Figure 1As shown, the resistance R1 and the capacitor C2, the resistance R2 and the capacitor C3, the resistance R3 and the capacitor C4, the resistance R4 and the capacitor C5, the resistance R5 and the capacitor C6, the resistance R6 and the capacitor C7 are the RC filter circuit of the MOS tube Q1, the MOS tube Q2, the MOS tube Q3, the MOS tube Q4, the MOS tube Q5, the MOS tube Q6 respectively, inhibit high frequency noise in the process of opening and closing of the MOS tube Q1-MOS tube Q6, smooth the voltage peak or oscillation of the switching transient, so that the signal output is more stable and reliable. Embodiment

[0076] Please refer to Figure 1 , the dynamic performance test circuit provided in the embodiment is further configured with the capacitor C1 for decoupling and filtering the excitation on the basis of the first embodiment, the second embodiment, the third embodiment. Embodiment

[0077] Please refer to Figure 1 , the dynamic performance test circuit provided in the embodiment is further configured with the resistance R7 on the basis of the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, one end of the resistance R7 is connected to the third connection end and serves as the sixth connection end of the circuit for connecting the external circuit, and the other end serves as the seventh connection end of the circuit for connecting the excitation.

[0078] R7 is an overcurrent protection resistance, when the current reaches the limit value, a feedback signal is fed back to the external control circuit, and the switching devices (switches U1-U6, switch Q7) in the external control circuit or the MOS tubes in the three-phase full bridge are turned off, thereby protecting the circuit. The external control circuit can be a pulse signal generating circuit. Embodiment

[0079] Please refer to Figure 1 , the dynamic performance test circuit provided in the embodiment is further configured with the diode D1 on the basis of the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, and the excitation is connected to the first connection end through the diode D1. The diode D1 prevents current backflow and reverse connection, and protects the circuit.

[0080] The circuit structure of the technical scheme realizes the short circuit and double pulse test of the three-phase full bridge MOS module in the same circuit, makes the evaluation of the three-phase full bridge MOS module more convenient and comprehensive, and at the same time reduces the V DS oscillation interference of the measured MOS tube drain-source voltage, enhances the accuracy of the experiment; the test circuit has strong anti-interference ability and high safety, and in actual application, the test efficiency is improved while the cost is low.

[0081] The above examples are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced without departing from the purpose and scope of the present application, and all should be covered in the scope of the claims of the present application. The technical, shape and structure parts not described in detail in the present application are all known technologies.

Claims

1. A dynamic performance test circuit for a three-phase full-bridge MOS module, characterized by, The circuit is configured with switches U1, U2, U3, U4, U5, U6, inductors L1 and L2; One end of the switch U1 is used as the first connection end of the circuit, for connecting the first ends of the three-phase full-bridge upper bridge MOS tubes Q1, Q3 and Q5 and for excitation access; the other end is connected to one end of the switch U4 and is used as the second connection end of the circuit, for connecting the third end of the three-phase full-bridge upper bridge MOS tube Q1; the other end of the switch U4 is used as the third connection end of the circuit, for connecting the third ends of the three-phase full-bridge lower bridge MOS tubes Q2, Q4 and Q6 and for excitation access; One end of the switch U2 is connected to the first connection end, and the other end is connected to one end of the switch U3, one end of the switch U5 and one end of the switch U6 through the inductor L1; The other end of the switch U3 is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to the third connection end; The other end of the switch U5 is used as the fourth connection end of the circuit, for connecting the third end of the three-phase full-bridge upper bridge MOS tube Q3; The other end of the switch U6 is used as the fifth connection end of the circuit, for connecting the third end of the three-phase full-bridge upper bridge MOS tube Q5.

2. The dynamic performance test circuit for a three-phase full-bridge MOS module of claim 1, wherein, The circuit is further configured with a switch Q7, and excitation is accessed to the first connection end through the switch Q7.

3. The dynamic performance test circuit for a three-phase full-bridge MOS module of claim 1, wherein, The circuit is further configured with resistors R1-R6 and capacitors C2-C7; One end of the resistor R1 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C2; the second plate of the capacitor C2 is connected to the second connection end; One end of the resistor R2 is connected to the second connection end, and the other end is connected to the first plate of the capacitor C3; the second plate of the capacitor C3 is connected to the third connection end; One end of the resistor R3 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C4; the second plate of the capacitor C4 is connected to the fourth connection end; One end of the resistor R4 is connected to the fourth connection end, and the other end is connected to the first plate of the capacitor C5; the second plate of the capacitor C5 is connected to the third connection end; One end of the resistor R5 is connected to the first connection end, and the other end is connected to the first plate of the capacitor C6; the second plate of the capacitor C6 is connected to the fifth connection end; One end of the resistor R6 is connected to the fifth connection end, and the other end is connected to the first plate of the capacitor C7; the second plate of the capacitor C7 is connected to the third connection end.

4. The dynamic performance test circuit for a three-phase full-bridge MOS module of claim 1, wherein, The circuit is further configured with a capacitor C1 for decoupling and filtering excitation.

5. The dynamic performance test circuit for a three-phase full-bridge MOS module of claim 4, wherein, The circuit is further configured with a resistor R7, one end of the resistor R7 is connected to the third connection end and is used as the sixth connection end of the circuit, for connecting an external circuit; the other end is used as the seventh connection end of the circuit, for excitation access.

6. The dynamic performance test circuit for a three-phase full-bridge MOS module according to any one of claims 1-5, wherein, The circuit is further configured with a diode D1, and excitation is accessed to the first connection end through the diode D1 in the forward direction.

7. A dynamic performance test system for a three-phase full-bridge MOS module, characterized by, The system is configured with: a dynamic performance test circuit, for connecting with a measured three-phase full-bridge circuit and forming a double-pulse test loop or a short-circuit test loop with a measured MOS tube; The pulse signal generating circuit is used for generating pulse signals required by double pulse test and short circuit test, and controlling the on and off of the MOS tube to be tested. The acquisition device is used for acquiring the current and voltage of the MOS tube to be tested during the double pulse test and short circuit test.

8. A three-phase full-bridge MOS module, characterized by The module is configured with a three-phase full-bridge circuit mainly composed of MOS tubes Q1-Q6 and a dynamic performance test circuit used for dynamically testing the three-phase full-bridge circuit. The dynamic performance test circuit comprises switches U1, U2, U3, U4, U5, U6, inductors L1 and L2. One end of the switch U1 is connected to the first ends of the MOS tubes Q1, Q3 and Q5, and serves as a first connection end of the test circuit for excitation access; the other end of the switch U1 is connected to the third end of the MOS tube Q1 and one end of the switch U4; the other end of the switch U4 is connected to the third ends of the MOS tubes Q2, Q4 and Q6, and serves as a third connection end of the test circuit for excitation access; One end of the switch U2 is connected to the first connection end, and the other end of the switch U2 is connected to one end of the switch U3, one end of the switch U5, one end of the switch U6 and the third end of the MOS tube Q1 through the inductor L1; The other end of the switch U3 is connected to one end of the inductor L2, and the inductor L2 is connected to the third connection end; The other end of the switch U5 is connected to the third end of the MOS tube Q3; The other end of the switch U6 is connected to the third end of the MOS tube Q5.

9. The three-phase full-bridge MOS module of claim 8, wherein, The module is further configured with a switch Q7, and excitation is accessed to the first connection end through the switch Q7.

10. The three-phase full-bridge MOS module according to claim 8 or 9, characterized in that, The module is further configured with resistors R1-R6 and capacitors C2-C7; One end of the resistor R1 is connected to the first connection end, and the other end of the resistor R1 is connected to the first plate of the capacitor C2; the second plate of the capacitor C2 is connected to the third end of the MOS tube Q1; One end of the resistor R2 is connected to the third end of the MOS tube, and the other end of the resistor R2 is connected to the first plate of the capacitor C3; the second plate of the capacitor C3 is connected to the third connection end; One end of the resistor R3 is connected to the first connection end, and the other end of the resistor R3 is connected to the first plate of the capacitor C4; the second plate of the capacitor C4 is connected to the third end of the MOS tube Q3; One end of the resistor R4 is connected to the third end of the MOS tube Q3, and the other end of the resistor R4 is connected to the first plate of the capacitor C5; the second plate of the capacitor C5 is connected to the third connection end; One end of the resistor R5 is connected to the first connection end, and the other end of the resistor R5 is connected to the first plate of the capacitor C6; the second plate of the capacitor C6 is connected to the third end of the MOS tube Q5; One end of the resistor R6 is connected to the third end of the MOS tube Q5, and the other end of the resistor R6 is connected to the first plate of the capacitor C7; the second plate of the capacitor C7 is connected to the third connection end.

Images