Slave based on SPI communication and communication system
By designing a control unit and chip select signal management mechanism in the SPI communication system, the problem of limited number of slave devices was solved, and efficient communication between multiple slave devices was achieved.
Patent Information
- Application Number
- CN202422820908.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2034-11-19
AI Technical Summary
In SPI communication, the number of slave devices is limited by the resource constraints of the chip select output on the master device, which prevents the number of slave devices from being expanded.
Design an SPI-based slave device, including a control unit, a chip select input terminal, and a chip select output terminal. The control unit controls the output signal of the chip select terminal according to the chip select signal to realize the address setting and communication of multiple slave devices. The master only needs one chip select output terminal to communicate with multiple slave devices.
This effectively avoids the limitation on the number of slave devices and improves the scalability and communication efficiency of slave devices in the SPI communication system.
Smart Images
Figure CN223637978U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to communication technical field especially relates to a slave based on SPI communication and communication system. BACKGROUND
[0002] SPI (serial peripheral interface) bus technology is a kind of high-speed, synchronous, full-duplex communication bus technology, and SPI is a kind of serial peripheral interface, is a kind of high-speed, full-duplex communication serial bus interface, has the advantages such as simple communication, data transmission rate fast.
[0003] SPI works in master-slave communication mode, and SPI master (spimaster, host for short) provides clock signal for SPI communication, is the active party of communication, all communication is initiated by host, and host can initiate or stop communication at any time;SPI slave (spisalve, slave for short) is the passive party of SPI communication process, and the receiving and transmitting process is generally controlled by SPI master. Master-slave communication mode usually includes a host and one or more slaves, and four signals are transmitted in the communication process, which are clock signal (CLK), host output / slave input signal (MOSI), host input / slave output signal (MISO) and chip select signal (CS).
[0004] When SPI realizes one master and multiple slaves mode, the chip select input end of each slave has corresponding chip select output end on the host, and the host sends chip select signal to the corresponding chip select input end by selecting chip select output end to control the slave corresponding to the chip select input end to respond to the host for communication. At this time, each slave needs to use a chip select output end of the host for communication control, and since the resources on the host are limited, the number of chip select output ends that can be set on the host is limited, which easily leads to the limitation of the number of slaves. UTILITY MODEL CONTENTS
[0005] The utility model provides a communication system based on SPI can effectively avoid the number of slaves based on SPI communication is limited.
[0006] The utility model provides a slave based on SPI communication, and it includes:
[0007] Control unit, chip select input end and chip select output end, wherein,
[0008] Chip select input end and chip select output end are connected with control unit respectively, chip select input end is used to receive chip select signal, and control unit controls chip select output end to output chip select signal according to chip select signal.
[0009] Further, the slave further comprises a clock input end, a slave input end and a slave output end; wherein,
[0010] The clock input end, the slave input end and the slave output end are connected with the control unit respectively, the clock input end is used for receiving a clock signal, the slave signal input end is used for receiving a slave input signal, and the control unit controls the slave output end to output a slave output signal according to the clock signal, the chip selection signal and the slave input signal.
[0011] Further, the clock input end is a clock single-end input circuit, the slave input end is a slave single-end input circuit, and the slave output end is a slave single-end output circuit.
[0012] Further, the clock input end is a clock differential input circuit, the slave input end is a slave differential input circuit, and the slave output end is a slave differential output circuit.
[0013] Further, the clock differential input circuit and the slave differential input circuit are located in the same differential input circuit, or the clock differential input circuit and the slave differential input circuit are independent differential input circuits respectively.
[0014] The embodiment of the application further provides a SPI-based communication system, comprising a host and a plurality of above-mentioned slaves.
[0015] The host comprises a chip selection output end.
[0016] The slave comprises a chip selection input end and a chip selection output end.
[0017] The plurality of slaves are connected in sequence through the mode that the chip selection output end is connected with the chip selection input end, and the chip selection output end of the host is connected with the chip selection input end of the first slave.
[0018] Further, the host further comprises a clock output end, a host output end and a host input end, and the slave further comprises a clock input end, a slave input end and a slave output end.
[0019] The clock output end of the host is connected with the clock input end of each slave.
[0020] The host output end of the host is connected with the slave input end of each slave.
[0021] The host input end of the host is connected with the slave output end of each slave.
[0022] Further, the clock output end comprises a clock single-end output circuit, the host output end comprises a host single-end output circuit, and the host input end comprises a host single-end input circuit;
[0023] The clock input end comprises a clock single-end input circuit, the slave input end comprises a slave single-end input circuit, and the slave output end comprises a slave single-end output circuit;
[0024] The clock single-end output circuit of the host is connected with the clock single-end input circuit of each slave.
[0025] The host single-end output circuit of the host is connected with the slave single-end input circuit of each slave.
[0026] The host single-end input circuit of the host is connected with the slave single-end output circuit of each slave.
[0027] Further, the clock output end comprises a clock differential output circuit, the host output end comprises a host differential output circuit, and the host input end comprises a host differential input circuit;
[0028] The clock input end comprises a clock differential input circuit, the slave input end comprises a slave differential input circuit, and the slave output end comprises a slave differential output circuit;
[0029] The clock differential output circuit of the host is connected with the clock differential input circuit of each slave.
[0030] The host differential output circuit of the host is connected with the slave differential input circuit of each slave.
[0031] The host differential input circuit of the host is connected with the slave differential output circuit of each slave.
[0032] Further, the clock differential output circuit and the host differential output circuit are located in the same differential output circuit, or the clock differential output circuit and the host differential output circuit are independent differential output circuits.
[0033] The clock differential input circuit and the slave differential input circuit are located in the same differential input circuit, or the clock differential input circuit and the slave differential input circuit are independent differential input circuits.
[0034] The utility model further provides a kind of communication device, characterized by, using the communication of above-mentioned SPI-based communication system.
[0035] From the above technical solution, the utility model has the following advantages:
[0036] The slave machine based on SPI communication of the utility model, include: control unit, chip selection input and chip selection output, wherein, chip selection input and chip selection output are connected with control unit respectively, chip selection input is used for receiving chip selection signal, control unit controls chip selection output to output chip selection signal according to chip selection signal, when SPI communication contains multiple slave machines, host computer only needs a chip selection output to input chip selection signal to the chip selection input of one slave machine, and then make every slave machine receive chip selection signal, and do not need to configure a corresponding chip selection output on host computer for every slave machine, effectively avoid the number of slave machine based on SPI communication is limited. BRIEF DESCRIPTION OF DRAWINGS
[0037] In order to more clearly illustrate the technical scheme in the utility model, the following will be needed to use the drawing in the embodiment description briefly introduced, obviously, the drawing in the following description only is some embodiments of the application, for ordinary skilled person in the art, can also obtain other drawings according to these drawings.
[0038] Figure 1 It is one master-slave communication system diagram for the utility model discloses;
[0039] Figure 2 It is slave machine schematic diagram based on SPI communication for the utility model discloses;
[0040] Figure 3 It is communication system diagram based on SPI for the utility model discloses;
[0041] Figure 4 It is another communication system diagram based on SPI for the utility model discloses;
[0042] Figure 5 It is differential output circuit schematic diagram for the utility model discloses;
[0043] Figure 6 It is another differential output circuit schematic diagram for the utility model discloses;
[0044] Figure 7 It is differential input circuit schematic diagram for the utility model discloses;
[0045] Figure 8 It is another differential input circuit schematic diagram for the utility model discloses. DETAILED DESCRIPTION
[0046] In order to enable personnel in the technical field to better understand the scheme of the present application, the technical scheme in the present application will be clearly and completely described below in combination with the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.
[0047] In the description of the present application, it should be noted that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and are not intended to indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0048] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.
[0049] The existing SPI master-slave communication mode usually includes one host and one or more slaves, and four signals are transmitted in the communication process, which are clock signal (CLK), host output / slave input signal (MOSI), host input / slave output signal (MISO) and chip selection signal (CS). Each slave needs to use one chip selection output end of the host for communication control, and the more the number of slaves, the more chip selection output ends need to be set on the host, such as Figure 1 As shown, when the communication system includes three slaves, three chip selection output ends (CS1, CS2 and CS3) need to be set on the host. Since the resources on the host are limited, the chip selection output ends that can be set on the host are limited, which easily leads to the limitation of the number of slaves. Therefore, the present application provides a slave based on SPI communication, which can effectively avoid the limitation of the number of slaves based on SPI communication, as shown in Figure 2 The specific implementation is as follows:
[0050] The utility model discloses a slave based on SPI communication includes: control unit, slice selection input (CS end) and slice selection output (IO end), wherein, slice selection input and slice selection output are connected with control unit respectively, and slice selection input is used for receiving slice selection signal (CS signal), and control unit controls slice selection output to output slice selection signal according to slice selection signal.
[0051] Further, the slave further includes: a clock input end (CLK end), a slave input end (MOSI end) and a slave output end (MISO end); wherein, the clock input end, the slave input end and the slave output end are connected with the control unit respectively, the clock input end is used for receiving a clock signal (CLK signal), the slave signal input end is used for receiving a slave input signal (MOSI signal), and the control unit controls the slave output end to output a slave output signal according to the clock signal, the slice selection signal and the slave input signal. That is, when the slice selection signal selects the slave communication, and the clock signal is in the trigger state (such as the rising edge), the control unit can control the slave output end to output the slave output signal to respond to the slave input signal.
[0052] Further, when the slave in the SPI communication carries out short distance communication, single-ended signal can be used for communication; at this time, in the slave, the clock input end is a clock single-ended input circuit; the slave input end is a slave single-ended input circuit; and the slave output end is a slave single-ended output circuit. At this time, the clock signal (CLK signal), the slave input signal (MOSI signal) and the slave output signal (MISO signal) are all single-ended signals.
[0053] Further, when the slave in the SPI communication carries out long distance communication, if single-ended signal is used for communication, the single-ended signal takes signal ground as a reference point, the single-ended signal will attenuate and be easily interfered in the long distance transmission process, and the communication stability is poor in the long distance transmission process; at this time, differential signal can be used for communication to avoid signal interference and improve the communication stability.
[0054] Specifically, the clock input end of the slave machine is a clock differential input circuit; the slave machine input end is a slave machine differential input circuit; and the slave machine output end is a slave machine differential output circuit.
[0055] It can be understood that when the communication distance is less than the preset distance threshold, it is short distance communication, and when the communication distance is greater than or equal to the preset distance threshold, it is long distance communication; the preset distance threshold can be 100 centimeters, and the specific value is not limited here.
[0056] Further, the clock differential input circuit and the slave machine differential input circuit are located in the same differential input circuit, which can be a differential line receiver; or the clock differential input circuit and the slave machine differential input circuit are independent differential input circuits, which can be composed of electronic elements.
[0057] The utility model further provides a kind of communication system based on SPI, effectively avoid the quantity of slave machine in communication system is limited, as shown in Figure Figure 3 As shown in the following:
[0058] In the utility model, the communication system based on SPI includes: host computer and multiple above-mentioned slave machines;Specifically, the host computer includes: chip selection output end (CS end in host computer);The slave machine includes: chip selection input end (CS end in slave machine) and chip selection output end (I0 end in slave machine);Multiple slave machines are sequentially connected by the mode that chip selection output end and chip selection input end are connected, and the chip selection output end of host computer is connected with the chip selection input end of first-level slave machine;The host computer is used for sending chip selection signal to the chip selection input end of first-level slave machine through chip selection output end;The first-level slave machine is used for setting the address of first-level slave machine after receiving chip selection signal, and outputting chip selection signal to the chip selection input end of next-level host computer through chip selection output end, to control next-level slave machine to set address, and sequentially set the address of multiple slave machines.The address is the unique identification information of slave machine, for identifying and distinguishing different slave machines, and the address can be understood as station number or number of slave machine, and the specific value is not limited here.
[0059] The host can change the chip selection signal from high level to low level, at this time, the first slave machine receiving the low level chip selection signal sets its own address as 1; then the first slave machine outputs the chip selection signal to the next slave machine through the chip selection output terminal (IO terminal); at this time, the next slave machine sets its own address as 2 after receiving the chip selection signal and outputs the chip selection signal to the next slave machine through the chip selection output terminal, and the address setting of all slave machines is completed in this way. After setting the addresses of all slave machines, the one-host multi-slave communication operation is performed. The slave machine can return the address to the host after setting the address, at this time, the host can communicate with the slave machine based on the slave machine address.
[0060] It can be seen that, in the utility model, the SPI-based communication system comprises: a host and a plurality of slave machines, the plurality of slave machines are connected in sequence through the mode that the chip selection output terminal is connected with the chip selection input terminal, the chip selection output terminal of the host is connected with the chip selection input terminal of the first slave machine, the host sets the addresses of the plurality of slave machines one by one by sending the chip selection signal to the first slave machine, and the host communicates with the slave machine based on the slave machine address; at this time, the host only needs one chip selection output terminal to realize the communication with the plurality of slave machines, and it is not necessary to configure a corresponding chip selection output terminal on the host for each slave machine, thereby effectively avoiding that the number of slave machines in the communication system is limited.
[0061] Further, the host further comprises a clock output terminal (the CLK terminal in the host) and a host output terminal (the MOSI terminal in the host), and the slave machine further comprises a clock input terminal (the CLK terminal in the slave machine) and a slave machine input terminal (the MOSI terminal in the slave machine); the clock output terminal of the host is connected with the clock input terminal of each slave machine, and the host output terminal of the host is connected with the slave machine input terminal of each slave machine; the host is used for sending the clock signal and the host output signal to the clock input terminal and the slave machine input terminal of the plurality of slave machines through the clock output terminal and the host output terminal before sending the chip selection signal to the chip selection input terminal of the first slave machine, so that the plurality of slave machines enter the address setting state.
[0062] That is, the host can trigger the slave machine to set the address through the self-defined SPI protocol, specifically, the host can send the clock signal (CLK signal) and the host output signal (MOSI signal) to the plurality of slave machines, and the MOSI signal has the self-defined identification code data, and the slave machine receives the identification code data and is ready to set the address according to the received chip selection signal (CS signal).
[0063] Further, the host further comprises a host input terminal (the MISO terminal in the host), and the slave machine further comprises a slave machine output terminal (the MISO terminal in the slave machine); the host input terminal of the host is connected with the slave machine output terminal of each slave machine; the plurality of slave machines are further used for transmitting the slave machine address to the host through the slave machine output terminal of the slave machine after setting the address; and the host is further used for communicating with the slave machine based on the slave machine address.
[0064] It can be understood that after setting the addresses of all slaves, a master-slave communication operation is performed, that is, the master sends a clock signal (CLK signal) and a master output / slave input signal (MOSI signal) to all slaves, and the MOSI signal carries an identification code of the slave address, and the corresponding slave returns a signal to the master input terminal of the master through the slave output terminal after receiving the MOSI signal, and the other slaves do not send signals, thereby realizing the operation of the slave; and a master-slave communication mode with high efficiency is realized.
[0065] Further, when the master and the plurality of slaves are in single-board communication, that is, the master and the slave perform short-distance communication, such as communication within a PCB, the communication signals between the master and the plurality of slaves are single-ended signals.
[0066] Specifically, in the master, the clock output terminal includes a clock single-ended output circuit, the master output terminal includes a master single-ended output circuit, and the master input terminal includes a master single-ended input circuit; in the slave, the clock input terminal includes a clock single-ended input circuit, the slave input terminal includes a slave single-ended input circuit, and the slave output terminal includes a slave single-ended output circuit. The clock single-ended output circuit of the master is connected to the clock single-ended input circuit of each slave, the master single-ended output circuit of the master is connected to the slave single-ended input circuit of each slave, and the master single-ended input circuit of the master is connected to the slave single-ended output circuit of each slave. At this time, the clock signal (CLK signal), the master output / slave input signal (MOSI signal), and the master input / slave output signal (MISO signal) between the master and the slave are single-ended signals.
[0067] Further, when the master and the slave perform long-distance communication, the communication signals between the master and the slave need to use differential signals, which are signals with the same voltage amplitude and opposite polarity on two transmission lines and can be reference points to each other.
[0068] Specifically, as shown in Figure 3 the master, the clock output terminal includes a clock differential output circuit (CLK differential output circuit), the master output terminal includes a master differential output circuit (MOSI differential output circuit), and the master input terminal includes a master differential input circuit (MISO differential input circuit); in the slave, the clock input terminal includes a clock differential input circuit (provided at the CLK terminal of the slave), the slave input terminal includes a slave differential input circuit (provided at the MOSI terminal of the slave), and the slave output terminal includes a slave differential output circuit (provided at the MISO terminal of the slave).
[0069] The master clock differential output circuit is connected to the clock differential input circuit of each slave unit. The master clock differential output circuit converts single-ended clock signals into differential clock signals, and the slave clock differential input circuit converts differential clock signals into single-ended clock signals. The master differential output circuit is also connected to the slave differential input circuit of each slave unit. The master differential output circuit converts single-ended master output signals into differential master output signals, and the slave differential input circuit converts differential master output signals into single-ended slave input signals. Finally, the master differential input circuit converts differential signals into single-ended signals, and the slave differential output circuit converts single-ended slave output signals into differential slave output signals, and the master differential input circuit converts differential slave output signals into single-ended master input signals. After the differential input circuit converts the differential signal into a single-ended signal, the processor of either the master or slave unit can read and process the single-ended signal.
[0070] As can be seen, in this utility model, the single-ended signal that needs to travel long distance on the host or slave can be converted into a differential signal before being transmitted. When the host or slave receives the differential signal, it can be converted back into the corresponding single-ended signal for further processing. That is, the signal transmitted on the long-distance communication line between the host and slave is a differential signal. The differential signal has less attenuation and better anti-interference ability than the single-ended signal during long-distance transmission, which can effectively improve the communication stability during long-distance transmission.
[0071] Furthermore, the clock differential output circuit on the host and the host differential output circuit are located in the same differential output circuit, which can be a differential line driver. For example... Figure 4 As shown, a single-ended clock signal (CLK signal) and a single-ended host output signal (MOSI signal) can be input into the differential output circuit. The differential output circuit converts the single-ended clock signal into differential clock signals (SPI SCK P and SPI SCK N) and converts the single-ended host output signal into differential host output signals (SPI SDO P and SPI SDO N).
[0072] Alternatively, the clock differential output circuit on the host and the host differential output circuit are independent differential output circuits, which can be composed of multiple electronic components. For example... Figure 5As shown, the single-ended host output signal (MOSI signal) can be input into the differential output circuit, and the differential output circuit converts the single-ended host output signal into differential host output signals (SPI SDO P and SPI SDO N).
[0073] Further, the clock differential input circuit on the slave and the slave differential input circuit are located in the same differential input circuit, and the differential input circuit can be a differential line receiver. Figure 6 As shown, the differential clock signal (SPI SCK P and SPI SCK N) and the differential host output signal (SPI SDO P and SPI SDO N) can be input into the differential input circuit, and the differential input circuit converts the differential clock signal (SPI SCK P and SPI SCK N) into a single-ended clock signal (CLK signal) and converts the differential host output signal (SPI SDO P and SPI SDO N) into a single-ended host output signal (MOSI signal).
[0074] Alternatively, the clock differential input circuit on the slave and the slave differential input circuit are independent differential input circuits; the differential input circuit can be composed of electronic elements. Figure 7 As shown, the differential host output signal (SPI SDO P and SPI SDO N) can be input into the differential input circuit, and the differential input circuit converts the differential host output signal (SPI SDO P and SPI SDO N) into a single-ended host output signal (MOSI signal); or the differential clock signal (SPI SCK P and SPI SCK N) can be input into the differential input circuit, and the differential input circuit converts the differential clock signal (SPI SCK P and SPI SCK N) into a single-ended clock signal (CLK signal).
[0075] The utility model further provides a kind of communication device, and the communication of above-mentioned communication system based on SPI is carried out.
[0076] In the utility model, the terms "first", "second", "third" and "fourth" are only for the purpose of description, and cannot be understood as indicating or implying relative importance. The term "multiple" means two or more than two, unless otherwise explicitly limited.
[0077] The above embodiments are only used to illustrate the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the specification of the present application.
Claims
1. A slave based on SPI communication, characterized in that, The chip select input end and the chip select output end are connected with the control unit respectively, the chip select input end is used for receiving a chip select signal, and the control unit controls the chip select output end to output a chip select signal according to the chip select signal. The clock input end, the slave input end and the slave output end are connected with the control unit respectively, the clock input end is used for receiving a clock signal, the slave signal input end is used for receiving a slave input signal, and the control unit controls the slave output end to output a slave output signal according to the clock signal, the chip select signal and the slave input signal. The clock input end is a clock single-end input circuit, the slave input end is a slave single-end input circuit, and the slave output end is a slave single-end output circuit.
2. The slave according to claim 1, wherein, The clock input end is a clock differential input circuit, the slave input end is a slave differential input circuit, and the slave output end is a slave differential output circuit. The clock differential input circuit and the slave differential input circuit are located in the same differential input circuit, or the clock differential input circuit and the slave differential input circuit are independent differential input circuits.
3. The slave according to claim 2, wherein, The master and a plurality of slaves as claimed in claim 1 are included.
4. The slave according to claim 2, wherein, The master includes a chip select output end.
5. The slave of claim 4, wherein, The slave includes a chip select input end and a chip select output end.
6. A SPI-based communication system, characterized by The plurality of slaves are connected in sequence through the connection of the chip select output end and the chip select input end, and the chip select output end of the master is connected with the chip select input end of the first slave. The master further includes a clock output end, a master output end and a master input end, and the slave further includes a clock input end, a slave input end and a slave output end. The clock output end of the master is connected with the clock input end of each slave. The master output end of the master is connected with the slave input end of each slave. The master input end of the master is connected with the slave output end of each slave.
7. The communication system of claim 6, wherein, The clock output end includes a clock single-end output circuit, the master output end includes a master single-end output circuit, and the master input end includes a master single-end input circuit. The clock input end includes a clock single-end input circuit, the slave input end includes a slave single-end input circuit, and the slave output end includes a slave single-end output circuit. The clock single-end output circuit of the master is connected with the clock single-end input circuit of each slave. The master single-end output circuit of the master is connected with the slave single-end input circuit of each slave.
8. The communication system of claim 7, wherein, The master single-end input circuit of the master is connected with the slave single-end output circuit of each slave. The clock output end includes a clock differential output circuit, the master output end includes a master differential output circuit, and the master input end includes a master differential input circuit. The clock input end includes a clock differential input circuit, the slave input end includes a slave differential input circuit, and the slave output end includes a slave differential output circuit. 9. The communication system of claim 7, wherein, The clock differential output circuit of the host is connected with the clock differential input circuit of each slave; The host differential output circuit of the host is connected with the slave differential input circuit of each slave; The host differential input circuit of the host is connected with the slave differential output circuit of each slave.
10. The communication system according to claim 9, characterized in that, The clock differential output circuit and the host differential output circuit are located in the same differential output circuit, or the clock differential output circuit and the host differential output circuit are independent differential output circuits respectively; The clock differential input circuit and the slave differential input circuit are located in the same differential input circuit, or the clock differential input circuit and the slave differential input circuit are independent differential input circuits respectively.