Bidirectional variable gain amplifier and bidirectional phase shifter

Abstract

The embodiment of the utility model provides a bidirectional variable gain amplifier and a bidirectional phase shifter. The bidirectional variable gain amplifier comprises a forward node and a reverse node, the first variable gain unit is used for providing variable gain when the forward node inputs a radio frequency signal; the input end of the first variable gain unit is connected with the forward node; the first switch unit is used for connecting or disconnecting the forward node, the input end of the first variable gain unit and a first path between the output end of the first variable gain unit and the reverse node; the second variable gain unit is used for providing variable gain when the reverse node inputs the radio frequency signal; the input end of the second variable gain unit is connected with the reverse node; and the second switch unit is used for connecting or disconnecting the reverse node, the input end of the second variable gain unit and a second path between the output end of the second variable gain unit and the forward node.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of communication, and in particular to a bidirectional variable gain amplifier and a bidirectional phase shifter. BACKGROUND

[0002] The phased array technology is widely used in the fields of millimeter wave communication, radar, etc. A phased array system contains a large number of transceiver components, and the performance of the transceiver components will directly affect the performance of the phased array system. The transceiver components of the phased array system contain both a transmitting link and a receiving link, and are mainly used to realize the functions of amplifying signals, controlling the phase and amplitude of signals, etc. In the traditional transceiver components, the transmitting link and the receiving link are independent of each other, and the transmitting link and the receiving link respectively include independent variable gain amplifiers and independent phase shifters, so that the number of devices of the phased array system is relatively large, thereby causing the defects of large device size and area and large power consumption. SUMMARY

[0003] Embodiments of the present disclosure propose a bidirectional variable gain amplifier and a bidirectional phase shifter, so that the transmitting link and the receiving link can multiplex the bidirectional variable gain amplifier and the bidirectional phase shifter, thereby reducing the area of the phased array system.

[0004] In a first aspect, an embodiment of the present disclosure provides a bidirectional variable gain amplifier, comprising: a forward node and a reverse node; a first variable gain unit configured to provide variable gain when a radio frequency signal is input at the forward node; an input end of the first variable gain unit being connected to the forward node; a first switch unit configured to turn on or turn off a first path between the forward node, an input end of the first variable gain unit, an output end of the first variable gain unit and the reverse node; a second variable gain unit configured to provide variable gain when a radio frequency signal is input at the reverse node; an input end of the second variable gain unit being connected to the reverse node; and a second switch unit configured to turn on or turn off a second path between the reverse node, an input end of the second variable gain unit, an output end of the second variable gain unit and the forward node.

[0005] In a second aspect, an embodiment of the present disclosure provides a bidirectional phase shifter, comprising: a quadrature signal generator connected to a radio frequency integrated circuit, configured to convert an input signal into two-way quadrature I-channel signal and Q-channel signal, or combine the two-way quadrature I-channel signal and Q-channel signal into an output signal; a power divider connected to an antenna, configured to synthesize or distribute the I-channel signal and the Q-channel signal, and realize vector synthesis or power distribution; two bidirectional variable gain amplifiers according to any one of the first aspect, respectively configured to adjust the gain of the I-channel signal and the Q-channel signal, wherein the forward node of the bidirectional variable gain amplifier is connected to the quadrature signal generator, and the reverse node of the bidirectional variable gain amplifier is connected to the power divider.

[0006] In the scheme of the present disclosure, the bidirectional variable gain amplifier includes a forward node, a reverse node, a first switch unit, a first variable gain unit, and a second switch unit. The first variable gain unit is configured to provide variable gain when the forward node inputs a radio frequency signal; an input end of the first variable gain unit is connected with the forward node; the first switch unit is configured to turn on or turn off a first path between the forward node, the input end of the first variable gain unit, an output end of the first variable gain unit, and the reverse node; the forward node serves as a radio frequency signal input end, and the reverse node serves as a radio frequency signal input end, so as to realize a forward working mode; the second variable gain unit is configured to provide variable gain when the reverse node inputs a radio frequency signal; an input end of the second variable gain unit is connected with the reverse node; and the second switch unit is configured to turn on or turn off a second path between the reverse node, the input end of the second variable gain unit, the output end of the second variable gain unit, and the forward node; the reverse node serves as a radio frequency signal input end, and the forward node serves as a radio frequency signal input end, so as to realize a reverse working mode. The bidirectional variable gain amplifier can realize bidirectional gain adjustment, and realize signal isolation in the forward working mode and the reverse working mode through the first switch unit and the second switch unit. Such a configuration can not only reduce the chip area, but also be conducive to saving power consumption.

[0007] The bidirectional variable gain amplifier can be used in a bidirectional phase shifter, which includes a quadrature signal generator, a power divider, and two bidirectional variable gain amplifiers. The quadrature signal generator is connected with a radio frequency integrated circuit, and is configured to convert an input signal into two quadrature I signals and Q signals, or combine the two quadrature I signals and Q signals into an output signal; the power divider is connected with an antenna, and is configured to combine or distribute the I signals and the Q signals, so as to realize vector combination or power distribution; and the two bidirectional variable gain amplifiers are respectively used for gain adjustment of the I signals and the Q signals. When external signals are received from the antenna, the bidirectional variable gain amplifier is in the reverse working mode, and the signals first pass through an active structure (the bidirectional variable gain amplifier) inside the bidirectional phase shifter, and then pass through a passive structure (the quadrature signal generator) inside the bidirectional phase shifter, so as to greatly reduce the noise coefficient; when signals are transmitted to the outside through the antenna, the bidirectional variable gain amplifier is in the forward working mode, and the signals first pass through the passive structure (the quadrature signal generator) inside the bidirectional phase shifter, and then pass through the active structure (the bidirectional variable gain amplifier) inside the bidirectional phase shifter, so as to keep the noise coefficient at the level of a normal one-way active phase shifter. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A structural schematic diagram of a transceiver assembly is shown;

[0009] Figure 2 A block diagram of a bidirectional variable gain amplifier provided by an embodiment of the present disclosure is shown;

[0010] Figure 3A A structure diagram of a bidirectional variable gain amplifier provided by an embodiment of the present disclosure is shown Figure 1 ;

[0011] Figure 3B A transmission diagram of the structure shown in Figure 3A ;

[0012] Figure 4A A structure diagram of a bidirectional variable gain amplifier provided by an embodiment of the present disclosure is shown Figure 2 ;

[0013] Figure 4B A transmission diagram of the structure shown in Figure 4A ;

[0014] Figure 5A A structure diagram of a bidirectional variable gain amplifier provided by an embodiment of the present disclosure is shown

[0015] Figure 5B A transmission diagram of the structure shown in Figure 5A ;

[0016] Figure 6A A structure diagram of a bidirectional variable gain amplifier provided by an embodiment of the present disclosure is shown

[0017] Figure 6B A transmission diagram of the structure shown in Figure 6A ;

[0018] Figure 7A A structure diagram of a bidirectional variable gain amplifier provided by an embodiment of the present disclosure is shown

[0019] Figure 7B A transmission diagram of the structure shown in Figure 7A ;

[0020] Figure 8 A structure diagram of a bidirectional phase shifter provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the embodiments of the present disclosure and the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0022] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of skill in the art upon

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] The rapid development of phased array technology puts forward higher and higher requirements for the miniaturization of transceiver assemblies. In a transceiver assembly, the integration of a radio frequency front-end transceiver circuit is one of the most challenging designs. Generally, a radio frequency front-end transceiver circuit not only requires performance indicators such as a wide frequency band, low insertion loss, and high isolation, but also requires a small size to achieve high integration.

[0025] In the related art, each antenna unit in a phased array circuit is equipped with a transceiver assembly, and multiple transceiver assemblies are synthesized to obtain a phased array. Figure 1 A structure diagram of a transceiver assembly and an antenna is shown. As shown in Figure 1 The transceiver assembly includes a transmit chain and a receive chain; the transmit chain and the receive chain are switched by transceiver channel switches 101 and 108. The transmit chain includes a power amplifier 102, a phase shifter 103, and a variable gain amplifier 104; the receive chain includes a low noise amplifier 105, a phase shifter 106, and a variable gain amplifier 107. Among them, the phase shifters 103 and 106 are respectively used to realize the phase control of the transmit chain and the receive chain, the variable gain amplifiers 104 and 107 are respectively used to realize the amplitude control of the transmit chain and the receive chain, the power amplifier 102 is used to realize the signal amplification of the transmit chain, and the low noise amplifier 105 is used to realize the signal amplification of the receive chain. Figure 1 In the transceiver assembly shown in

[0026] It should be noted that in actual application, the positions of the phase shifter and the variable gain amplifier can be interchanged. Moreover, a matching circuit is usually arranged between the phase shifter and the variable gain amplifier, which is used for matching impedance between the phase shifter and the variable gain amplifier. In order to clearly show, the matching circuit is not shown in Figure 1 .

[0027] It should also be noted that the phase shifters 103 and 106 are unidirectional phase shifters, that is, the signal can only be transmitted in one direction. Among them, the phase shifter 103 is used to realize the phase control of the transmission link, and the phase shifter 106 is used to realize the phase control of the receiving link; the variable gain amplifiers 104 and 107 are unidirectional variable gain amplifiers, wherein the variable gain amplifier 104 is used to realize signal amplification of the transmission link, and the variable gain amplifier 107 is used to realize signal amplification of the receiving link.

[0028] Figure 2 A block diagram of a bidirectional variable gain amplifier provided by an embodiment of the present disclosure is shown. As shown in Figure 2 , the present disclosure provides a bidirectional variable gain amplifier, which is taken as an example in a differential structure. The bidirectional variable gain amplifier comprises forward nodes PIN1, PIN2 and reverse nodes PIN3, PIN4, wherein the forward nodes PIN1 and the reverse nodes PIN3 are positive (+) nodes, and the forward nodes PIN2 and the reverse nodes PIN4 are negative (-) nodes. The node refers to a point in a circuit that connects two or more circuit elements, which can be a physical connection point. The node is usually a place where elements (such as resistors, capacitors, inductors, diodes, etc.) in a circuit are connected by wires; in some cases, the node can also be a point artificially defined in the circuit, which can not correspond to the actual physical connection, and is only artificially defined for convenience of description. The forward nodes PIN1, PIN2 and the reverse nodes PIN3, PIN4 are used to connect the bidirectional variable gain amplifier with other circuit elements, and are used for bidirectional receiving signals or bidirectional output signals;

[0029] The first variable gain unit 210 is used to provide variable gain when the radio frequency signals are input to the forward nodes PIN1 and PIN2. The input end of the first variable gain unit 210 is connected with the forward nodes PIN1 and PIN2, which is used to receive the input signals from the forward nodes PIN1 and PIN2 and amplify them;

[0030] The first switch unit 230 is used to turn on or turn off the first path between the forward nodes PIN1 and PIN2, the input end of the first variable gain unit 210, the output end of the first variable gain unit 210 and the reverse nodes PIN3 and PIN4, which is used to output signals to the reverse nodes PIN3 and PIN4;

[0031] The second variable gain unit 220 is configured to provide variable gain when the reverse nodes PIN3 and PIN4 input the radio frequency signal; the input end of the second variable gain unit 220 is connected with the reverse nodes PIN3 and PIN4, configured to receive the input signal from the reverse nodes PIN3 and PIN4 and amplify the input signal;

[0032] The second switch unit 240 is configured to turn on or turn off the second path between the reverse nodes PIN3 and PIN4, the input end of the second variable gain unit 220, the output end of the second variable gain unit 220 and the forward nodes PIN1 and PIN2, and output the signal to the forward nodes PIN1 and PIN2.

[0033] It should be noted that the bidirectional variable gain amplifier in the embodiments of the present disclosure is taken as an example of a differential input and differential output structure for description, but the bidirectional variable gain amplifier provided by the embodiments of the present disclosure can also be a single-ended input and single-ended output structure, and when the bidirectional variable gain amplifier is a single-ended input and single-ended output structure, there can be only one forward node and one reverse node.

[0034] It should also be noted that, Figure 2 The first variable gain unit 210 and the second variable gain unit 220 in the bidirectional variable gain amplifier are only used to illustrate the inclusion relationship, and are not used to limit the connection relationship between the first variable gain unit 210 and the second variable gain unit 220. The specific connection relationship will be described in detail later.

[0035] In the embodiments of the present disclosure, the first variable gain unit 210 and the second variable gain unit 220 work “in time sharing”, realizing bidirectional transmission of the signal link. The “time sharing” work includes but is not limited to: in the A time period, the first switch unit 230 turns on the path between the output end of the first variable gain unit 210 and the reverse nodes PIN3 and PIN4, so that the first variable gain unit 210 amplifies the signal; in the B time period, the second switch unit 240 turns on the path between the output end of the second variable gain unit 220 and the forward nodes PIN1 and PIN2, so that the second variable gain unit 220 amplifies the signal.

[0036] In the scheme of the present disclosure, the bidirectional variable gain amplifier is used for signal amplification of the forward link or the reverse link as a bidirectional module, wherein the first variable gain unit 210 in the bidirectional variable gain amplifier is used for signal amplification of the forward link, and the second variable gain unit 220 is used for signal amplification of the reverse link. Here, the forward link is a link input by the forward nodes PIN1 and PIN2, passing through the first switch unit 230 and the first variable gain unit 210, and output by the reverse nodes PIN3 and PIN4, and the reverse link is a link input by the reverse nodes PIN3 and PIN4, passing through the second switch unit 240 and the second variable gain unit 220, and output by the forward nodes PIN1 and PIN2.

[0037] In the scheme of the present disclosure, the bidirectional variable gain amplifier can replace two unidirectional variable gain amplifiers, and the area of the bidirectional variable gain amplifier itself is smaller than that of the two unidirectional variable gain amplifiers. In addition, the forward nodes PIN1 and PIN2 of the bidirectional variable gain amplifier need a matching circuit with the front-stage circuit, and the reverse nodes PIN3 and PIN4 need a matching circuit with the front-stage circuit. Compared with the prior art, the circuit shown in the present disclosure can save two matching circuits, thereby saving the chip area and being beneficial to saving the power consumption. Figure 1 The circuit shown in the present disclosure can save two matching circuits, thereby saving the chip area and being beneficial to saving the power consumption.

[0038] In the embodiment of the present disclosure, the first switch unit 230 is connected between the output end of the first variable gain unit 210 and the reverse nodes PIN3 and PIN4, and is used for turning on the path between the output end of the first variable gain unit 210 and the reverse nodes PIN3 and PIN4 when the forward nodes PIN1 and PIN2 input the radio frequency signal, so that the first variable gain unit 210 amplifies the radio frequency signal input by the forward nodes PIN1 and PIN2, and the amplified radio frequency signal is output through the reverse nodes PIN3 and PIN4, and at this time, the forward working mode is realized. The second switch unit 240 is connected between the output end of the second variable gain unit 220 and the forward nodes PIN1 and PIN2, and is used for turning on the path between the output end of the second variable gain unit 220 and the forward nodes PIN1 and PIN2 when the reverse nodes PIN3 and PIN4 input the radio frequency signal, so that the second variable gain unit 220 amplifies the radio frequency signal input by the reverse nodes PIN3 and PIN4, and the amplified radio frequency signal is output through the forward nodes PIN1 and PIN2, and at this time, the reverse working mode is realized.

[0039] The first switching unit 230 is connected between the output of the first variable gain unit 210 and the reverse nodes PIN3 and PIN4, and the second switching unit 240 is connected between the output of the second variable gain unit 220 and the forward nodes PIN1 and PIN2, so that the signal will not leak from the second variable gain unit 220 in the forward working mode and the signal will not leak from the first variable gain unit 210 in the reverse working mode, thus ensuring the reliability of the circuit.

[0040] In this embodiment of the disclosure, the bidirectional variable gain amplifier further includes: a gain control node (for clarity, in...) Figure 2 (Not shown in the image), the control terminals of the first variable gain unit 210 and the second variable gain unit 220 share a gain control node. The first and second variable gain units 210 and 220 are controlled by the gain control node for gain adjustment. In other words, the gain control node can be used to control the amplification level of the signal in the forward or reverse link. The shared gain control node between the first and second variable gain units 210 and 220 reduces control switching time and the number of control bits in the control signal output by the gain control node, thereby reducing the parasitic capacitance of the first and second variable gain units and achieving high gain.

[0041] Figure 3A A schematic diagram of the structure of the bidirectional variable gain amplifier provided in the embodiments of this disclosure is shown. Figure 1 It should be noted that, Figure 3A for Figure 2 The structure of the block diagram shown is refined, combined with Figure 2 and Figure 3A As shown, the first variable gain unit 210 includes multiple first transistor sets 310, used to control the output current of the transistors in the first transistor sets 310 by changing the bias voltage of the transistors in the first transistor sets 310, thereby changing the gain of the first variable gain unit 210; the second variable gain unit 220 includes multiple second transistor sets 320, used to control the output current of the transistors in the second transistor sets 320 by changing the bias voltage of the transistors in the second transistor sets 320, thereby changing the gain of the second variable gain unit 220. It should be noted that... Figure 3A Taking the first variable gain unit 210, which includes N first transistor sets 310, and the second variable gain unit 220, which includes N second transistor sets 320, as an example, the N first transistor sets 310 can achieve N+1 levels of gain adjustment in the forward link, and the N second transistor sets 320 can achieve N+1 levels of gain adjustment in the negative link. N is an integer greater than or equal to 2. Figure 3A The transistors in it are digitally controlled transistors.

[0042] In the embodiments of the present disclosure, the N first transistor sets 310 and the N second transistor sets 320 work in parallel, the transistors in each first transistor set 310 are turned on or turned off by a respective control signal, and each first transistor set 310 is used to realize one gain step; the transistors in each second transistor set 320 are turned on or turned off by a respective control signal, and each second transistor set 320 is used to realize one gain step; the N first transistor sets 310 share Figure 2 the first switch unit 230 in the first gain control circuit 200, that is, one first switch unit 230 is used to simultaneously control whether the N first transistor sets 310 are turned on with the reverse nodes PIN3 and PIN4, thereby saving the number of switches; the N second transistor sets 320 share Figure 2 the second switch unit 240 in the second gain control circuit 200, that is, one second switch unit 240 is used to simultaneously control whether the N second transistor sets 320 are turned on with the forward nodes PIN1 and PIN2, thereby saving the number of switches. Wherein, each first transistor set in the N first transistor sets has the same structure, each second transistor set in the N second transistor sets has the same structure, that is, the number, type and connection relationship between devices in each first transistor set and each second transistor set are all the same.

[0043] In the embodiments of the present disclosure, the transistors in the first transistor set 310 can be connected in a common source manner, and the transistors in the second transistor set 320 can be connected in a common source manner, so that the gain can be improved and the parasitic phase shift can be reduced.

[0044] Figure 3ATaking a first transistor set in the N first transistor sets and a first transistor set in the N second transistor sets as examples, the first transistor set 310 includes a pair of first main transistors M1, M4 and a pair of first cross-coupled transistors M2, M3. The first main transistors M1, M4 and the first cross-coupled transistors M2, M3 are connected in common source, and the sources are grounded. The first main transistors M1, M4 and the first cross-coupled transistors M2, M3 form a cross-coupled relationship. The first transistor set 310 is controlled by the gain control nodes Da1, Db1, wherein the gates of the first main transistors M1, M4 are connected to a first control node Da1 in the gain control nodes, the gates of the first cross-coupled transistors M2, M3 are connected to a second control node Db1 in the gain control nodes, and the drains of the first main transistors M1, M4 and the drains of the first cross-coupled transistors M2, M3 are used to connect the first switch unit. The first transistor set 320 includes a pair of second main transistors M5, M8 and a pair of second cross-coupled transistors M6, M7. The second main transistors M5, M8 and the second cross-coupled transistors M6, M7 are connected in common source, and the sources are grounded. The second main transistors M5, M8 and the second cross-coupled transistors M6, M7 form a cross-coupled relationship. The second transistor set 320 is controlled by the gain control nodes Da1, Db1, wherein the gates of the second main transistors M5, M8 are connected to the first control node Da1 in the gain control nodes, the gates of the second cross-coupled transistors M6, M7 are connected to the second control node Db1 in the gain control nodes, and the drains of the second main transistors M5, M8 and the drains of the second cross-coupled transistors M6, M7 are used to connect the second switch unit.

[0045] In the embodiments of the present disclosure, the signals output by the first control node and the second control node are complementary signals, so that the number of turned-on main transistors and the number of turned-on cross-coupled transistors are complementary; and the main transistor drain and the cross-coupled transistor drain are connected, so that the connection node of the main transistor drain and the cross-coupled transistor drain has a voltage difference, thereby generating a gain.

[0046] The first variable gain unit 210 includes N first transistor sets 310, and the second variable gain unit 220 includes N second transistor sets 320, so that N first control nodes respectively output N first control signals Da1-DaN (for clarity, Figure 3A only Da1 is shown), and N second control nodes respectively output N second control signals Db1-DbN (for clarity, Figure 3AAs shown in FIG. 1, each first control signal corresponds to control one first transistor set and one second transistor set, and each second control signal corresponds to control one first transistor set and one second transistor set. For example, the first control signal Da1 and the second control signal Db1 control the first first transistor set and the first second transistor set, and the first control signal DaN and the second control signal DbN control the Nth first transistor set and the Nth second transistor set. Each first control signal controls a pair of first main transistors and a pair of second main transistors, and each second control signal controls a pair of first cross-coupled transistors and a pair of second cross-coupled transistors. For example, the first control signal Da1 controls the first main transistors M1, M4 and the second main transistors M5, M8, and the second control signal Db1 controls the first cross-coupled transistors M2, M3 and the second cross-coupled transistors M6, M7. Here, the first control signal and the second control signal can be voltage signals.

[0047] Because the embodiment is a differential structure, the first switch unit 230 includes the third transistor M11 and the fourth transistor M12 connected in common gate, and the gates of the third transistor M11 and the fourth transistor M12 share a switch control node VGN. The source of the third transistor M11 is connected to the drain of one transistor (e.g., M1) of a pair of first main transistors, the source of the fourth transistor M12 is connected to the drain of another transistor (e.g., M4) of the pair of first main transistors, the drain of the third transistor M11 is connected to the gate of one transistor (e.g., M5) of a pair of second main transistors, and the drain of the fourth transistor M12 is connected to the gate of another transistor (e.g., M8) of the pair of second main transistors. Here, the gates of the pair of second main transistors are the input terminals of the second variable gain unit. In other words, the gates of the second main transistors M5 and M8 are connected to the reverse nodes PIN3 and PIN4, specifically, the second main transistor M5 is connected to the reverse node PIN3, and the second main transistor M8 is connected to the reverse node PIN4.

[0048] Because the embodiment is a differential structure, the second switch unit 240 includes the fifth transistor M9 and the sixth transistor M10 connected in common gate, and the gates of the fifth transistor M9 and the sixth transistor M10 share a switch control node VGP. The source of the fifth transistor M9 is connected to the drain of one transistor (e.g., M5) of a pair of second main transistors, the source of the sixth transistor M10 is connected to the drain of another transistor (e.g., M8) of the pair of second main transistors, the drain of the fifth transistor M9 is connected to the gate of one transistor (e.g., M1) of a pair of first main transistors, and the drain of the sixth transistor M10 is connected to the gate of another transistor (e.g., M4) of the pair of first main transistors.

[0049] In the embodiments of the present disclosure, the signals output by the switch control node VGN and the switch control node VGP are inverse signals of each other. The switch control node VGN controls the on-off of the third transistor M11 and the fourth transistor M12, and in this way controls the on-off of the first switch unit 230; the switch control node VGP controls the on-off of the fifth transistor M9 and the sixth transistor M10, and in this way controls the on-off of the second switch unit 240. In other words, the switch control node VGN and the switch control node VGP control whether the bidirectional variable gain amplifier is used to realize signal amplification of the forward link or signal amplification of the reverse link.

[0050] Figure 3B It is shown that Figure 3A The transmission schematic diagram of the structure shown is as follows: Figure 3B As shown, the gates of the first main transistors M1, M4 and the first cross-coupled transistors M2, M3 are connected to the forward nodes PIN1, PIN2 as the input terminals of the first variable gain unit. The drains of the first main transistors M1, M4 and the first cross-coupled transistors M2, M3 are connected to the reverse nodes PIN3, PIN4 as the output terminals of the first variable gain unit. Here, the output terminals of the first variable gain unit are connected to the reverse nodes PIN3, PIN4 through the first switch unit 230. Specifically, the first main transistor M1 and the first cross-coupled transistor M2 are connected to the reverse node PIN3 through the third transistor M11, and the first main transistor M4 and the first cross-coupled transistor M3 are connected to the reverse node PIN4 through the fourth transistor M12. The third transistor M11 and the fourth transistor M12 are turned on for the forward link (as shown by the dot-dash line in FIG. 11), at which time the radio frequency signal is input from the forward nodes PIN1, PIN2, passes through the first variable gain unit 210 composed of the N first transistor set 310, the third transistor M11 and the fourth transistor M12, and is output by the reverse nodes PIN3, PIN4. Figure 3B

[0051] The gates of the second main transistors M5, M8 and the second cross-coupled transistors M6, M7 are connected to the reverse nodes PIN3, PIN4 as the input terminals of the second variable gain unit. The drains of the second main transistors M5, M8 and the second cross-coupled transistors M6, M7 are connected to the forward nodes PIN1, PIN2 as the output terminals of the second variable gain unit. Here, the output terminals of the second variable gain unit are connected to the forward nodes PIN1, PIN2 through the second switch unit 240. Specifically, the second main transistor M5 and the second cross-coupled transistor M6 are connected to the forward node PIN1 through the fifth transistor M9, and the second main transistor M8 and the second cross-coupled transistor M7 are connected to the forward node PIN2 through the sixth transistor M10. The fifth transistor M9 and the sixth transistor M10 are turned on for the reverse link (as shown by the dot-dash line in FIG. 11), at which time the radio frequency signal is input from the reverse nodes PIN3, PIN4, passes through the second variable gain unit 240 composed of the fifth transistor M9 and the sixth transistor M10, and is output by the forward nodes PIN1, PIN2. Figure 3B ​(As shown by the dashed lines in the diagram), the RF signal is input through the reverse nodes PIN3 and PIN4, passes through the second variable gain unit 220 composed of N second transistor sets 320, the fifth transistor M9, and the sixth transistor M10, and is output through the forward nodes PIN1 and PIN2. The first transistor set 310 also includes capacitors C1-C4 and resistors R1-R4, where capacitors C1-C4 are filter capacitors and resistors R1-R4 are filter resistors. Capacitors C1-C4 and resistors R1-R4 constitute the filter network of the first transistor set 310. Here, capacitors C1-C4 can also be used to isolate DC signals, and resistors R1-R4 can also be used to isolate AC signals. Similarly, the second transistor set 320 can also include capacitors C5-C8 and resistors R5-R8, the first switching unit 230 also includes capacitors C11-C12 and resistors R11-R12, and the second switching unit 240 also includes capacitors C9-C10 and resistors R9-R10, to perform filtering and isolate the corresponding DC or AC signals.

[0052] Figure 4A A schematic diagram of the structure of the bidirectional variable gain amplifier provided in the embodiments of this disclosure is shown. Figure 2 It should be noted that, Figure 4A for Figure 2 The structure of the block diagram shown is refined, combined with Figure 2 and Figure 4A As shown, the first variable gain unit 210 includes a first transistor set 410; the second variable gain unit 220 includes a second transistor set 420.

[0053] In this embodiment of the disclosure, the first transistor set 410 includes a pair of first main transistors M1' and M4' and a pair of first cross-coupled transistors M2' and M3', and the second transistor set 420 includes a pair of second main transistors M5' and M8' and a pair of second cross-coupled transistors M6' and M7'.

[0054] In this embodiment of the disclosure, the transistors (including M1', M2', M3', and M4') in the first transistor set 410 are voltage-controlled transistors, and the voltage at the control terminal of the voltage-controlled transistor is an analog voltage; the transistors (including M5', M6', M7', and M8') in the second transistor set 420 are voltage-controlled transistors.

[0055] The first control node outputs a first control signal Va, and the second control node outputs a second control signal Vb. The first main transistors M1' and M4', and the second main transistors M5' and M8' are connected to the first control signal Va. The first cross-coupled transistors M2' and M3', and the second cross-coupled transistors M6' and M7' are connected to the second control signal Vb. Here, the sum of the first control signal Va and the second control signal Vb is a fixed value. Specifically, the first control signal Va and the second control signal Vb can be voltage signals. By adjusting the voltage difference between the first control signal Va and the second control signal Vb, the first transistor set 410 or the second transistor set 420 can exhibit different gains.

[0056] The first switching unit 230 includes a third transistor M11' and a fourth transistor M12' connected by a common gate, and the gates of the third transistor M11' and the fourth transistor M12' share a switching control node VGN. The second switching unit 240 includes a fifth transistor M9' and a sixth transistor M10' connected by a common gate, and the gates of the fifth transistor M9' and the sixth transistor M10' share a switching control node VGP.

[0057] The bidirectional variable gain amplifier shown in Figure 4 also includes capacitors C1'-C12' and resistors R1'-R12' for filtering and isolating corresponding AC or DC signals.

[0058] Figure 4B It shows Figure 4A The transmission diagram of the structure shown is as follows: Figure 4B As shown, the third transistor M11' and the fourth transistor M12' conduct the forward link (as shown). Figure 4B (As shown by the dotted lines in the diagram), at this time, the RF signal is input from the forward nodes PIN1 and PIN2, passes through the first variable gain unit 210 composed of the first transistor set 410, the third transistor M11' and the fourth transistor M12', and is output from the reverse nodes PIN3 and PIN4. The fifth transistor M9' and the sixth transistor M10' conduct the reverse link (as shown by the dotted lines in the diagram). Figure 4B (As shown by the dashed line in the diagram), at this time, the radio frequency signal is input from the reverse nodes PIN3 and PIN4, passes through the second variable gain unit 220 composed of the second transistor set 420, the fifth transistor M9' and the sixth transistor M10', and is output from the forward nodes PIN1 and PIN2.

[0059] It should be noted that, Figure 4A The schematic diagram shows the first transistor set 410, the second transistor set 420, the first switching voltage 230, and the second switching unit 240. Figure 3A The connection structure of the first transistor set 310, the second transistor set 320, the first switching voltage 230, and the second switching unit 240 in each of the illustrated arrays is the same.Figure 4A The specific connection relationship of the first transistor set 410, the second transistor set 420, the first switch unit 230, and the second switch unit 240 in FIG. 10 can be understood with reference to the description of Figure 3A .

[0060] Figure 5A FIG. 3 shows a structural schematic diagram of a bidirectional variable gain amplifier provided by an embodiment of the present disclosure. It should be noted that, Figure 5A the bidirectional variable gain amplifier shown in FIG. 3 is a refinement of the block diagram shown in FIG. 10, and the description of Figure 2 and Figure 2 and Figure 5A It is shown that the first variable gain unit 210 includes a plurality of first transistor sets 510, which are used to control the size of the output current of the transistors in the first transistor set 510 by changing the size of the bias voltage of the transistors in the first transistor set 510, so as to change the gain of the first variable gain unit 210; the second variable gain unit 220 includes a plurality of second transistor sets 520, which are used to control the size of the output current of the transistors in the second transistor set 520 by changing the size of the bias voltage of the transistors in the second transistor set 520, so as to change the gain of the second variable gain unit 220. It should be noted that, Figure 5A Taking an example in which the first variable gain unit 210 includes N first transistor sets 510 and the second variable gain unit 220 includes N second transistor sets 520 for description. Figure 5A The transistors in FIG. 10 are digitally controlled transistors.

[0061] In the embodiment of the present disclosure, the N first transistor sets 510 and the N second transistor sets 520 work in parallel, the transistors in each first transistor set 510 are turned on or turned off through a respective control signal, and each first transistor set 510 is used to realize one gain step; the transistors in each second transistor set 520 are turned on or turned off through a respective control signal, and each second transistor set 520 is used to realize one gain step; the N first transistor sets 510 share the first switch unit 230; that is, one first switch unit 230 is used to simultaneously control whether the N first transistor sets 510 are turned on with the reverse nodes PIN3 and PIN4, thereby saving the number of switches; the plurality of second transistor sets 520 share the second switch unit 240, that is, one second switch unit 240 is used to simultaneously control whether the N second transistor sets 520 are turned on with the forward nodes PIN1 and PIN2, thereby saving the number of switches.

[0062] In the embodiment of the present disclosure, the transistors in the first transistor set 510 can be connected in a common source manner, and the transistors in the second transistor set 520 can be connected in a common source manner, so as to improve the gain and reduce the parasitic phase shift.

[0063] Figure 5A The first one of the N first transistor sets 510 includes a pair of first main transistors M21, M24 and a pair of first cross-coupled transistors M22, M23. The first transistor set 510 is controlled by the gain control nodes Da1, Db1, wherein one of the pair of first main transistors and the pair of first cross-coupled transistors (e.g. M21 and M22) is controlled by the first control node Da1 of the gain control nodes and the other of the pair of first main transistors and the pair of first cross-coupled transistors (e.g. M23 and M24) is controlled by the second control node Db1 of the gain control nodes. The signals outputted by the first control node and the second control node are complementary to each other. The first one of the N second transistor sets 520 includes a pair of second main transistors M25, M28 and a pair of second cross-coupled transistors M26, M27. The second transistor set 520 is controlled by the gain control nodes, wherein one of the pair of second main transistors and the pair of second cross-coupled transistors (e.g. M25 and M26) has its gate connected to the first control node Da1 of the gain control nodes and the other of the pair of second main transistors and the pair of second cross-coupled transistors (e.g. M27 and M28) has its gate connected to the second control node Db1 of the gain control nodes. The signals outputted by the first control node and the second control node are complementary to each other.

[0064] The first variable gain unit 210 includes N first transistor sets 510 and the second variable gain unit 220 includes N second transistor sets 520, whereby N first control nodes output N first control signals Da1-DaN (for clarity, only Da1 is shown) and N second control nodes output N second control signals Db1-DbN (for clarity, only Db1 is shown) respectively, the first one of the N first transistor sets 510 and the first one of the N second transistor sets 520 are coupled and share the same first control signal and the same second control signal, the second one of the N first transistor sets 510 and the second one of the N second transistor sets 520 are coupled and share the same first control signal and the same second control signal, and so on. Each first control signal corresponds to control one first transistor set and one second transistor set, and each second control signal corresponds to control one first transistor set and one second transistor set. Figure 5A Figure 5A The first variable gain unit 210 includes N first transistor sets 510 and the second variable gain unit 220 includes N second transistor sets 520, whereby N first control nodes output N first control signals Da1-DaN (for clarity, only Da1 is shown) and N second control nodes output N second control signals Db1-DbN (for clarity, only Db1 is shown) respectively, the first one of the N first transistor sets 510 and the first one of the N second transistor sets 520 are coupled and share the same first control signal and the same second control signal, the second one of the N first transistor sets 510 and the second one of the N second transistor sets 520 are coupled and share the same first control signal and the same second control signal, and so on. Each first control signal corresponds to control one first transistor set and one second transistor set, and each second control signal corresponds to control one first transistor set and one second transistor set.

[0065] ​Because the present embodiment is a differential structure, the first switch unit 230 includes the third transistor M31 and the fourth transistor M32 connected in common gate, in other words, the gates of the third transistor M31 and the fourth transistor M32 share a switch control node VGN. The drain of the third transistor M31 is connected to the source of one of the pair of first main transistors (for example, M21), the source of the fourth transistor M32 is connected to the source of the other of the pair of first main transistors (for example, M24), and the gates of the third transistor M31 and the fourth transistor M32 are further connected to the reverse nodes PIN3, PIN4. Here, the drain of the second main transistor M25 is also connected to the reverse node PIN3, and the drain of the second main transistor M28 is also connected to the reverse node PIN4.

[0066] Because the present embodiment is a differential structure, the second switch unit 240 includes the fifth transistor M29 and the sixth transistor M30 connected in common gate, in other words, the gates of the fifth transistor M29 and the sixth transistor M30 share a switch control node VGN. The drain of the fifth transistor M29 is connected to the source of one of the pair of second main transistors (for example, M25), the drain of the sixth transistor M30 is connected to the source of the other of the pair of second main transistors (for example, M28), and the gates of the fifth transistor M29 and the sixth transistor M30 are further connected to the forward nodes PIN1, PIN2, respectively. Here, the drain of the first main transistor M21 is also connected to the forward node PIN1, and the drain of the first main transistor M24 is also connected to the forward node PIN2.

[0067] In the present embodiment of the disclosure, the sources of the third transistor M31 and the fourth transistor M32 are grounded, and the sources of the fifth transistor M29 and the sixth transistor M30 are grounded. The first capacitors C21, C22 are connected between the gates of the fifth transistor M29 and the sixth transistor M30 and the corresponding forward nodes PIN1, PIN2, and the second capacitors C23, C24 are connected between the gates of the third transistor M31 and the fourth transistor M32 and the corresponding reverse nodes PIN3, PIN4, for isolating direct current signals. In addition, the bidirectional variable gain amplifier further includes resistors R21 to R28 for isolating alternating current signals and filtering.

[0068] Figure 5B The transmission schematic diagram of the structure shown is as follows: Figure 5A The transmission schematic diagram of the structure shown is as follows: Figure 5BAs shown, the drains of the first main transistors M21, M24 and the first cross-coupled transistors M22, M23 are connected to the positive nodes PIN1, PIN2 as the input terminals of the first variable gain unit. The sources of the first main transistors M21, M24 and the first cross-coupled transistors M22, M23 are connected to the negative nodes PIN3, PIN4 as the output terminals of the first variable gain unit. The first main transistor M21 and the first cross-coupled transistor M22 are connected to the negative node PIN3 through the third transistor M31, and the first main transistor M24 and the first cross-coupled transistor M23 are connected to the negative node PIN4 through the fourth transistor M32. The third transistor M31 and the fourth transistor M32 conduct the forward link (as shown by the dot-dash line in FIG. 13), and the radio frequency signal is input from the positive nodes PIN1, PIN2, passes through the first variable gain unit 210 composed of the N first transistor sets 510, the third transistor M31 and the fourth transistor M32, and is output from the negative nodes PIN3, PIN4. Figure 5B

[0069] The drains of the second main transistors M25, M28 and the second cross-coupled transistors M26, M27 are connected to the negative nodes PIN3, PIN4 as the input terminals of the second variable gain unit. The sources of the second main transistors M25, M28 and the second cross-coupled transistors M26, M27 are connected to the positive nodes PIN1, PIN2 as the output terminals of the second variable gain unit. The second main transistor M25 and the second cross-coupled transistor M26 are connected to the positive node PIN1 through the fifth transistor M29, and the second main transistor M28 and the second cross-coupled transistor M27 are connected to the positive node PIN2 through the sixth transistor M30. The fifth transistor M29 and the sixth transistor M30 conduct the reverse link (as shown by the dashed line in FIG. 14), and the radio frequency signal is input from the negative nodes PIN3, PIN4, passes through the second variable gain unit 220 composed of the N second transistor sets 520, the fifth transistor M29 and the sixth transistor M30, and is output from the positive nodes PIN1, PIN2. Figure 5B

[0070] Figure 6A It is shown that the structure of the bidirectional variable gain amplifier provided by the embodiments of the present disclosure is shown in FIG. 15, and it needs to be explained that, Figure 6A Figure 2 The structure refinement of the block diagram shown in FIG. 15 is shown in FIG. 16, in combination with Figure 2 and Figure 6A ​​​As shown, the first variable gain unit 210 includes a first transistor set 610; the second variable gain unit 220 includes a second transistor set 620. The first transistor set 610 includes a pair of first main transistors M21', M24' and a pair of first cross-coupled transistors M22', M23'; the second transistor set 620 includes a pair of second main transistors M25', M28' and a pair of second cross-coupled transistors M26', M27'.

[0071] In the embodiments of the present disclosure, the transistors in the first transistor set 610 (including M21', M22', M23', M24') are voltage-controlled transistors; the transistors in the second transistor set 620 (including M25', M26', M27', M28') are voltage-controlled transistors.

[0072] The first control node outputs a first control signal Va, and the second control node outputs a second control signal Vb; the first main transistor M21', the first cross-coupled transistor M22', the second main transistor M5' and the second cross-coupled transistor M6' are connected to the first control signal Va; the first main transistor M24', the first cross-coupled transistor M23', the second main transistor M28' and the second cross-coupled transistor M27' are connected to the second control signal Vb. Here, the sum of the first control signal Va and the second control signal Vb is a fixed value, and the first control signal Va and the second control signal Vb can be voltage signals. By adjusting the voltage difference between the first control signal Va and the second control signal Vb, the first transistor set 410 or the second transistor set 420 can exhibit different gains.

[0073] The first switch unit 230 includes the third transistor M31' and the fourth transistor M32' connected in common gate, and the gates of the third transistor M31' and the fourth transistor M32' share a switch control node VGN. The second switch unit 240 includes the fifth transistor M29' and the sixth transistor M30' connected in common gate, and the gates of the fifth transistor M29' and the sixth transistor M30' share a switch control node VGN. The gates of the fifth transistor M29' and the sixth transistor M30' are connected to the corresponding positive nodes PIN1, PIN2 through the first capacitors C21', C22', and the gates of the third transistor M31' and the fourth transistor M32' are connected to the corresponding negative nodes PIN3, PIN4 through the second capacitors C23', C24', for isolating direct current signals and filtering. The bidirectional variable gain amplifier further includes R21' to R28' for isolating alternating current signals and filtering.

[0074] Figure 6B The transmission schematic diagram of the structure shown is as follows: Figure 6A The transmission schematic diagram of the structure shown is as follows: Figure 6BAs shown, the third transistor M31' and the fourth transistor M32' conduct the forward link (as shown). Figure 6B (As shown by the dotted lines in the diagram), at this time, the RF signal is input from the forward nodes PIN1 and PIN2, passes through the first variable gain unit 210 composed of the first transistor set 610, the third transistor M31', and the fourth transistor M32', and is output from the reverse nodes PIN3 and PIN4. The sixth transistor M30' of the fifth transistor M29' conducts the reverse link (as shown by the dotted lines in the diagram). Figure 6B (As shown by the dashed line in the diagram), at this time, the radio frequency signal is input from the reverse nodes PIN3 and PIN4, passes through the second variable gain unit 220 composed of the second transistor set 620, the sixth transistor M30' of the fifth transistor M29', and is output from the forward nodes PIN1 and PIN2.

[0075] It should be noted that, and Figure 6A The first transistor set 610, the second transistor set 620, the first switching voltage 230, and the second switching unit 240 are in conjunction with Figure 5A The structures of the first transistor set 510, the second transistor set 520, the first switching voltage 230, and the second switching unit 240 are also identical. Figure 6A The specific connection relationships of the first transistor set 610, the second transistor set 620, the first switching voltage 230, and the second switching unit 240 can be referred to Figure 5A The description is for reference only, and will not be repeated here.

[0076] above Figure 3A , Figure 4A , Figure 5A and Figure 6A In the bidirectional variable gain amplifier, at least one first transistor set and at least one second transistor set share a first switching unit and a second switching unit, thereby enabling the bidirectional variable gain amplifier to switch between the forward and reverse links through the two switching units. In some embodiments, the first and second variable gain units can be variable gain amplifiers (VGAs).

[0077] Figure 7A A schematic diagram of the structure of the bidirectional variable gain amplifier provided in this embodiment is shown in Figure 5. Figure 7A As shown, the first variable gain unit 210 includes multiple first transistor sets 710; each first transistor set 710 includes a pair of first main transistors M41 and M44 and a pair of first cross-coupled transistors M42 and M43; the second variable gain unit 220 includes multiple second transistor sets 720; each second transistor set 720 includes a pair of second main transistors M45 and M48 and a pair of second cross-coupled transistors M46 and M47. It should be noted that...Figure 7A The first variable gain unit 210 includes N first transistor sets 710, and the second variable gain unit 220 includes N second transistor sets 720. N is an integer greater than or equal to 2. Figure 7A The transistor in the first variable gain unit 210 is a digital controlled transistor.

[0078] The first switch unit 230 includes a fifth transistor M49 and a sixth transistor M50 connected in common source, the drain of the fifth transistor M49 is connected to the source of the first main transistor M41 and M44, the drain of the sixth transistor M50 is connected to the source of the first cross-coupled transistor M42 and M43, and the sources of the fifth transistor M49 and the sixth transistor M50 are grounded. The second switch unit 240 includes a third transistor M51 and a fourth transistor M52 connected in common source, the drain of the third transistor M51 is connected to the source of the second main transistor M45 and M48, the drain of the fourth transistor M52 is connected to the source of the second cross-coupled transistor M46 and M47, and the sources of the third transistor M51 and the fourth transistor M52 are grounded.

[0079] In the embodiments of the present disclosure, the N first transistor sets 710 and the N second transistor sets 720 work in parallel, the transistors in each first transistor set 710 are turned on or turned off by a respective control signal, and each first transistor set 710 is used to realize one gain step; the transistors in each second transistor set 720 are turned on or turned off by a respective control signal, and each second transistor set 720 is used to realize one gain step; each first transistor set 710 corresponds to one first switch unit 230; each second transistor set 720 corresponds to one second switch unit 240. Each first transistor set in the N first transistor sets has the same structure, and each second transistor set in the N second transistor sets has the same structure, that is, the number, type and connection relationship of devices in each first transistor set and each second transistor set are the same.

[0080] Figure 7ATaking the first first transistor set of N first transistor sets and the first second transistor set of N second transistor sets as examples, the first first transistor set 710 includes a pair of first main transistors M41 and M44 and a pair of first cross-coupled transistors M42 and M43. The gates of the transistors in the first transistor set 710 are connected to the first control node VP in the gain control node. The first second transistor set 720 includes a pair of second main transistors M45 and M48 and a pair of second cross-coupled transistors M46 and M47. The gates of the transistors in the second transistor set 720 are connected to the second control node VN in the gain control node. It should be noted that the N first transistor sets 710 share one first control node VP, and the N second transistor sets 720 share one second control node VN. That is, one first control node VP is used to simultaneously control the gain of the N first transistor sets 710, and one second control node VN is used to simultaneously control the gain of the N second transistor sets 720, thus saving the number of control nodes.

[0081] The fifth transistor M49 in the first switching unit 230 and the third transistor M51 in the second switching unit 240 are controlled by the first switching control node in the switching control node, and the sixth transistor M50 in the first switching unit 230 and the fourth transistor M52 in the second switching unit 240 are controlled by the second switching control node in the switching control node.

[0082] The first switch control node outputs N first switch control signals Dx1-DxN (for clarity, ...). Figure 7A Only Dx1 is shown in the diagram. The second switch control node outputs N second switch control signals Dy1-DyN (for clarity, ...). Figure 7A Only Dy1 is shown in the diagram. Each first switch control signal and second switch control signal controls one first switch unit 230 and one second switch unit 240 respectively. For example, the first switch control signal Dx1 and the second switch control signal Dy1 control the first first switch unit and the first second switch unit, and the first switch control signal DyN and the second switch control signal DyN control the Nth first switch unit and the Nth second switch unit. Specifically, the first switch control signal Dx1 controls the third transistor M51 and the fifth transistor M49, and the second switch control signal Dy1 controls the sixth transistor M50 and the fourth transistor M52. In this embodiment, the first switch control signal and the second switch control signal can specifically be voltage signals. The signals output by the first switch control node and the second switch control node are inverted signals. In other words, the first switch control signal and the second switch control signal are inverted signals.

[0083] The gates of the first main transistors M41 and M44 and the first cross-coupled transistors M42 and M43 serve as the input terminals of the first variable gain unit and are connected to the forward nodes PIN1 and PIN2. The drains of the first main transistors M41 and M44 and the first cross-coupled transistors M42 and M43 serve as the output terminals of the first variable gain unit and are connected to the reverse nodes PIN3 and PIN4. By controlling the switching on and off of the transistors in the first switching unit through the signal output from the switching control node, current regulation can be achieved while simultaneously controlling the on / off path between the first variable gain unit and the reverse nodes PIN3 and PIN4.

[0084] The gates of the second main transistors M45 and M48 and the second cross-coupled transistors M46 and M47 serve as the input terminals of the second variable gain unit and are connected to the inverting nodes PIN3 and PIN4. The drains of the second main transistors M45 and M48 and the second cross-coupled transistors M46 and M47 serve as the output terminals of the second variable gain unit and are connected to the forward nodes PIN1 and PIN2. By controlling the switching on and off of the transistors in the second switching unit through the signal output from the switching control node, current regulation can be achieved while simultaneously controlling the on / off state of the path between the second variable gain unit and the forward nodes PIN1 and PIN2.

[0085] Figure 7B It shows Figure 7A The transmission diagram of the structure shown is as follows: Figure 7B As shown, the fifth transistor M49 and the sixth transistor M50 conduct the forward link (as shown). Figure 7B (As shown by the dotted lines in the diagram), at this time, the RF signal is input from the forward nodes PIN1 and PIN2, passes through the first variable gain unit 210 composed of N first transistor sets 710, the fifth transistor M49, and the sixth transistor M50, and is output from the reverse nodes PIN3 and PIN4. The third transistor M51 and the fourth transistor M52 conduct the reverse link (as shown by the dotted lines in the diagram). Figure 7B (As shown by the dashed line in the diagram), at this time, the radio frequency signal is input from the reverse nodes PIN3 and PIN4, passes through the second variable gain unit 220 composed of N second transistor sets 720, the third transistor M51 and the fourth transistor M52, and is output from the forward nodes PIN1 and PIN2.

[0086] Figure 7A The bidirectional variable gain amplifier shown also includes resistors R41-R48 and capacitors C41-C44 for filtering and isolating AC or DC signals.

[0087] The structure of the first switching unit and the second switching unit in the above embodiments is illustrated using a transistor as an example. The first switching unit and the second switching unit can also be composed of structures such as transmission gates.

[0088] Based on the above embodiments, the disclosure also provides a bidirectional phase shifter, Figure 8 The structure of the bidirectional phase shifter is shown in the schematic diagram. As shown in the schematic diagram, Figure 8 The bidirectional phase shifter provided by the embodiments of the disclosure includes: a quadrature signal generator 810 connected to a radio frequency integrated circuit (RFIC) for converting an input signal into two-channel orthogonal I-channel signal and Q-channel signal, or combining the two-channel orthogonal I-channel signal and Q-channel signal into an output signal; a power divider 820 connected to an antenna for synthesizing or distributing the I-channel signal and the Q-channel signal to realize vector synthesis or power distribution; a first bidirectional variable gain amplifier 830 and a second bidirectional variable gain amplifier 840 for gain adjustment of the I-channel signal and the Q-channel signal, respectively. The forward nodes of the first bidirectional variable gain amplifier 830 and the second bidirectional variable gain amplifier 840 are connected to the quadrature signal generator 810, and the reverse nodes of the first bidirectional variable gain amplifier 830 and the second bidirectional variable gain amplifier 840 are connected to the power divider 820. The first bidirectional variable gain amplifier 830 and the second bidirectional variable gain amplifier 840 can be any one of the bidirectional variable gain amplifiers in Figure 2 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A and Figure 7A .

[0089] In the embodiments of the disclosure, when the phased array system transmits a signal, the radio frequency integrated circuit is used to provide a radio frequency signal to be transmitted (input signal), and the input signal is transmitted from the first radio frequency node RFIN1 to the second radio frequency node RFIN2. At this time, the first radio frequency node RFIN1 receives the input signal, and the input signal is converted into two-channel orthogonal I-channel signal and Q-channel signal via the quadrature signal generator 810. The I-channel signal is adjusted in gain via the first bidirectional variable gain amplifier 830, and the Q-channel signal is adjusted in gain via the second bidirectional variable gain amplifier 840. The adjusted I-channel signal and Q-channel signal are vector synthesized via the power divider 820 to obtain an output signal, and the output signal is transmitted to the antenna via the second radio frequency node RFIN2.

[0090] In the embodiment of the present disclosure, when the phased array system receives a signal, the antenna transmits the received signal to the second radio frequency node RFIN2, and the signal is transmitted by the second radio frequency node RFIN2 to the first radio frequency node RFIN1. The second radio frequency node RFIN2 receives an input signal, the input signal is divided into two signals by the power divider 820, and the two signals are respectively distributed to the first bidirectional variable gain amplifier 830 and the second bidirectional variable gain amplifier 840. The two signals are respectively adjusted in gain by the first bidirectional variable gain amplifier 830 and the second bidirectional variable gain amplifier 840 to obtain adjusted I and Q signals, and the adjusted I and Q signals are vector synthesized by the quadrature signal generator 810 to obtain an output signal, and the output signal is transmitted to the radio frequency integrated circuit by the first radio frequency node RFIN1.

[0091] In the embodiment of the present disclosure, a passive poly-phase filter (PPF) can be used as the quadrature signal generator 810. The PPF has the function of bidirectional transmission of signals and can reduce the noise coefficient.

[0092] In the embodiment of the present disclosure, the bidirectional phase shifter further comprises a first transformer TF1, a second transformer TF2, a third transformer TF3, a fourth transformer TF4, and a fifth transformer TF5. The forward nodes of the first bidirectional variable gain amplifier 830 and the second bidirectional variable gain amplifier 840 are connected to the quadrature signal generator 810 through the second transformer TF2 and the third transformer TF3, and the reverse nodes of the first bidirectional variable gain amplifier 830 and the second bidirectional variable gain amplifier 840 are connected to the power divider 820 through the fourth transformer TF4 and the fifth transformer TF5. The center taps of the second transformer TF2, the third transformer TF3, the fourth transformer TF4, and the fifth transformer TF5 are connected to VDD to realize bidirectional power supply of the bidirectional phase shifter.

[0093] In the embodiments of the present disclosure, the bidirectional variable gain amplifier can be used in a bidirectional phase shifter, including a quadrature signal generator, a power divider and two bidirectional variable gain amplifiers. The quadrature signal generator is connected to a radio frequency integrated circuit, and is used to convert an input signal into two quadrature I and Q signals, or combine the two quadrature I and Q signals into an output signal; the power divider is connected to an antenna, and is used to combine or distribute the I and Q signals to realize vector combination or power distribution; the two bidirectional variable gain amplifiers are respectively used for gain adjustment of the I and Q signals. When receiving external signals from the antenna, the bidirectional variable gain amplifier is in a reverse working mode, and the signal first passes through the active structure (bidirectional variable gain amplifier) inside the bidirectional phase shifter, and then passes through the passive structure (quadrature signal generator) inside the bidirectional phase shifter, so that the noise figure is greatly reduced; when transmitting signals to the outside through the antenna, the bidirectional variable gain amplifier is in a forward working mode, and the signal first passes through the passive structure (quadrature signal generator) inside the bidirectional phase shifter, and then passes through the active structure (bidirectional variable gain amplifier) inside the bidirectional phase shifter, so that the noise figure remains at the normal level of the one-way active phase shifter.

[0094] The above merely describes the preferred embodiments of the present disclosure, and does not limit the patent scope of the present disclosure, and any equivalent structural transformation made according to the disclosure content of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A bidirectional variable gain amplifier, characterized by, The bidirectional variable gain amplifier comprises: a forward node and a reverse node; a first variable gain unit for providing variable gain when the forward node inputs a radio frequency signal; an input end of the first variable gain unit is connected with the forward node; a first switch unit for turning on or off a first path between the forward node, the input end of the first variable gain unit, an output end of the first variable gain unit and the reverse node; a second variable gain unit for providing variable gain when the reverse node inputs a radio frequency signal; an input end of the second variable gain unit is connected with the reverse node; a second switch unit for turning on or off a second path between the reverse node, the input end of the second variable gain unit, an output end of the second variable gain unit and the forward node.

2. The bidirectional variable gain amplifier of claim 1, wherein, Further comprising: the first switch unit is connected between the output end of the first variable gain unit and the reverse node, for turning on the output end of the first variable gain unit and the reverse node when the forward node inputs the radio frequency signal; the second switch unit is connected between the output end of the second variable gain unit and the forward node, for turning on the output end of the second variable gain unit and the forward node when the reverse node inputs the radio frequency signal.

3. The bidirectional variable gain amplifier of claim 2, wherein, Further comprising: a gain control node, a control end of the first variable gain unit and a control end of the second variable gain unit share the gain control node, the first variable gain unit and the second variable gain unit are controlled by the gain control node to adjust gain; the first variable gain unit comprises at least one first transistor set, for controlling the output current of the transistors in the first transistor set by changing the size of the bias voltage of the transistors in the first transistor set, to change the gain of the first variable gain unit; the second variable gain unit comprises at least one second transistor set, for controlling the output current of the transistors in the second transistor set by changing the size of the bias voltage of the transistors in the second transistor set, to change the gain of the second variable gain unit.

4. The bidirectional variable gain amplifier according to claim 3, wherein: the first transistor set comprises a pair of first main transistors; the second transistor set comprises a pair of second main transistors.

5. The bidirectional variable gain amplifier according to claim 4, wherein: the first switch unit comprises a third transistor and a fourth transistor connected in common gate, the pair of first main transistors are connected in common source; the source of the third transistor is connected with the drain of one transistor in the pair of first main transistors, the source of the fourth transistor is connected with the drain of the other transistor in the pair of first main transistors, the drain of the third transistor is connected with the gate of one transistor in the pair of second main transistors, and the drain of the fourth transistor is connected with the gate of the other transistor in the pair of second main transistors. The second switch unit includes a fifth transistor and a sixth transistor connected in common gate, and the pair of second main transistors are connected in common source; a source of the fifth transistor is connected to a drain of one transistor of the pair of second main transistors, a source of the sixth transistor is connected to a drain of another transistor of the pair of second main transistors, a drain of the fifth transistor is connected to a gate of one transistor of the pair of first main transistors, and a drain of the sixth transistor is connected to a gate of another transistor of the pair of first main transistors.

6. The bidirectional variable gain amplifier of claim 5, wherein, The first switch unit includes a third transistor and a fourth transistor connected in common gate, a drain of the third transistor is connected to a source of one transistor of the pair of first main transistors, a drain of the fourth transistor is connected to a source of another transistor of the pair of first main transistors, and gates of the third transistor and the fourth transistor are connected to the reverse node; The second switch unit includes a fifth transistor and a sixth transistor connected in common gate, a drain of the fifth transistor is connected to a source of one transistor of the pair of second main transistors, a drain of the sixth transistor is connected to a source of another transistor of the pair of second main transistors, and gates of the fifth transistor and the sixth transistor are connected to the forward node; The gates of the fifth transistor and the sixth transistor are connected to the corresponding forward node via a first capacitor, and the gates of the third transistor and the fourth transistor are connected to the corresponding reverse node via a second capacitor.

7. The bidirectional variable gain amplifier of claim 5 or 6, wherein, The first variable gain unit includes a plurality of the first transistor sets, the plurality of the first transistor sets work in parallel, and the plurality of the first transistor sets share the first switch unit; The second variable gain unit includes a plurality of the second transistor sets, the plurality of the second transistor sets work in parallel, and the plurality of the second transistor sets share the second switch unit.

8. The bidirectional variable gain amplifier of claim 5 or 6, wherein, The first variable gain unit includes one of the first transistor sets, and the transistors in the first transistor set are voltage-controlled transistors; The second variable gain unit includes one of the second transistor sets, and the transistors in the second transistor set are voltage-controlled transistors.

9. The bidirectional variable gain amplifier of claim 1, wherein, The first variable gain unit includes a plurality of first transistor sets, and the first variable gain unit realizes gain adjustment via one or more of the first transistor sets; the first transistor set includes a pair of first main transistors and a pair of first cross-coupled transistors; The second variable gain unit includes at least one of the second transistor sets, and the second variable gain unit realizes gain adjustment via two or more of the second transistor sets; the second transistor set includes a pair of second main transistors and a pair of second cross-coupled transistors. The second switch unit comprises a third transistor and a fourth transistor connected in common source, a drain of the third transistor is connected to a source of the second main transistor, a drain of the fourth transistor is connected to a source of the second cross-coupled transistor, and sources of the third transistor and the fourth transistor are grounded; The first switch unit comprises a fifth transistor and a sixth transistor connected in common source, a drain of the fifth transistor is connected to a source of the first main transistor, a drain of the sixth transistor is connected to a source of the first cross-coupled transistor, and sources of the fifth transistor and the sixth transistor are grounded.

10. A bidirectional phase shifter, characterized by, The application further discloses a radio frequency integrated circuit comprising: a quadrature signal generator connected to the radio frequency integrated circuit, for converting an input signal into two quadrature signals of I and Q, or combining two quadrature signals of I and Q into an output signal; a power divider connected to the antenna, for combining or distributing the I and Q signals to realize vector combination or power distribution; two bidirectional variable gain amplifiers according to any one of claims 1 to 9, respectively used for gain adjustment of the I and Q signals, the forward nodes of the bidirectional variable gain amplifiers being connected to the quadrature signal generator, and the reverse nodes of the bidirectional variable gain amplifiers being connected to the power divider.

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