Packaging piece and memory
By integrating the multiplexer and bare die into the same molding compound, the problem of large board space occupation in existing memory is solved, achieving higher integration rate and smaller package size.
Patent Information
- Application Number
- CN202423221114.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2034-12-24
AI Technical Summary
In existing memory systems, the separate packaging of the controller, multiplexer, and bare die results in a large footprint on the circuit board and increases packaging costs.
The multiplexer and bare die are packaged in the same plastic layer to form an integrated package, reducing the space occupied on the circuit board.
It reduces the space occupied by the package on the circuit board, improves the integration rate, and saves circuit board space to facilitate the installation of more electronic components.
Smart Images
Figure CN223639445U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of storage, in particular to a package and a memory. BACKGROUND
[0002] The memory usually comprises a controller and a memory chip, the memory chip comprises a plurality of dies, which can be referred to as memory dies, the controller and the plurality of dies are coupled through a data bus (i.e. DQ line), in order to reduce the load of the data bus, some existing memories add a multiplexer between the controller and the plurality of dies, one end of the multiplexer is coupled to the data bus, and the other end is provided with a plurality of pin ends, each pin end is coupled to a corresponding die, the controller determines a target die according to the obtained physical address, and only turns on the target die through the corresponding pin end of the multiplexer, while turning off other dies.
[0003] In the existing memory, the controller and the memory chip are respectively pre-singulated package to protect them, similarly, in order to protect the added multiplexer, the multiplexer also needs to be molded, but this will occupy a larger circuit board space. CONTENT OF THE UTILITY MODEL
[0004] In view of this, the present application provides a package and a memory, which can improve the problem that the package occupies a larger circuit board space due to the multiplexer.
[0005] The package provided by the present application comprises:
[0006] A circuit board, provided with a data bus;
[0007] At least one die, coupled to the circuit board;
[0008] A multiplexer, comprising a first pin end and a plurality of second pin ends, the first pin end is coupled to the data bus, and each second pin end is coupled to a corresponding die through the circuit board;
[0009] A molding layer, provided on the circuit board and covering the multiplexer and the die.
[0010] Optionally, the multiplexer is provided on the circuit board and spaced apart from the die.
[0011] Optionally, the package comprises a single die;
[0012] The multiplexer is provided on the die; the multiplexer further comprises a plurality of leads, each lead couples a corresponding second pin end to the circuit board.
[0013] Optionally, the die is a control die.
[0014] Optionally, the package comprises a plurality of dies stacked on the circuit board.
[0015] The multiplexer is disposed on the stacked dies; the multiplexer further comprises a plurality of leads, each of the leads coupling the corresponding second pin end to the circuit board.
[0016] Optionally, the die is a memory die.
[0017] Optionally, the package comprises a first die and a plurality of second dies, the first die is disposed on the circuit board, and the plurality of second dies are stacked on the circuit board.
[0018] The multiplexer is disposed on the circuit board, and the multiplexer, the first die, and the stacked second dies are disposed in pairs.
[0019] Optionally, the package comprises a first die and a plurality of second dies, the first die is disposed on the circuit board and coupled to a data bus of the circuit board, and the plurality of second dies are stacked on the circuit board; the multiplexer is disposed on the first die or the stacked second dies; the first pin end is coupled to the data bus, and each of the second pin ends is coupled to the corresponding second die through the circuit board.
[0020] Optionally, the first die is a control die, and the second die is a memory die.
[0021] Optionally, the multiplexer is bonded with the die located thereunder.
[0022] The application provides a memory comprising the package as claimed in any one of the preceding embodiments.
[0023] As described above, in the package and the memory of the application, the multiplexer and the die are encapsulated in the same plastic layer, which can reduce the space occupied by the multiplexer and the die after final encapsulation, thereby reducing the space occupied on the circuit board. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 is a structural schematic diagram of a package of a first embodiment of the application;
[0025] Figure 2 is a circuit equivalent schematic diagram of a memory provided by the embodiments of the application;
[0026] Figure 3 is a structural schematic diagram of a package of a second embodiment of the application;
[0027] Figure 4 is a structural schematic diagram of a package of a third embodiment of the present application;
[0028] Figure 5 is a structural schematic diagram of a package of a fourth embodiment of the present application;
[0029] Figure 6 is a structural schematic diagram of a package of a fifth embodiment of the present application;
[0030] Figure 7 is a structural schematic diagram of a package of a sixth embodiment of the present application;
[0031] Figure 8 is a structural schematic diagram of a package of a seventh embodiment of the present application.
[0032] Package 1, circuit board 11, first surface 11a, second surface 11b, data bus 111, controller 12, bare die 121, control bare die 121, first bare die 121, multiplexer 13, first lead 130, first pin end 131, second pin end 132, adhesive 133, second lead 134, plastic encapsulation layer 14, memory chip 15, bare die 151, memory bare die 151, second bare die 151. DETAILED DESCRIPTION
[0033] To solve the above problems in the prior art, in the package and the memory of the present application, the multiplexer and the bare die are encapsulated in the same plastic encapsulation layer, without additional plastic encapsulation, thereby reducing the occupied circuit board space and the plastic encapsulation cost.
[0034] Among them, the multiplexer is not plastic encapsulated with the bare die in the plastic encapsulation layer, in addition, the shape, number, size, etc. of any of the multiplexer, bare die, circuit board and plastic encapsulation layer can be adapted according to actual needs, which is not limited by the present application.
[0035] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly below in combination with specific embodiments and corresponding drawings. Obviously, the following described embodiments are only part of the embodiments of the present application, not all the embodiments. In the case of no conflict, the following various embodiments and their technical features can be combined with each other, and also belong to the technical scheme of the present application.
[0036] First embodiment
[0037] Figure 1 is a structural schematic diagram of a package of a first embodiment of the present application, Figure 2 is a circuit equivalent schematic diagram of a memory provided by the present application. Referring to Figure 1 and Figure 2As shown, the package 1 comprises a circuit board 11, a bare die 121, a multiplexer 13 and a plastic encapsulation layer 14.
[0038] The circuit board 11 is provided with a data bus 111, which is used at least for coupling the controller 12 of the memory with the multiplexer 13. The bare die 121 is coupled to the circuit board 11, for example, can be mounted on the first surface 11a of the circuit board 11 by SMT (Surface Mounted Technology) and coupled with the data bus 111 of the circuit board 11, and the bare die 121 can also be called a control bare die 121. Correspondingly, the package 1 of the embodiment can be regarded as a controller 12 integrated with a multiplexer 13, for example, a multiplexer 13 integrated in a commonly said CPU (Central Processing Unit).
[0039] The circuit board 11 has a first surface 11a and a second surface 11b oppositely arranged along the thickness direction of the circuit board 11. According to the placement orientation of the circuit board 11 in the actual scene, the first surface 11a can be called the upper surface 11a, and the second surface 11b can be called the lower surface 11b. The circuit board 11 includes but is not limited to a PCB (Printed Circuit Board) and other types of circuit boards, which have multiple layers of wiring (i.e. copper cladding) inside. The adjacent two layers of wiring are insulated by the material of the circuit board 11, and the different layers of wiring are coupled by vias and conductive pillars arranged in the vias, that is, the so-called interlayer coupling. Based on this, the specific form of the data bus 111 can be adapted according to the wiring design of the circuit board 11.
[0040] The multiplexer 13 is arranged on the circuit board 11 and is spaced apart from the bare die 121. The so-called spaced apart means that the minimum distance between the two main bodies is not equal to zero, that is, the two are not in contact.
[0041] The multiplexer 13 comprises a first pin end 131 and a plurality of second pin ends 132, which are respectively coupled with the circuit board 11. Specifically, the first pin end 131 is coupled with the data bus 111 of the circuit board 11, and each second pin end 132 is coupled with the bare die 121 through the wiring of the circuit board 11. Figure 2 As shown, the storage chip 15 is coupled. The storage chip 15 includes but is not limited to a flash memory chip, and each bare die 151 contained therein can be called a storage bare die 151.
[0042] The number of bare dies 151 contained in the storage chip 15 can be equal to the number of second pin ends 132 in the multiplexer 13, such as Figure 2As shown, four second pin ends 132 are coupled to four dies 151 one by one, and the controller 12 determines the target die 151 according to the acquired physical address, and only turns on the target die 151 through each second pin end 132 of the multiplexer 13, while turning off other dies 151. For example, when the first die 151 is determined as the target die 151, the multiplexer 13 turns on the coupling path between the first pin end 131 and the first second pin end 132, so that the first die 151 is turned on with the data bus 111, while the coupling between the first pin end 131 and the remaining three second pin ends 132 is turned off, so that the remaining three dies 151 are in a disconnected state with the data bus 111.
[0043] The plastic sealing layer 14 is arranged on the circuit board 11, and the plastic sealing layer 14 covers the multiplexer 13 and all the dies 121. Based on this, the multiplexer 13 and the dies 121 are packaged in the same plastic sealing layer 14, so that the entire package 1 is realized as a device that can be produced, sold, transported and assembled independently. Compared with separately packaging the dies 121 and the multiplexer 13, the present application can make the circuit board space occupied by the final package 1 smaller; in other words, the circuit board 11 can save more space to mount more electronic components, improving the integration rate.
[0044] The so-called circuit board space refers to the area reserved on the surface (for example, the first surface 11a) of the circuit board 11 for mounting electronic components. That is, the circuit board space can be regarded as the surface area of the circuit board 11.
[0045] Second embodiment
[0046] Figure 3 is a structural schematic diagram of the package of the second embodiment of the present application. For the same name of the structural element, the same label is adopted for identification in the present application. For reference Figure 2 and Figure 3 As shown in the foregoing description of the first embodiment, the difference is that the package 1 of the present embodiment can be regarded as a storage chip 15 integrated with the multiplexer 13, and the storage chip 15 is provided with a plurality of dies 151, also known as storage dies 151. The four dies 151 shown in the figure are only exemplary display and do not constitute a limitation on the protection scope of the present application. The storage chip 15 includes but is not limited to a flash memory chip, and correspondingly, the storage die 151 is a flash memory die of an adaptive type.
[0047] The dies 151 are stacked on the first surface 11a of the circuit board 11.
[0048] In the storage chip 15 of the embodiment, the multiplexer 13 and the bare chip 151 are packaged in the same plastic package layer 14, so that the entire storage chip 15 is realized as a device that can be produced, sold, transported and assembled individually, and occupies a smaller space, thereby reducing the occupied space of the circuit board.
[0049] Third Embodiment
[0050] Figure 4 is a structural schematic diagram of the package of the third embodiment of the application. Referring to Figure 2 and Figure 4 together, the package 1 of the embodiment is still the controller 12 integrated with the multiplexer 13, the only bare chip 121 of the controller 12 is a control bare chip, and based on the description of the first embodiment, the difference is that the multiplexer 13 is arranged on the bare chip 121, and the multiplexer 13 further includes a first lead 130, one end of the first lead 130 is coupled with the first pin end 131, and the other end of the first lead 130 is coupled with the data bus 111 of the circuit board 11. Based on the coupling of the bare chip 121 and the data bus 111 of the circuit board 11, the coupling between the bare chip 121 and the first pin end 131 of the multiplexer 13 can be realized.
[0051] In the package 1 of the embodiment, the multiplexer 13 and the bare chip 121 are packaged in the same plastic package layer 14, so that the entire package 1 can also reduce the occupied space of the circuit board. Moreover, the multiplexer 13 and the bare chip 121 are stacked, which can further reduce the occupied space of the circuit board after packaging.
[0052] In an example, the multiplexer 13 and the bare chip 121 can be provided with an adhesive 133, such as a DAF (Die Attach Film, die attach film) adhesive, the adhesive 133 is used to realize the adhesion between the multiplexer 13 and the bare chip 121, so as to maintain the relative stability between the multiplexer 13 and the bare chip 121, and in the process of injection molding the plastic package layer 14, the multiplexer 13 can be prevented from being offset and dislocated relative to the bare chip 121.
[0053] Fourth Embodiment
[0054] Figure 5 is a structural schematic diagram of the package of the fourth embodiment of the application. Referring to Figure 2 and Figure 5As shown in FIG. 1 and FIG. 2, the package 1 of the present embodiment is still a storage chip 15 integrated with a multiplexer 13, which is provided with a plurality of dies 151, which can also be referred to as storage dies 151. These dies 151 are stacked on the circuit board 11. Based on the description of the second embodiment, the difference is that the multiplexer 13 is arranged on the stacked dies 151, i.e., on the uppermost die 151; the multiplexer 13 further includes a plurality of second leads 134, one end of each second lead 134 is coupled with a corresponding second pin end 132, and the other end of each second lead 134 is coupled with a corresponding die 151 through the circuit board 11, thereby realizing the selective coupling between the multiplexer 13 and the storage chip 15.
[0055] In the storage chip 15 of the present embodiment, the multiplexer 13 and the dies 151 are packaged in the same plastic package layer 14, which can further reduce the circuit board space occupied by the entire storage chip 15. Moreover, the multiplexer 13 and the dies 151 are stacked, which can further reduce the circuit board space occupied after packaging.
[0056] In an example, the multiplexer 13 and the first die 151 located thereunder can be provided with an adhesive 133, such as DAF glue, to realize the bonding therebetween, so as to maintain the relative stability between the multiplexer 13 and the die 151, and to avoid the displacement of the multiplexer 13 relative to the die 151 during the process of injection molding of the plastic package layer 14.
[0057] Fifth Embodiment
[0058] Figure 6 FIG. 1 is a structural schematic diagram of a package according to a fifth embodiment of the present application. FIG. 2 is a structural schematic diagram of a package according to a sixth embodiment of the present application. Figure 2 and Figure 6 As shown in FIG. 1 and FIG. 2, the package 1 of the present embodiment is still a storage chip 15 integrated with a multiplexer 13, which is provided with a plurality of dies 151, which can also be referred to as storage dies 151. These dies 151 are stacked on the circuit board 11. Based on the description of the second embodiment, the difference is that the multiplexer 13 is arranged on the stacked dies 151, i.e., on the uppermost die 151; the multiplexer 13 further includes a plurality of second leads 134, one end of each second lead 134 is coupled with a corresponding second pin end 132, and the other end of each second lead 134 is coupled with a corresponding die 151 through the circuit board 11, thereby realizing the selective coupling between the multiplexer 13 and the storage chip 15.
[0059] The circuit board 11 can be provided with a data bus 111.
[0060] The first die 121 and the plurality of second dies 151 are coupled to the circuit board 11, as shown in FIG. 1 and FIG. 2. The first die 121 can be directly SMT mounted on the first surface 11a of the circuit board 11, and the first die 121 is coupled with the data bus 111 of the circuit board 11, which can be the control die 121 described in the corresponding embodiments; and the plurality of second dies 151 are stacked on the circuit board 11, and only the lowermost one of the second dies 151 can be directly SMT mounted on the first surface 11a of the circuit board 11, and the second dies 151 can be the storage dies 151 described in the corresponding embodiments. Figure 6 The first die 121 and the plurality of second dies 151 are coupled to the circuit board 11, as shown in FIG. 1 and FIG. 2. The first die 121 can be directly SMT mounted on the first surface 11a of the circuit board 11, and the first die 121 is coupled with the data bus 111 of the circuit board 11, which can be the control die 121 described in the corresponding embodiments; and the plurality of second dies 151 are stacked on the circuit board 11, and only the lowermost one of the second dies 151 can be directly SMT mounted on the first surface 11a of the circuit board 11, and the second dies 151 can be the storage dies 151 described in the corresponding embodiments.
[0061] The multiplexer 13 is disposed on the circuit board 11 and is spaced apart from the first die 121 and the stacked second dies 151.
[0062] The multiplexer 13 includes a first pin end 131 and a plurality of second pin ends 132, the number of the second dies 151 of the storage chip 15 can be equal to the number of the second pin ends 132, the first pin end 131 is coupled with the data bus 111 of the circuit board 11, and each second pin end 132 is coupled with a corresponding second die 151 through a wire of the circuit board 11.
[0063] The plastic sealing layer 14 is disposed on the circuit board 11, and the plastic sealing layer 14 covers the multiplexer 13, the first die 121, and all the stacked second dies 151. Based on this, the multiplexer 13, the control die 121, and the storage dies 151 are all encapsulated in the same plastic sealing layer 14, so that the entire package 1 can simultaneously integrate the functions of the controller 12, the storage chip 15, and the multiplexer 13, and realize a device that can be produced, sold, transported, and assembled separately. Compared with separately packaging the three, the package 1 ultimately obtained by the application occupies less space, thereby reducing the occupied circuit board space.
[0064] In actual scenarios, the package 1 of the embodiment can be an eMMC (embedded Multi Media Card) chip or a UFS (Universal Flash Storage) chip.
[0065] Sixth Embodiment
[0066] Figure 7 is a structural schematic diagram of a package of the sixth embodiment of the application. Referring to Figure 2 and Figure 7 together, the package 1 of the embodiment can simultaneously integrate the functions of the controller 12, the storage chip 15, and the multiplexer 13. Based on the description of the foregoing fifth embodiment, the difference is that the multiplexer 13 of the embodiment is disposed on the first die (i.e., the control die) 121, and an adhesive 133 such as DAF glue can be used to bond the two.
[0067] The multiplexer 13 further comprises a first lead line 130, one end of the first lead line 130 is coupled with the first pin end 131, and the other end of the first lead line 130 is coupled with the data bus 111 of the circuit board 11, based on the coupling between the first die 121 and the data bus 111 of the circuit board 11, the coupling between the first die 121 and the first pin end 131 of the multiplexer 13 can be realized.
[0068] In the package 1 of the present embodiment, the multiplexer 13 and the first die 121 are stacked, which can further reduce the circuit board space occupied by the package 1.
[0069] Seventh Embodiment
[0070] Figure 8 is a structural schematic diagram of a package according to the seventh embodiment of the present application. As shown in Figure 2 and Figure 8 The multiplexer 13 can be disposed on the stacked second dies 151, and the multiplexer 13 and the first second die 151 located thereunder can be adhered by an adhesive 133 such as DAF glue. The multiplexer 13 further comprises a plurality of second lead lines 134, one end of each second lead line 134 is coupled with a corresponding second pin end 132, and the other end of each second lead line 134 is coupled with a corresponding die 151 through the circuit board 11, thereby realizing the selective coupling between the multiplexer 13 and the memory chip 15.
[0071] In the package 1 of the present embodiment, the multiplexer 13 and the plurality of second dies 151 are stacked, which can further reduce the circuit board space occupied by the package 1.
[0072] For any of the first embodiment, the second embodiment and the fifth embodiment described above, the multiplexer 13 can be coupled to the circuit board 11 by a chip face-down mounting process, for example, the multiplexer 13 comprises a first device surface and a second device surface opposite to each other along the thickness direction of the multiplexer 13, the first device surface faces the circuit board 11, and the plurality of second pin ends 132 protrude from the first device surface or a side surface adjacent to the first device surface and are coupled with the circuit board 11.
[0073] In other examples, the multiplexer 13 can be coupled to the circuit board 11 by a chip flip chip process, for example, the plurality of second pin ends 132 of the multiplexer 13 protrude from the second device surface or a side surface adjacent to the second device surface; since there is a height difference between the second pin ends 132 and the mounting surface (for example, the first surface 11a) of the circuit board 11 when the chip flip chip process is used, the multiplexer 13 can be provided with a plurality of flying lines to couple each second pin end 132 with the circuit board 11.
[0074] The application further provides a memory comprising the package 1 of any of the preceding embodiments, thus producing the advantageous effects produced by the package 1 of the corresponding embodiments.
[0075] The application does not limit the specific type of the memory, and in addition, the circuit board 11 of the package 1 can be part of the circuit board of the memory, or can be independent of the circuit board of the memory. The circuit board 11 of the package 1 can be referred to as a sub-circuit board, and the circuit board of the memory can be referred to as a main circuit board. The application does not limit the positional relationship between the sub-circuit board and the main circuit board, for example, the sub-circuit board can be smaller, and the main circuit board can be larger. The sub-circuit board can be stacked on the main circuit board.
[0076] The above only describes some embodiments of the application, and does not limit the patent scope of the application. For those skilled in the art, any equivalent structural transformation made by using the content of the specification and the drawings is also included in the patent protection scope of the application.
[0077] In the description of the embodiments of the application, the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the technical solutions of the corresponding embodiments, and do not indicate or imply that the device or element must have a particular orientation, be constructed and operated in a particular orientation, and cannot be understood as limiting the application.
[0078] Although the terms "first", "second", and the like are used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. In addition, the singular forms "a", "an" and "the" are intended to include plural forms. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.
Claims
1. A package, characterized by The package comprises: a circuit board; at least one die coupled to the circuit board; a multiplexer comprising a first pin coupled to the circuit board and a plurality of second pins, the first pin and / or the second pins being coupled to corresponding dies through the circuit board; a plastic encapsulation layer disposed on the circuit board and covering the multiplexer and the dies.
2. The package of claim 1, wherein, The multiplexer is disposed on the circuit board and is spaced apart from each of the dies.
3. The package of claim 1, wherein: the package comprises a single die coupled to a data bus of the circuit board; the multiplexer is disposed on the die; and 4. The package of claim 3, wherein, the multiplexer further comprises a first lead coupled at one end to the first pin and at another end to the data bus. The die is a control die.
5. The package of claim 1, wherein: the package comprises a plurality of dies stacked on the circuit board; 6. The package of claim 5, wherein, the multiplexer is disposed on the stacked dies; and the multiplexer further comprises a plurality of second leads, each of the second leads being coupled at one end to a corresponding second pin and at another end to a corresponding die through the circuit board. The die is a memory die.
7. The package of claim 1, wherein:
8. The package of claim 7, wherein, the package comprises a first die disposed on the circuit board and coupled to a data bus of the circuit board and a plurality of second dies stacked on the circuit board; 9. The package of any one of claims 3 to 8, wherein, the multiplexer is disposed on the first die or the stacked second dies; and 10. A memory, comprising: the first pin is coupled to the data bus and each of the second pins is coupled to a corresponding second die through the circuit board. The first die is a control die and the second dies are memory dies. The multiplexer is bonded to a die located thereunder. The package of any one of claims 1 to 9.